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[/] [openarty/] [trunk/] [rtl/] [lleqspi.v] - Blame information for rev 8

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///////////////////////////////////////////////////////////////////////////
//
// Filename:    lleqspi.v
//
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
//              to/from a Quad SPI port.  The port is understood to be 
//              a normal SPI port unless the driver requests four bit mode.
//              When not in use, unlike our previous SPI work, no bits will
//              toggle.
//
// Creator:     Dan Gisselquist
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
`define EQSPI_IDLE      3'h0
`define EQSPI_START     3'h1
`define EQSPI_BITS      3'h2
`define EQSPI_READY     3'h3
`define EQSPI_HOLDING   3'h4
`define EQSPI_STOP      3'h5
`define EQSPI_STOP_B    3'h6
`define EQSPI_RECYCLE   3'h7
 
// Modes
`define EQSPI_MOD_SPI   2'b00
`define EQSPI_MOD_QOUT  2'b10   // Write
`define EQSPI_MOD_QIN   2'b11   // Read
 
module  lleqspi(i_clk,
                // Module interface
                i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
                        o_word, o_valid, o_busy,
                // QSPI interface
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
        input                   i_clk;
        // Chip interface
        //      Can send info
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
        //                      i_word = { 1'b0, 32'info to send },
        //                      i_len = # of bytes in word-1
        input                   i_wr, i_hold;
        input           [31:0]   i_word;
        input           [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
        input                   i_spd; // 0 -> normal QPI, 1 -> QSPI
        input                   i_dir; // 0 -> read, 1 -> write to SPI
        input                   i_recycle; // 0 = 20ns, 1 = 50ns
        output  reg     [31:0]   o_word;
        output  wire            o_valid;
        output  reg             o_busy;
        // Interface with the QSPI lines
        output  reg             o_sck;
        output  reg             o_cs_n;
        output  reg     [1:0]    o_mod;
        output  reg     [3:0]    o_dat;
        input           [3:0]    i_dat;
 
        // output       wire    [22:0]  o_dbg;
        // assign       o_dbg = { state, spi_len,
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
 
        wire    i_miso;
        assign  i_miso = i_dat[1];
 
        // These are used in creating a delayed input.
        reg             rd_input, rd_spd, rd_valid;
 
        reg             r_spd, r_dir;
        reg     [3:0]    r_recycle;
        reg     [5:0]    spi_len;
        reg     [31:0]   r_word;
        reg     [30:0]   r_input;
        reg     [2:0]    state;
        initial state = `EQSPI_IDLE;
        initial o_sck   = 1'b1;
        initial o_cs_n  = 1'b1;
        initial o_dat   = 4'hd;
        initial rd_valid = 1'b0;
        initial o_busy  = 1'b0;
        initial r_input = 31'h000;
        initial rd_valid = 1'b0;
        always @(posedge i_clk)
        begin
                rd_input <= 1'b0;
                rd_spd   <= r_spd;
                rd_valid <= 1'b0;
 
                if ((state == `EQSPI_IDLE)&&(o_sck))
                begin
                        o_cs_n <= 1'b1;
                        o_busy  <= 1'b0;
                        o_mod <= `EQSPI_MOD_SPI;
                        r_word <= i_word;
                        r_spd <= i_spd;
                        r_dir <= i_dir;
                        o_dat <= 4'hc;
                        r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                        o_sck <= 1'b1;
                        if (i_wr)
                        begin
                                state <= `EQSPI_START;
                                o_cs_n <= 1'b0;
                                o_busy <= 1'b1;
                        end
                end else if (state == `EQSPI_START)
                begin // We come in here with sck high, stay here 'til sck is low
                        o_sck <= 1'b0;
                        if (o_sck == 1'b0)
                        begin
                                state <= `EQSPI_BITS;
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
                                if (r_spd)
                                        r_word <= { r_word[27:0], 4'h0 };
                                else
                                        r_word <= { r_word[30:0], 1'b0 };
                        end
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                                o_dat <= r_word[31:28];
                        else
                                o_dat <= { 3'b110, r_word[31] };
                end else if (~o_sck)
                begin
                        o_sck <= 1'b1;
                        o_busy <= ((state != `EQSPI_READY)||(~i_wr));
                end else if (state == `EQSPI_BITS)
                begin
                        // Should enter into here with at least a spi_len
                        // of one, perhaps more
                        o_sck <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                r_word <= { r_word[27:0], 4'h0 };
                                spi_len <= spi_len - 6'h4;
                                if (spi_len == 6'h4)
                                        state <= `EQSPI_READY;
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                r_word <= { r_word[30:0], 1'b0 };
                                spi_len <= spi_len - 6'h1;
                                if (spi_len == 6'h1)
                                        state <= `EQSPI_READY;
                        end
 
                        rd_input <= 1'b1;
                end else if (state == `EQSPI_READY)
                begin
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        // This is the state on the last clock (both low and
                        // high clocks) of the data.  Data is valid during
                        // this state.  Here we chose to either STOP or
                        // continue and transmit more.
                        o_sck <= (i_hold); // No clocks while holding
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state <= `EQSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        // spi_len <= spi_len - 4;
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h4;
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
                                                - 6'h1;
                                end
 
                                // Read a bit upon any transition
                                rd_input <= 1'b1;
                                rd_valid <= 1'b1;
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
                                o_busy <= (~i_hold);
 
                                // Read a bit upon any transition
                                rd_valid <= 1'b1;
                                rd_input <= 1'b1;
                        end
                end else if (state == `EQSPI_HOLDING)
                begin
                        // We need this state so that the o_valid signal
                        // can get strobed with our last result.  Otherwise
                        // we could just sit in READY waiting for a new command.
                        //
                        // Incidentally, the change producing this state was
                        // the result of a nasty race condition.  See the
                        // commends in wbqspiflash for more details.
                        //
                        rd_valid <= 1'b0;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b0;
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state  <= `EQSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck  <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        spi_len<= { 1'b0, i_len, 3'b100 };
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b111 };
                                end
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
                                o_busy <= (~i_hold);
                        end
                end else if (state == `EQSPI_STOP)
                begin
                        o_sck   <= 1'b1; // Stop the clock
                        rd_valid <= 1'b0; // Output may have just been valid, but no more
                        o_busy  <= 1'b1; // Still busy till port is clear
                        state <= `EQSPI_STOP_B;
                        // Can't change modes for at least one cycle
                        // o_mod <= `EQSPI_MOD_SPI;
                end else if (state == `EQSPI_STOP_B)
                begin
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        // Do I need this????
                        // spi_len <= 3; // Minimum CS high time before next cmd
                        state <= `EQSPI_RECYCLE;
                        o_busy <= 1'b1;
                        o_mod <= `EQSPI_MOD_SPI;
                end else begin // Recycle state
                        r_recycle <= r_recycle - 1'b1;
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        o_busy <= 1'b1;
                        o_mod <= `EQSPI_MOD_SPI;
                        o_dat <= 4'hc;
                        if (r_recycle[3:1] == 3'h0)
                                state <= `EQSPI_IDLE;
                end
                /*
                end else begin // Invalid states, should never get here
                        state   <= `EQSPI_STOP;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b1;
                        o_cs_n  <= 1'b1;
                        o_sck   <= 1'b1;
                        o_mod   <= `EQSPI_MOD_SPI;
                        o_dat   <= 4'hd;
                end
                */
        end
 
        always @(posedge i_clk)
        begin
                if ((state == `EQSPI_IDLE)||(rd_valid))
                        r_input <= 31'h00;
                else if ((rd_input)&&(r_spd))
                        r_input <= { r_input[26:0], i_dat };
                else if (rd_input)
                        r_input <= { r_input[29:0], i_miso };
 
                if ((rd_valid)&&(r_spd))
                        o_word  <= { r_input[27:0], i_dat };
                else if (rd_valid)
                        o_word  <= { r_input[30:0], i_miso };
        end
 
        assign  o_valid = rd_valid;
 
endmodule
 

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[/] [openarty/] [trunk/] [rtl/] [lleqspi.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	3	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: lleqspi.v`
4			`//`
5			`// Project: Wishbone Controlled Quad SPI Flash Controller`
6			`//`
7			`// Purpose: Reads/writes a word (user selectable number of bytes) of data`
8			`// to/from a Quad SPI port. The port is understood to be`
9			`// a normal SPI port unless the driver requests four bit mode.`
10			`// When not in use, unlike our previous SPI work, no bits will`
11			`// toggle.`
12			`//`
13			`// Creator: Dan Gisselquist`
14			`// Gisselquist Technology, LLC`
15			`//`
16			`///////////////////////////////////////////////////////////////////////////`
17			`//`
18			`// Copyright (C) 2015-2016, Gisselquist Technology, LLC`
19			`//`
20			`// This program is free software (firmware): you can redistribute it and/or`
21			`// modify it under the terms of the GNU General Public License as published`
22			`// by the Free Software Foundation, either version 3 of the License, or (at`
23			`// your option) any later version.`
24			`//`
25			`// This program is distributed in the hope that it will be useful, but WITHOUT`
26			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
27			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
28			`// for more details.`
29			`//`
30			`// You should have received a copy of the GNU General Public License along`
31			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
32			`// target there if the PDF file isn't present.) If not, see`
33			`// <http://www.gnu.org/licenses/> for a copy.`
34			`//`
35			`// License: GPL, v3, as defined and found on www.gnu.org,`
36			`// http://www.gnu.org/licenses/gpl.html`
37			`//`
38			`//`
39			`///////////////////////////////////////////////////////////////////////////`
40			`define EQSPI_IDLE 3'h0
41			`define EQSPI_START 3'h1
42			`define EQSPI_BITS 3'h2
43			`define EQSPI_READY 3'h3
44			`define EQSPI_HOLDING 3'h4
45			`define EQSPI_STOP 3'h5
46			`define EQSPI_STOP_B 3'h6
47			`define EQSPI_RECYCLE 3'h7
48
49			`// Modes`
50			`define EQSPI_MOD_SPI 2'b00
51			`define EQSPI_MOD_QOUT 2'b10 // Write
52			`define EQSPI_MOD_QIN 2'b11 // Read
53
54			`module lleqspi(i_clk,`
55			`// Module interface`
56			`i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,`
57			`o_word, o_valid, o_busy,`
58			`// QSPI interface`
59			`o_sck, o_cs_n, o_mod, o_dat, i_dat);`
60			`input i_clk;`
61			`// Chip interface`
62			`// Can send info`
63			`// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,`
64			`// i_word = { 1'b0, 32'info to send },`
65			`// i_len = # of bytes in word-1`
66			`input i_wr, i_hold;`
67			`input [31:0] i_word;`
68			`input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits`
69			`input i_spd; // 0 -> normal QPI, 1 -> QSPI`
70			`input i_dir; // 0 -> read, 1 -> write to SPI`
71			`input i_recycle; // 0 = 20ns, 1 = 50ns`
72			`output reg [31:0] o_word;`
73			`output wire o_valid;`
74			`output reg o_busy;`
75			`// Interface with the QSPI lines`
76			`output reg o_sck;`
77			`output reg o_cs_n;`
78			`output reg [1:0] o_mod;`
79			`output reg [3:0] o_dat;`
80			`input [3:0] i_dat;`
81
82			`// output wire [22:0] o_dbg;`
83			`// assign o_dbg = { state, spi_len,`
84			`// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };`
85
86			`wire i_miso;`
87			`assign i_miso = i_dat[1];`
88
89			`// These are used in creating a delayed input.`
90			`reg rd_input, rd_spd, rd_valid;`
91
92			`reg r_spd, r_dir;`
93			`reg [3:0] r_recycle;`
94			`reg [5:0] spi_len;`
95			`reg [31:0] r_word;`
96			`reg [30:0] r_input;`
97			`reg [2:0] state;`
98			initial state = `EQSPI_IDLE;
99			`initial o_sck = 1'b1;`
100			`initial o_cs_n = 1'b1;`
101			`initial o_dat = 4'hd;`
102			`initial rd_valid = 1'b0;`
103			`initial o_busy = 1'b0;`
104			`initial r_input = 31'h000;`
105			`initial rd_valid = 1'b0;`
106			`always @(posedge i_clk)`
107			`begin`
108			`rd_input <= 1'b0;`
109			`rd_spd <= r_spd;`
110			`rd_valid <= 1'b0;`
111
112			if ((state == `EQSPI_IDLE)&&(o_sck))
113			`begin`
114			`o_cs_n <= 1'b1;`
115			`o_busy <= 1'b0;`
116			o_mod <= `EQSPI_MOD_SPI;
117			`r_word <= i_word;`
118			`r_spd <= i_spd;`
119			`r_dir <= i_dir;`
120			`o_dat <= 4'hc;`
121			`r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4`
122			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;`
123			`o_sck <= 1'b1;`
124			`if (i_wr)`
125			`begin`
126			state <= `EQSPI_START;
127			`o_cs_n <= 1'b0;`
128			`o_busy <= 1'b1;`
129			`end`
130			end else if (state == `EQSPI_START)
131			`begin // We come in here with sck high, stay here 'til sck is low`
132			`o_sck <= 1'b0;`
133			`if (o_sck == 1'b0)`
134			`begin`
135			state <= `EQSPI_BITS;
136			`spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );`
137			`if (r_spd)`
138			`r_word <= { r_word[27:0], 4'h0 };`
139			`else`
140			`r_word <= { r_word[30:0], 1'b0 };`
141			`end`
142			o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
143			`o_cs_n <= 1'b0;`
144			`o_busy <= 1'b1;`
145			`if (r_spd)`
146			`o_dat <= r_word[31:28];`
147			`else`
148			`o_dat <= { 3'b110, r_word[31] };`
149			`end else if (~o_sck)`
150			`begin`
151			`o_sck <= 1'b1;`
152			o_busy <= ((state != `EQSPI_READY)\|\|(~i_wr));
153			end else if (state == `EQSPI_BITS)
154			`begin`
155			`// Should enter into here with at least a spi_len`
156			`// of one, perhaps more`
157			`o_sck <= 1'b0;`
158			`o_busy <= 1'b1;`
159			`if (r_spd)`
160			`begin`
161			`o_dat <= r_word[31:28];`
162			`r_word <= { r_word[27:0], 4'h0 };`
163			`spi_len <= spi_len - 6'h4;`
164			`if (spi_len == 6'h4)`
165			state <= `EQSPI_READY;
166			`end else begin`
167			`o_dat <= { 3'b110, r_word[31] };`
168			`r_word <= { r_word[30:0], 1'b0 };`
169			`spi_len <= spi_len - 6'h1;`
170			`if (spi_len == 6'h1)`
171			state <= `EQSPI_READY;
172			`end`
173
174			`rd_input <= 1'b1;`
175			end else if (state == `EQSPI_READY)
176			`begin`
177			`o_cs_n <= 1'b0;`
178			`o_busy <= 1'b1;`
179			`// This is the state on the last clock (both low and`
180			`// high clocks) of the data. Data is valid during`
181			`// this state. Here we chose to either STOP or`
182			`// continue and transmit more.`
183			`o_sck <= (i_hold); // No clocks while holding`
184			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
185			`begin`
186			state <= `EQSPI_BITS;
187			`o_busy <= 1'b1;`
188			`o_sck <= 1'b0;`
189
190			`// Read the new request off the bus`
191			`r_spd <= i_spd;`
192			`r_dir <= i_dir;`
193			`// Set up the first bits on the bus`
194			o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
195			`if (i_spd)`
196			`begin`
197			`o_dat <= i_word[31:28];`
198			`r_word <= { i_word[27:0], 4'h0 };`
199			`// spi_len <= spi_len - 4;`
200			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
201			`- 6'h4;`
202			`end else begin`
203			`o_dat <= { 3'b110, i_word[31] };`
204			`r_word <= { i_word[30:0], 1'b0 };`
205			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8`
206			`- 6'h1;`
207			`end`
208
209			`// Read a bit upon any transition`
210			`rd_input <= 1'b1;`
211			`rd_valid <= 1'b1;`
212			`end else begin`
213			`o_sck <= 1'b1;`
214			state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
215			`o_busy <= (~i_hold);`
216
217			`// Read a bit upon any transition`
218			`rd_valid <= 1'b1;`
219			`rd_input <= 1'b1;`
220			`end`
221			end else if (state == `EQSPI_HOLDING)
222			`begin`
223			`// We need this state so that the o_valid signal`
224			`// can get strobed with our last result. Otherwise`
225			`// we could just sit in READY waiting for a new command.`
226			`//`
227			`// Incidentally, the change producing this state was`
228			`// the result of a nasty race condition. See the`
229			`// commends in wbqspiflash for more details.`
230			`//`
231			`rd_valid <= 1'b0;`
232			`o_cs_n <= 1'b0;`
233			`o_busy <= 1'b0;`
234			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
235			`begin`
236			state <= `EQSPI_BITS;
237			`o_busy <= 1'b1;`
238			`o_sck <= 1'b0;`
239
240			`// Read the new request off the bus`
241			`r_spd <= i_spd;`
242			`r_dir <= i_dir;`
243			`// Set up the first bits on the bus`
244			o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
245			`if (i_spd)`
246			`begin`
247			`o_dat <= i_word[31:28];`
248			`r_word <= { i_word[27:0], 4'h0 };`
249			`spi_len<= { 1'b0, i_len, 3'b100 };`
250			`end else begin`
251			`o_dat <= { 3'b110, i_word[31] };`
252			`r_word <= { i_word[30:0], 1'b0 };`
253			`spi_len<= { 1'b0, i_len, 3'b111 };`
254			`end`
255			`end else begin`
256			`o_sck <= 1'b1;`
257			state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
258			`o_busy <= (~i_hold);`
259			`end`
260			end else if (state == `EQSPI_STOP)
261			`begin`
262			`o_sck <= 1'b1; // Stop the clock`
263			`rd_valid <= 1'b0; // Output may have just been valid, but no more`
264			`o_busy <= 1'b1; // Still busy till port is clear`
265			state <= `EQSPI_STOP_B;
266			`// Can't change modes for at least one cycle`
267			// o_mod <= `EQSPI_MOD_SPI;
268			end else if (state == `EQSPI_STOP_B)
269			`begin`
270			`o_cs_n <= 1'b1;`
271			`o_sck <= 1'b1;`
272			`// Do I need this????`
273			`// spi_len <= 3; // Minimum CS high time before next cmd`
274			state <= `EQSPI_RECYCLE;
275			`o_busy <= 1'b1;`
276			o_mod <= `EQSPI_MOD_SPI;
277			`end else begin // Recycle state`
278			`r_recycle <= r_recycle - 1'b1;`
279			`o_cs_n <= 1'b1;`
280			`o_sck <= 1'b1;`
281			`o_busy <= 1'b1;`
282			o_mod <= `EQSPI_MOD_SPI;
283			`o_dat <= 4'hc;`
284			`if (r_recycle[3:1] == 3'h0)`
285			state <= `EQSPI_IDLE;
286			`end`
287			`/*`
288			`end else begin // Invalid states, should never get here`
289			state <= `EQSPI_STOP;
290			`o_valid <= 1'b0;`
291			`o_busy <= 1'b1;`
292			`o_cs_n <= 1'b1;`
293			`o_sck <= 1'b1;`
294			o_mod <= `EQSPI_MOD_SPI;
295			`o_dat <= 4'hd;`
296			`end`
297			`*/`
298			`end`
299
300			`always @(posedge i_clk)`
301			`begin`
302			if ((state == `EQSPI_IDLE)\|\|(rd_valid))
303			`r_input <= 31'h00;`
304			`else if ((rd_input)&&(r_spd))`
305			`r_input <= { r_input[26:0], i_dat };`
306			`else if (rd_input)`
307			`r_input <= { r_input[29:0], i_miso };`
308
309			`if ((rd_valid)&&(r_spd))`
310			`o_word <= { r_input[27:0], i_dat };`
311			`else if (rd_valid)`
312			`o_word <= { r_input[30:0], i_miso };`
313			`end`
314
315			`assign o_valid = rd_valid;`
316
317			`endmodule`
318