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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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dgisselq |
//
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// Filename: rtcdate.v
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//
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// Project: A Wishbone Controlled Real--time Clock Core
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//
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// Purpose:
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// This core provides a real-time date function that can be coupled with
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// a real-time clock. The date provided is in Binary Coded Decimal (bcd)
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// form, and available for reading and writing over the Wishbone Bus.
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//
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// WARNING: Race conditions exist when updating the date across the Wishbone
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// bus at or near midnight. (This should be obvious, but it bears
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// stating.) Specifically, if the update command shows up at the same
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// clock as the ppd clock, then the ppd clock will be ignored and the
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// new date will be the date of the day following midnight. However,
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// if the update command shows up one clock before the ppd, then the date
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// may be updated, but may have problems dealing with the last day of the
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// month or year. To avoid race conditions, update the date sometime
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// after the stroke of midnight and before 5 clocks before the next
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// midnight. If you are concerned that you might hit a race condition,
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// just read the clock again (5+ clocks later) to make certain you set
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// it correctly.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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dgisselq |
//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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dgisselq |
module rtcdate(i_clk, i_ppd, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data);
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input i_clk;
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// A one part per day signal, i.e. basically a clock enable line that
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// controls when the beginning of the day happens. This line should
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// be high on the very last second of any day in order for the rtcdate
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// module to always have the right date.
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input i_ppd;
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [31:0] i_wb_data;
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// Wishbone outputs
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire [31:0] o_wb_data;
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reg [5:0] r_day;
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reg [4:0] r_mon;
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reg [13:0] r_year;
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reg last_day_of_month, last_day_of_year, is_leap_year;
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reg [5:0] days_per_month;
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initial days_per_month = 6'h31; // Remember, this is BCD
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always @(posedge i_clk)
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begin // Clock 3
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case(r_mon)
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5'h01: days_per_month <= 6'h31; // Jan
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5'h02: days_per_month <= (is_leap_year)? 6'h29:6'h28;
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5'h03: days_per_month <= 6'h31; // March
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5'h04: days_per_month <= 6'h30; // April
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5'h05: days_per_month <= 6'h31; // May
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5'h06: days_per_month <= 6'h30; // June
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5'h07: days_per_month <= 6'h31; // July
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5'h08: days_per_month <= 6'h31; // August
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5'h09: days_per_month <= 6'h30; // Sept
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5'h10: days_per_month <= 6'h31; // October
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5'h11: days_per_month <= 6'h30; // November
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5'h12: days_per_month <= 6'h31; // December
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default: days_per_month <= 6'h31; // Invalid month
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endcase
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end
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initial last_day_of_month = 1'b0;
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always @(posedge i_clk) // Clock 4
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last_day_of_month <= (r_day >= days_per_month);
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initial last_day_of_year = 1'b0;
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always @(posedge i_clk) // Clock 5
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last_day_of_year <= (last_day_of_month) && (r_mon == 5'h12);
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reg year_divisible_by_four, century_year, four_century_year;
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always @(posedge i_clk) // Clock 1
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year_divisible_by_four<= ((~r_year[0])&&(r_year[4]==r_year[1]));
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always @(posedge i_clk) // Clock 1
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century_year <= (r_year[7:0] == 8'h00);
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always @(posedge i_clk) // Clock 1
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four_century_year <= ((~r_year[8])&&((r_year[12]==r_year[9])));
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always @(posedge i_clk) // Clock 2
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is_leap_year <= (year_divisible_by_four)&&((~century_year)
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||((century_year)&&(four_century_year)));
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// Adjust the day of month
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reg [5:0] next_day, fixd_day;
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always @(posedge i_clk)
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if (last_day_of_month)
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next_day <= 6'h01;
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else if (r_day[3:0] != 4'h9)
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next_day <= { r_day[5:4], (r_day[3:0]+4'h1) };
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else
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next_day <= { (r_day[5:4]+2'h1), 4'h0 };
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always @(posedge i_clk)
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if ((r_day == 0)||(r_day > 6'h31)||(r_day[3:0] > 4'h9))
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fixd_day <= 6'h01;
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else
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fixd_day <= r_day;
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initial r_day = 6'h01;
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always @(posedge i_clk)
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begin // Depends upon 9 inputs
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if (i_ppd)
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r_day <= next_day;
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else if (~o_wb_ack)
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r_day <= fixd_day;
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if ((i_wb_stb)&&(i_wb_we)&&(~i_wb_data[7]))
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r_day <= i_wb_data[5:0];
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end
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// Adjust the month of the year
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reg [4:0] next_mon, fixd_mon;
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always @(posedge i_clk)
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if (last_day_of_year)
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next_mon <= 5'h01;
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else if ((last_day_of_month)&&(r_mon[3:0] != 4'h9))
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next_mon <= { r_mon[4], (r_mon[3:0] + 4'h1) };
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else if (last_day_of_month)
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begin
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next_mon[3:0] <= 4'h0;
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next_mon[4] <= 1;
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end else
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next_mon <= r_mon;
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always @(posedge i_clk)
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if ((r_mon == 0)||(r_mon > 5'h12)||(r_mon[3:0] > 4'h9))
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fixd_mon <= 5'h01;
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else
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fixd_mon <= r_mon;
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initial r_mon = 5'h01;
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always @(posedge i_clk)
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begin // Depeds upon 9 inputs
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if (i_ppd)
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r_mon <= next_mon;
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else if (~o_wb_ack)
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r_mon <= fixd_mon;
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if ((i_wb_stb)&&(i_wb_we)&&(~i_wb_data[15]))
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r_mon <= i_wb_data[12:8];
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end
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// Adjust the year
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reg [13:0] next_year;
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reg [2:0] next_year_c;
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always @(posedge i_clk)
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begin // Takes 5 clocks to propagate
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next_year_c[0] <= (r_year[ 3: 0]>=4'h9);
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next_year_c[1] <= (r_year[ 7: 4]>4'h9)||((r_year[ 7: 4]==4'h9)&&(next_year_c[0]));
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next_year_c[2] <= (r_year[11: 8]>4'h9)||((r_year[11: 8]==4'h9)&&(next_year_c[1]));
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next_year[ 3: 0] <= (next_year_c[0])? 4'h0:(r_year[ 3: 0]+4'h1);
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next_year[ 7: 4] <= (next_year_c[1])? 4'h0:
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(next_year_c[0])?(r_year[ 7: 4]+4'h1)
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: (r_year[7:4]);
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next_year[11: 8] <= (next_year_c[2])? 4'h0:
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(next_year_c[1])?(r_year[11: 8]+4'h1)
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: (r_year[11: 8]);
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next_year[13:12] <= (next_year_c[2])?(r_year[13:12]+2'h1):r_year[13:12];
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end
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initial r_year = 14'h2000;
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always @(posedge i_clk)
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begin // 11 inputs
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// Deal with any out of bounds conditions
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if (r_year[3:0] > 4'h9)
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r_year[3:0] <= 4'h0;
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if (r_year[7:4] > 4'h9)
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r_year[7:4] <= 4'h0;
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if (r_year[11:8] > 4'h9)
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r_year[11:8] <= 4'h0;
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if ((i_ppd)&&(last_day_of_year))
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r_year <= next_year;
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if ((i_wb_stb)&&(i_wb_we)&&(~i_wb_data[31]))
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r_year <= i_wb_data[29:16];
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end
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_data = { 2'h0, r_year, 3'h0, r_mon, 2'h0, r_day };
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endmodule
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