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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: rxecrc.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: To detect any CRC errors in the packet as received. The CRC
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// is not stripped as part of this process.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`define CRCBIT8 32'hedb88320
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`define CRCBIT4 32'h76dc4190
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`define CRCBIT2 32'h3b6e20c8
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`define CRCBIT1 32'h1db71064
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module rxecrc(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_v, o_d, o_err);
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input i_clk, i_ce, i_en, i_cancel;
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input i_v;
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input [3:0] i_d;
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output reg o_v;
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output reg [3:0] o_d;
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output wire o_err;
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reg r_err;
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reg [6:0] r_mq; // Partial CRC matches
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reg [3:0] r_mp; // Prior CRC matches
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reg [31:0] r_crc;
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reg [27:0] r_crc_q0;
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reg [23:0] r_crc_q1;
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reg [19:0] r_crc_q2;
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reg [15:0] r_crc_q3;
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reg [11:0] r_crc_q4;
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reg [ 7:0] r_crc_q5;
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reg [ 3:0] r_crc_q6;
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reg [14:0] r_buf;
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wire [3:0] lownibble;
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assign lownibble = r_crc[3:0] ^ i_d;
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wire [31:0] shifted_crc;
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assign shifted_crc = { 4'h0, r_crc[27:0] };
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always @(posedge i_clk)
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if (i_ce)
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begin
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r_crc_q0 <= r_crc[31:4];
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r_crc_q1 <= r_crc_q0[27:4];
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r_crc_q2 <= r_crc_q1[23:4];
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r_crc_q3 <= r_crc_q2[19:4];
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r_crc_q4 <= r_crc_q3[15:4];
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r_crc_q5 <= r_crc_q4[11:4];
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r_crc_q6 <= r_crc_q5[ 7:4];
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r_buf <= { r_buf[9:0], i_v, i_d };
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if (((!i_ce)&&(!o_v))||(i_cancel))
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begin
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r_crc <= 32'hffff_ffff;
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r_err <= 1'b0;
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r_mq[6:0] <= 7'h0;
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r_mp <= 4'h0;
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r_buf[ 4] <= 1'b0;
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r_buf[ 9] <= 1'b0;
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r_buf[14] <= 1'b0;
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end else
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begin
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/// Calculate the CRC
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case(lownibble)
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4'h0: r_crc <= shifted_crc;
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4'h1: r_crc <= shifted_crc ^ `CRCBIT1;
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4'h2: r_crc <= shifted_crc ^ `CRCBIT2;
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4'h3: r_crc <= shifted_crc ^ `CRCBIT2 ^ `CRCBIT1;
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4'h4: r_crc <= shifted_crc ^ `CRCBIT4;
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4'h5: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT1;
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4'h6: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT2;
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4'h7: r_crc <= shifted_crc ^ `CRCBIT4 ^ `CRCBIT2 ^ `CRCBIT1;
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4'h8: r_crc <= shifted_crc ^ `CRCBIT8;
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4'h9: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT1;
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4'ha: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT2;
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4'hb: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT2 ^ `CRCBIT1;
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4'hc: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4;
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4'hd: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT1;
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4'he: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT2;
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4'hf: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT2 ^ `CRCBIT1;
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endcase
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r_mq[0] <= (i_v)&&(i_d == r_crc[3:0]);
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r_mq[1] <= (r_mq[0])&&(i_v)&&(i_d == r_crc_q0[3:0]);
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r_mq[2] <= (r_mq[1])&&(i_v)&&(i_d == r_crc_q1[3:0]);
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r_mq[3] <= (r_mq[2])&&(i_v)&&(i_d == r_crc_q2[3:0]);
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r_mq[4] <= (r_mq[3])&&(i_v)&&(i_d == r_crc_q3[3:0]);
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r_mq[5] <= (r_mq[4])&&(i_v)&&(i_d == r_crc_q4[3:0]);
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r_mq[6] <= (r_mq[5])&&(i_v)&&(i_d == r_crc_q5[3:0]);
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//r_mq7<=(r_mq6)&&(i_v)&&(i_d == r_crc_q6[3:0]);
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r_mp <= { r_mp[2:0],
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(r_mq[6])&&(i_v)&&(i_d == r_crc_q6[3:0]) };
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// Now, we have an error if ...
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// On the first empty, none of the prior N matches
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// matched.
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r_err <= (r_err)||((i_en)&&(!i_v)&&(r_buf[4])&&(r_mp == 4'h0));
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if ((!i_v)&&(r_buf[4]))
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begin
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if (r_mp[3])
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begin
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r_buf[ 4] <= 1'b0;
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r_buf[ 9] <= 1'b0;
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r_buf[14] <= 1'b0;
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end else if (r_mp[2])
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begin
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r_buf[4] <= 1'b0;
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r_buf[9] <= 1'b0;
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end else if (r_mp[1])
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r_buf[4] <= 1'b0;
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// else if (r_mp[0]) ... keep everything
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end
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o_v <= r_buf[14];
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o_d <= r_buf[13:10];
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end
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end
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assign o_err = r_err;
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endmodule
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