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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: rxeipchk.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: To cull any IP packets (EtherType=0x0806) from the stream
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// whose packet header checksums don't match.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module rxeipchk(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_err);
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input i_clk, i_ce, i_en, i_cancel;
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input i_v; // Valid
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input [3:0] i_d; // Data nibble
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output reg o_err;
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reg r_v;
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reg [15:0] r_word;
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reg [7:0] r_cnt;
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reg [5:0] r_idx;
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always @(posedge i_clk)
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if (i_ce)
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begin
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if ((!i_v)||(i_cancel))
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begin
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r_cnt <= 0;
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r_idx <= 0;
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end else if(i_v)
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begin
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if (!(&r_cnt))
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r_cnt <= r_cnt + 1'b1;
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if (&r_cnt)
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r_v <= 1'b0;
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else
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r_v <= (r_cnt[1:0] == 2'b11);
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if (r_cnt[1:0]==2'b11)
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r_idx[5:0] <= r_cnt[7:2];
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if (!r_cnt[0])
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r_word <= { r_word[7:0], 4'h0, i_d };
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else
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r_word[7:4] <= i_d;
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end
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end
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reg r_ip;
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reg [5:0] r_hlen;
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reg [16:0] r_check;
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always @(posedge i_clk)
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if (i_ce)
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begin
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if ((!i_v)||(i_cancel))
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begin
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o_err <= 0;
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r_check <= 0;
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r_ip <= 0;
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end else if (r_v)
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begin
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if (r_idx == 6'h6)
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r_ip <= (r_word == 16'h0800);
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else if (r_idx == r_hlen)
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r_ip <= 1'b0;
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if (r_idx == 6'h7)
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r_hlen <= {r_word[11:8], 1'b0 } + 5'h7;
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if (r_idx == r_hlen)
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o_err <= (r_ip)&&(i_en)&&(r_check[15:0] != 16'hffff);
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if (r_ip)
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r_check <= r_check[15:0] + r_word + { 15'h0, r_check[16]};
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end
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end
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endmodule
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