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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: rxepreambl.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: To detect, and then remove, any ethernet hardware preamble.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module rxepreambl(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_v, o_d);
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input i_clk, i_ce, i_en, i_cancel;
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input i_v;
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input [3:0] i_d;
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output reg o_v;
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output reg [3:0] o_d;
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reg r_inpkt, r_cancel;
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reg [14:0] r_buf;
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always @(posedge i_clk)
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if(i_ce)
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begin
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if (((!i_v)&&(!o_v))||(i_cancel))
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begin
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// Set us up
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r_inpkt <= 1'b0;
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r_cancel <= (i_v)||(o_v);
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end else if (r_cancel)
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r_cancel <= (i_v)||(o_v);
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if ((i_en)&&(!r_inpkt))
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begin
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r_buf <= { r_buf[9:0], i_v, i_d };
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r_inpkt <= (!r_cancel)&&((r_buf == { 5'h15, 5'h15, 5'h15 })&&(i_v)&&(i_d == 4'hd));
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o_v <= 1'b0;
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end else begin
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o_v <= (i_v)&&(!r_cancel)&&(r_inpkt);
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o_d <= i_d;
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end
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end
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endmodule
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