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[/] [openarty/] [trunk/] [rtl/] [ufifo.v] - Blame information for rev 60

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1 50 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    ufifo.v
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//
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// Project:     wbuart32, a full featured UART with simulator
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//
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// Purpose:     
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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        parameter       BW=8;   // Byte/data width
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        parameter [3:0]  LGFLEN=4;
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        parameter       RXFIFO=1'b0;
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        input                   i_clk, i_rst;
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        input                   i_wr;
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        input   [(BW-1):0]       i_data;
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        output  wire            o_empty_n;      // True if something is in FIFO
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        input                   i_rd;
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        output  wire [(BW-1):0]  o_data;
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        output  wire    [15:0]   o_status;
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        output  wire            o_err;
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        localparam      FLEN=(1<<LGFLEN);
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        reg     [(BW-1):0]       fifo[0:(FLEN-1)];
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        reg     [(LGFLEN-1):0]   r_first, r_last, r_next;
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        wire    [(LGFLEN-1):0]   w_first_plus_one, w_first_plus_two,
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                                w_last_plus_one;
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        assign  w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10};
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        assign  w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1};
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        assign  w_last_plus_one  = r_next; // r_last  + 1'b1;
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        reg     will_overflow;
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        initial will_overflow = 1'b0;
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        always @(posedge i_clk)
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                if (i_rst)
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                        will_overflow <= 1'b0;
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                else if (i_rd)
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                        will_overflow <= (will_overflow)&&(i_wr);
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                else if (i_wr)
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                        will_overflow <= (w_first_plus_two == r_last);
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                else if (w_first_plus_one == r_last)
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                        will_overflow <= 1'b1;
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        // Write
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        reg     r_ovfl;
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        initial r_first = 0;
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        initial r_ovfl  = 0;
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        always @(posedge i_clk)
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                if (i_rst)
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                begin
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                        r_ovfl <= 1'b0;
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                        r_first <= { (LGFLEN){1'b0} };
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                end else if (i_wr)
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                begin // Cowardly refuse to overflow
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                        if ((i_rd)||(!will_overflow)) // (r_first+1 != r_last)
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                                r_first <= w_first_plus_one;
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                        else
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                                r_ovfl <= 1'b1;
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                end
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        always @(posedge i_clk)
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                if (i_wr) // Write our new value regardless--on overflow or not
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                        fifo[r_first] <= i_data;
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        // Reads
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        //      Following a read, the next sample will be available on the
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        //      next clock
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        //      Clock   ReadCMD ReadAddr        Output
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        //      0        0        0                fifo[0]
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        //      1       1       0                fifo[0]
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        //      2       0        1               fifo[1]
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        //      3       0        1               fifo[1]
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        //      4       1       1               fifo[1]
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        //      5       1       2               fifo[2]
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        //      6       0        3               fifo[3]
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        //      7       0        3               fifo[3]
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        reg     will_underflow;
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        initial will_underflow = 1'b1;
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        always @(posedge i_clk)
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                if (i_rst)
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                        will_underflow <= 1'b1;
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                else if (i_wr)
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                        will_underflow <= (will_underflow)&&(i_rd);
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                else if (i_rd)
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                        will_underflow <= (w_last_plus_one == r_first);
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                else
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                        will_underflow <= (r_last == r_first);
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        //
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        // Don't report FIFO underflow errors.  These'll be caught elsewhere
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        // in the system, and the logic below makes it hard to reset them.
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        // We'll still report FIFO overflow, however.
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        //
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        // reg          r_unfl;
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        // initial      r_unfl = 1'b0;
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        initial r_last = 0;
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        always @(posedge i_clk)
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                if (i_rst)
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                begin
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                        r_last <= 0;
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                        r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 };
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                        // r_unfl <= 1'b0;
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                end else if (i_rd)
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                begin
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                        if ((i_wr)||(!will_underflow)) // (r_first != r_last)
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                        begin
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                                r_last <= r_next;
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                                r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10};
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                                // Last chases first
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                                // Need to be prepared for a possible two
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                                // reads in quick succession
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                                // o_data <= fifo[r_last+1];
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                        end
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                        // else r_unfl <= 1'b1;
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                end
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        reg     [7:0]    fifo_here, fifo_next, r_data;
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        always @(posedge i_clk)
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                fifo_here <= fifo[r_last];
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        always @(posedge i_clk)
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                fifo_next <= fifo[r_next];
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        always @(posedge i_clk)
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                r_data <= i_data;
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        reg     [1:0]    osrc;
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        always @(posedge i_clk)
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                if (will_underflow)
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                        // o_data <= i_data;
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                        osrc <= 2'b00;
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                else if ((i_rd)&&(r_first == w_last_plus_one))
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                        osrc <= 2'b01;
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                else if (i_rd)
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                        osrc <= 2'b11;
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                else
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                        osrc <= 2'b10;
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        assign o_data = (osrc[1]) ? ((osrc[0])?fifo_next:fifo_here) : r_data;
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        // wire [(LGFLEN-1):0]  current_fill;
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        // assign       current_fill = (r_first-r_last);
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        reg     r_empty_n;
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        initial r_empty_n = 1'b0;
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        always @(posedge i_clk)
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                if (i_rst)
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                        r_empty_n <= 1'b0;
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                else case({i_wr, i_rd})
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                        2'b00: r_empty_n <= (r_first != r_last);
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                        2'b11: r_empty_n <= (r_first != r_last);
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                        2'b10: r_empty_n <= 1'b1;
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                        2'b01: r_empty_n <= (r_first != w_last_plus_one);
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                endcase
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        wire    w_full_n;
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        assign  w_full_n = will_overflow;
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        //
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        // If this is a receive FIFO, the FIFO count that matters is the number
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        // of values yet to be read.  If instead this is a transmit FIFO, then 
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        // the FIFO count that matters is the number of empty positions that
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        // can still be filled before the FIFO is full.
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        //
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        // Adjust for these differences here.
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        reg     [(LGFLEN-1):0]   r_fill;
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        always @(posedge i_clk)
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                if (RXFIFO!=0) begin
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                        // Calculate the number of elements in our FIFO
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                        //
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                        // Although used for receive, this is actually the more
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                        // generic answer--should you wish to use the FIFO in
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                        // another context.
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                        if (i_rst)
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                                r_fill <= 0;
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                        else case({i_wr, i_rd})
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                        2'b01:   r_fill <= r_first - r_next;
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                        2'b10:   r_fill <= r_first - r_last + 1'b1;
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                        default: r_fill <= r_first - r_last;
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                        endcase
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                end else begin
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                        // Calculate the number of elements that are empty and
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                        // can be filled within our FIFO
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                        if (i_rst)
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                                r_fill <= { (LGFLEN){1'b1} };
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                        else case({i_wr, i_rd})
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                        2'b01:   r_fill <= r_last - r_first;
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                        2'b10:   r_fill <= r_last - w_first_plus_two;
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                        default: r_fill <= r_last - w_first_plus_one;
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                        endcase
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                end
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        // We don't report underflow errors.  These
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        assign o_err = (r_ovfl); //  || (r_unfl);
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        wire    [3:0]    lglen;
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        assign lglen = LGFLEN;
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        wire    [9:0]    w_fill;
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        assign  w_fill[(LGFLEN-1):0] = r_fill;
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        generate if (LGFLEN < 10)
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                assign w_fill[9:(LGFLEN)] = 0;
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        endgenerate
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        wire    w_half_full;
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        assign  w_half_full = r_fill[(LGFLEN-1)];
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        assign  o_status = {
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                // Our status includes a 4'bit nibble telling anyone reading
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                // this the size of our FIFO.  The size is then given by
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                // 2^(this value).  Hence a 4'h4 in this position means that the
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                // FIFO has 2^4 or 16 values within it.
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                lglen,
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                // The FIFO fill--for a receive FIFO the number of elements
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                // left to be read, and for a transmit FIFO the number of
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                // empty elements within the FIFO that can yet be filled.
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                w_fill,
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                // A '1' here means a half FIFO length can be read (receive
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                // FIFO) or written to (not a receive FIFO).
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                // receive FIFO), or be written to (if it isn't).
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                (RXFIFO!=0)?w_half_full:w_half_full,
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                // A '1' here means the FIFO can be read from (if it is a
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                // receive FIFO), or be written to (if it isn't).
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                (RXFIFO!=0)?r_empty_n:w_full_n
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        };
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        assign  o_empty_n = r_empty_n;
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endmodule

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