Subversion Repositories openarty

////////////////////////////////////////////////////////////////////////////////

//

// Filename:    wbddrsdram.v

//

// Project:     OpenArty, an entirely open SoC based upon the Arty platform

//

// Purpose:     

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

////////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015-2016, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with this program.  (It's in the $(ROOT)/doc directory, run make with no

// target there if the PDF file isn't present.)  If not, see

// <http://www.gnu.org/licenses/> for a copy.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

////////////////////////////////////////////////////////////////////////////////

//

//

module  wbddrsdram(i_clk_200mhz,

                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,

                        o_wb_ack, o_wb_stb, o_wb_data,

                o_ddr_reset_n, o_ddr_cke,

                o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,

                o_ddr_dqs,

                o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);

        input   i_clk_200mhz;

        // Wishbone inputs

        input                   i_wb_cyc, i_wb_stb, i_wb_we;

        input           [25:0]   i_wb_addr;

        input           [31:0]   i_wb_data;

        // Wishbone outputs

        output  reg             o_wb_ack;

        output  reg             o_wb_stall;

        output  reg     [31:0]   o_wb_data;

        // DDR3 RAM Controller

        output  wire            o_ddr_reset_n;

        output  wire            o_ddr_reset_cke;

        // Control outputs

        output  reg             o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;

        // DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow

        output  reg     [2:0]    o_ddr_dqs;

        // Address outputs

        output  reg     [13:0]   o_ddr_addr;

        output  reg     [2:0]    o_ddr_ba;

        // And the data inputs and outputs

        output  reg     [31:0]   o_ddr_data;

        input                   i_ddr_data;

//

// tWTR = 7.5

// tRRD = 7.5

// tREFI= 7.8

// tFAW = 45

// tRTP = 7.5

// tCKE = 5.625

// tRFC = 160

// tRP  = 13.5

// tRAS = 36

// tRCD = 13.5

//

// RESET:

//      1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)

//              Hold cke low during this time as well

//              The clock should be free running into the chip during this time

//              Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;

//              ODT must be held low

//      2. Hold cke low for another 500us, or 100,000 clocks

//      3. Raise CKE, continue outputting a NOOP for

//              tXPR, tDLLk, and tZQInit

//      4. Load MRS2, wait tMRD

//      4. Load MRS3, wait tMRD

//      4. Load MRS1, wait tMOD

// Before using the SDRAM, we'll need to program at least 3 of the mode

//      registers, if not all 4. 

//   tMOD clocks are required to program the mode registers, during which

//      time the RAM must be idle.

//

// NOOP: CS low, RAS, CAS, and WE high

        // Need to set o_wb_dqs high one clock prior to any read.

        // As per spec, ODT = 0 during reads

        assign  o_ddr_odt = ~o_ddr_we_n;

endmodule