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1 30 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 3 dgisselq
//
3
// Filename:    wbspiflash.v
4
//
5
// Project:     Wishbone Controlled Quad SPI Flash Controller
6
//
7
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
9
//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14
//      Wishbone Registers (See spec sheet for more detail):
15
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
17
//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21
//      1: Configuration register
22
//      2: Status register (R/w)
23
//      3: Read ID (read only)
24
//      (19 bits): Data (R/w, but expect writes to take a while)
25
//              
26
//
27
// Creator:     Dan Gisselquist, Ph.D.
28
//              Gisselquist Technology, LLC
29
//
30 30 dgisselq
////////////////////////////////////////////////////////////////////////////////
31 3 dgisselq
//
32
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
33
//
34
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// You should have received a copy of the GNU General Public License along
45
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
46
// target there if the PDF file isn't present.)  If not, see
47
// <http://www.gnu.org/licenses/> for a copy.
48
//
49
// License:     GPL, v3, as defined and found on www.gnu.org,
50
//              http://www.gnu.org/licenses/gpl.html
51
//
52
//
53 30 dgisselq
////////////////////////////////////////////////////////////////////////////////
54 3 dgisselq
//
55 30 dgisselq
//
56 3 dgisselq
`include "flash_config.v"
57
//
58
`define WBQSPI_RESET            0
59
`define WBQSPI_RESET_QUADMODE   1
60
`define WBQSPI_IDLE             2
61
`define WBQSPI_RDIDLE           3       // Idle, but in fast read mode
62
`define WBQSPI_WBDECODE         4
63
`define WBQSPI_RD_DUMMY         5
64
`define WBQSPI_QRD_ADDRESS      6
65
`define WBQSPI_QRD_DUMMY        7
66
`define WBQSPI_READ_CMD         8
67
`define WBQSPI_READ_DATA        9
68
`define WBQSPI_WAIT_TIL_RDIDLE  10
69
`define WBQSPI_READ_ID_CMD      11
70
`define WBQSPI_READ_ID          12
71
`define WBQSPI_READ_STATUS      13
72
`define WBQSPI_READ_CONFIG      14
73
`define WBQSPI_WAIT_TIL_IDLE    15
74
//
75
//
76
`ifndef READ_ONLY
77
//
78
`define WBQSPI_WAIT_WIP_CLEAR   16
79
`define WBQSPI_CHECK_WIP_CLEAR  17
80
`define WBQSPI_CHECK_WIP_DONE   18
81
`define WBQSPI_WEN              19
82
`define WBQSPI_PP               20      // Program page
83
`define WBQSPI_QPP              21      // Program page, 4 bit mode
84
`define WBQSPI_WR_DATA          22
85
`define WBQSPI_WR_BUS_CYCLE     23
86
`define WBQSPI_WRITE_STATUS     24
87
`define WBQSPI_WRITE_CONFIG     25
88
`define WBQSPI_ERASE_WEN        26
89
`define WBQSPI_ERASE_CMD        27
90
`define WBQSPI_ERASE_BLOCK      28
91
`define WBQSPI_CLEAR_STATUS     29
92
`define WBQSPI_IDLE_CHECK_WIP   30
93
//
94
`endif
95
 
96
module  wbqspiflash(i_clk,
97
                // Internal wishbone connections
98
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
99
                i_wb_addr, i_wb_data,
100
                // Wishbone return values
101
                o_wb_ack, o_wb_stall, o_wb_data,
102
                // Quad Spi connections to the external device
103
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
104
                o_interrupt);
105
        parameter       ADDRESS_WIDTH=22;
106
        input                   i_clk;
107
        // Wishbone, inputs first
108
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
109
        input           [(ADDRESS_WIDTH-3):0]    i_wb_addr;
110
        input           [31:0]   i_wb_data;
111
        // then outputs
112
        output  reg             o_wb_ack;
113
        output  reg             o_wb_stall;
114
        output  reg     [31:0]   o_wb_data;
115
        // Quad SPI control wires
116
        output  wire            o_qspi_sck, o_qspi_cs_n;
117
        output  wire    [1:0]    o_qspi_mod;
118
        output  wire    [3:0]    o_qspi_dat;
119
        input           [3:0]    i_qspi_dat;
120
        // Interrupt line
121
        output  reg             o_interrupt;
122
        // output       wire    [31:0]  o_debug;
123
 
124
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
125
        reg     [31:0]   spi_in;
126
        reg     [1:0]    spi_len;
127
        wire    [31:0]   spi_out;
128
        wire            spi_valid, spi_busy;
129
        wire            w_qspi_sck, w_qspi_cs_n;
130
        wire    [3:0]    w_qspi_dat;
131
        wire    [1:0]    w_qspi_mod;
132
        // wire [22:0]  spi_dbg;
133
        llqspi  lldriver(i_clk,
134
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
135
                                spi_out, spi_valid, spi_busy,
136
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
137
                                i_qspi_dat);
138
 
139
        // Erase status tracking
140
        reg             write_in_progress, write_protect;
141
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
142
        reg             dirty_sector;
143
        initial begin
144
                write_in_progress = 1'b0;
145
                erased_sector = 0;
146
                dirty_sector  = 1'b1;
147
                write_protect = 1'b1;
148
        end
149
 
150
        reg     qspi_full_stop;
151
        always @(posedge i_clk)
152
                qspi_full_stop <= ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr));
153
 
154
        reg     [7:0]    last_status;
155
        reg             quad_mode_enabled;
156
        reg             spif_cmd, spif_override, wr_same_row, pipeline_read;
157
        reg     [(ADDRESS_WIDTH-3):0]    spif_addr;
158
        reg     [31:0]   spif_data;
159
        reg     [5:0]    state;
160
        reg             spif_ctrl, spif_req;
161
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
162
        assign  spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
163
 
164
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
165
 
166
        initial state = `WBQSPI_RESET;
167
        initial o_wb_ack   = 1'b0;
168
        initial o_wb_stall = 1'b1;
169
        initial spi_wr     = 1'b0;
170
        initial spi_len    = 2'b00;
171
        initial quad_mode_enabled = 1'b0;
172
        initial o_interrupt = 1'b0;
173
        always @(posedge i_clk)
174
        begin
175
        spif_override <= 1'b0;
176
        if (state == `WBQSPI_RESET)
177
        begin
178
                // From a reset, we should
179
                //      Enable the Quad I/O mode
180
                //      Disable the Write protection bits in the status register
181
                //      Chip should already be up and running, so we can start
182
                //      immediately ....
183
                o_wb_ack <= 1'b0;
184
                o_wb_stall <= 1'b1;
185
                spi_wr   <= 1'b0;
186
                spi_hold <= 1'b0;
187
                spi_spd  <= 1'b0;
188
                spi_dir  <= 1'b0;
189
                last_status <= 8'h00;
190
                state <= `WBQSPI_RESET_QUADMODE;
191
                spif_req <= 1'b0;
192
                spif_override <= 1'b1;
193
                last_status <= 8'hfc; //
194
                        // This guarantees that we aren't starting in quad
195
                        // I/O mode, where the FPGA configuration scripts may
196
                        // have left us.
197
        end else if (state == `WBQSPI_RESET_QUADMODE)
198
        begin
199
                // Okay, so here's the problem: we don't know whether or not
200
                // the Xilinx loader started us up in Quad Read I/O idle mode.
201
                // So, thus we need to 
202
                // Not ready to handle the bus yet, so stall any requests
203
                o_wb_ack   <= 1'b0;
204
                o_wb_stall <= 1'b1;
205
 
206
                // Do something ...
207
                if (last_status == 8'h00)
208
                begin
209
                        spif_override <= 1'b0;
210
                        state <= `WBQSPI_IDLE;
211
                end else begin
212
                        last_status <= last_status - 8'h1;
213
                        spif_override <= 1'b1;
214
                        spif_cmd  <= last_status[3]; // Toggle CS_n
215
                        spif_ctrl <= last_status[0]; // Toggle clock too
216
                end
217
        end else if (state == `WBQSPI_IDLE)
218
        begin
219
                o_interrupt <= 1'b0;
220
                o_wb_stall <= 1'b0;
221
                o_wb_ack <= 1'b0;
222
                spif_cmd   <= i_wb_we;
223
                spif_addr  <= i_wb_addr;
224
                spif_data  <= i_wb_data;
225
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
226
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
227
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
228
                spi_hold <= 1'b0;
229
                spi_spd  <= 1'b0;
230
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
231
                //
232
                if ((i_wb_data_stb)&&(~i_wb_we)&&(~write_in_progress))
233
                begin // Read access, normal mode(s)
234
                        o_wb_ack   <= 1'b0;
235
                        o_wb_stall <= 1'b1;
236
                        spi_wr     <= 1'b1;     // Write cmd to device
237
                        spi_len    <= 2'b11;
238
                        if (quad_mode_enabled)
239
                        begin
240
                                // spi_in <= { 8'heb, bus_address };
241
                                state <= `WBQSPI_QRD_ADDRESS;
242
                        end else begin
243
                                //spi_in <= { 8'h0b, bus_address };
244
                                state <= `WBQSPI_RD_DUMMY;
245
                        end
246
                end else if((i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
247
                begin
248
                        // A local read that doesn't touch the device, so leave
249
                        // the device in its current state
250
                        o_wb_stall <= 1'b0;
251
                        o_wb_ack <= 1'b1;
252
                        o_wb_data <= { write_in_progress,
253
                                        dirty_sector, spi_busy,
254
                                        ~write_protect,
255
                                        quad_mode_enabled,
256
                                        {(29-ADDRESS_WIDTH){1'b0}},
257
                                        erased_sector, 14'h000 };
258
                end else if ((i_wb_ctrl_stb)||(i_wb_data_stb))
259
                begin // Need to release the device from quad mode for all else
260
                        o_wb_ack   <= 1'b0;
261
                        o_wb_stall <= 1'b1;
262
                        spi_wr <= 1'b0;
263
                        spi_len <= 2'b11;
264
                        // spi_in <= 32'h00;
265
                        state <= `WBQSPI_WBDECODE;
266
                end
267
        end else if (state == `WBQSPI_RDIDLE)
268
        begin
269
                spi_wr <= 1'b0;
270
                o_wb_stall <= 1'b0;
271
                o_wb_ack <= 1'b0;
272
                spif_cmd   <= i_wb_we;
273
                spif_addr  <= i_wb_addr;
274
                spif_data  <= i_wb_data;
275
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
276
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
277
                spi_hold <= 1'b0;
278
                spi_spd<= 1'b1;
279
                spi_dir <= 1'b0; // Write (for now)
280
                if ((i_wb_data_stb)&&(~i_wb_we))
281
                begin // Continue our read ... send the new address / mode
282
                        o_wb_stall <= 1'b1;
283
                        spi_wr <= 1'b1;
284
                        spi_len <= 2'b10; // Write address, but not mode byte
285
                        // spi_in <= { bus_address, 8'ha0 };
286
                        state <= `WBQSPI_QRD_DUMMY;
287
                end else if((i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
288
                begin
289
                        // A local read that doesn't touch the device, so leave
290
                        // the device in its current state
291
                        o_wb_stall <= 1'b0;
292
                        o_wb_ack <= 1'b1;
293
                        o_wb_data <= { write_in_progress,
294
                                        dirty_sector, spi_busy,
295
                                        ~write_protect,
296
                                        quad_mode_enabled,
297
                                        {(29-ADDRESS_WIDTH){1'b0}},
298
                                        erased_sector, 14'h000 };
299
                end else if ((i_wb_ctrl_stb)||(i_wb_data_stb))
300
                begin // Need to release the device from quad mode for all else
301
                        o_wb_ack   <= 1'b0;
302
                        o_wb_stall <= 1'b1;
303
                        spi_wr <= 1'b1;
304
                        spi_len <= 2'b11;
305
                        // spi_in <= 32'h00;
306
                        state <= `WBQSPI_WBDECODE;
307
                end
308
        end else if (state == `WBQSPI_WBDECODE)
309
        begin
310
                // We were in quad SPI read mode, and had to get out.
311
                // Now we've got a command (not data read) to read and
312
                // execute.  Accomplish what we would've done while in the
313
                // IDLE state here, save only that we don't have to worry
314
                // about data reads, and we need to operate on a stored
315
                // version of the bus command
316
                o_wb_stall <= 1'b1;
317
                o_wb_ack <= 1'b0;
318
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
319
                spi_hold <= 1'b0;
320
                spi_spd <= 1'b0;
321
                spi_dir <= 1'b0;
322
                spif_req<= (spif_req) && (i_wb_cyc);
323
                if (qspi_full_stop) // only in full idle ...
324
                begin
325
                        // Data register access
326
                        if (~spif_ctrl)
327
                        begin
328
                                if (spif_cmd) // Request to write a page
329
                                begin
330
`ifdef  READ_ONLY
331
                                        o_wb_ack <= spif_req;
332
                                        o_wb_stall <= 1'b0;
333
                                        state <= `WBQSPI_IDLE;
334
`else
335
                                        if((~write_protect)&&(~write_in_progress))
336
                                        begin // 00
337
                                                spi_wr <= 1'b1;
338
                                                spi_len <= 2'b00; // 8 bits
339
                                                // Send a write enable command
340
                                                // spi_in <= { 8'h06, 24'h00 };
341
                                                state <= `WBQSPI_WEN;
342
 
343
                                                o_wb_ack <= 1'b0;
344
                                                o_wb_stall <= 1'b1;
345
                                        end else if (write_protect)
346
                                        begin // whether or not write-in_progress ...
347
                                                // Do nothing on a write protect
348
                                                // violation
349
                                                //
350
                                                o_wb_ack <= spif_req;
351
                                                o_wb_stall <= 1'b0;
352
                                                state <= `WBQSPI_IDLE;
353
                                        end else begin // write is in progress, wait
354
                                                // for it to complete
355
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
356
                                                o_wb_ack <= 1'b0;
357
                                                o_wb_stall <= 1'b1;
358
                                        end
359
                                // end else if (~write_in_progress) // always true
360
                                // but ... we wouldn't get here on a normal read access
361
`endif
362
                                end else begin
363
                                        // Something's wrong, we should never
364
                                        //   get here
365
                                        // Attempt to go to idle to recover
366
                                        state <= `WBQSPI_IDLE;
367
                                end
368
                        end else if ((spif_ctrl)&&(spif_cmd))
369
                        begin
370
`ifdef  READ_ONLY
371
                                o_wb_ack   <= spif_req;
372
                                o_wb_stall <= 1'b0;
373
                                state <= `WBQSPI_IDLE;
374
`else
375
                                o_wb_stall <= 1'b1;
376
                                case(spif_addr[1:0])
377
                                2'b00: begin // Erase command register
378
                                        o_wb_ack   <= spif_req;
379
                                        o_wb_stall <= 1'b0;
380
                                        state <= `WBQSPI_IDLE;
381
                                        write_protect <= ~spif_data[28];
382
                                        // Are we commanding an erase?
383
                                        // We're in read mode, writes cannot
384
                                        // be in progress, so ...
385
                                        if (spif_data[31]) // Command an erase
386
                                        begin
387
                                                // Since we're not going back
388
                                                // to IDLE, we must stall the
389
                                                // bus here
390
                                                o_wb_stall <= 1'b1;
391
                                                spi_wr <= 1'b1;
392
                                                spi_len <= 2'b00;
393
                                                // Send a write enable command
394
                                                // spi_in <= { 8'h06, 24'h00 };
395
                                                state <= `WBQSPI_ERASE_CMD;
396
                                        end end
397
                                2'b01: begin
398
                                        // Write the configuration register
399
                                        o_wb_ack <= spif_req;
400
                                        o_wb_stall <= 1'b1;
401
 
402
                                        // Need to send a write enable command first
403
                                        spi_wr <= 1'b1;
404
                                        spi_len <= 2'b00; // 8 bits
405
                                        // Send a write enable command
406
                                        // spi_in <= { 8'h06, 24'h00 };
407
                                        state <= `WBQSPI_WRITE_CONFIG;
408
                                        end
409
                                2'b10: begin
410
                                        // Write the status register
411
                                        o_wb_ack <= spif_req; // Ack immediately
412
                                        o_wb_stall <= 1'b1; // Stall other cmds
413
                                        // Need to send a write enable command first
414
                                        spi_wr <= 1'b1;
415
                                        spi_len <= 2'b00; // 8 bits
416
                                        // Send a write enable command
417
                                        // spi_in <= { 8'h06, 24'h00 };
418
                                        state <= `WBQSPI_WRITE_STATUS;
419
                                        end
420
                                2'b11: begin // Write the ID register??? makes no sense
421
                                        o_wb_ack <= spif_req;
422
                                        o_wb_stall <= 1'b0;
423
                                        state <= `WBQSPI_IDLE;
424
                                        end
425
                                endcase
426
`endif
427
                        end else begin // on (~spif_we)
428
                                case(spif_addr[1:0])
429
                                2'b00: begin // Read local register
430
                                        // Nonsense case--would've done this
431
                                        // already
432
                                        state <= `WBQSPI_IDLE;
433
                                        o_wb_ack <= spif_req;
434
                                        o_wb_stall <= 1'b0;
435
                                        end
436
                                2'b01: begin // Read configuration register
437
                                        state <= `WBQSPI_READ_CONFIG;
438
                                        spi_wr <= 1'b1;
439
                                        spi_len <= 2'b01;
440
                                        // spi_in <= { 8'h35, 24'h00};
441
 
442
                                        o_wb_ack <= 1'b0;
443
                                        o_wb_stall <= 1'b1;
444
                                        end
445
                                2'b10: begin // Read status register
446
                                        state <= `WBQSPI_READ_STATUS;
447
                                        spi_wr <= 1'b1;
448
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
449
                                        // spi_in <= { 8'h05, 24'h00};
450
 
451
                                        o_wb_ack <= 1'b0;
452
                                        o_wb_stall <= 1'b1;
453
                                        end
454
                                2'b11: begin // Read ID register
455
                                        state <= `WBQSPI_READ_ID_CMD;
456
                                        spi_wr <= 1'b1;
457
                                        spi_len <= 2'b00;
458
                                        // spi_in <= { 8'h9f, 24'h00};
459
 
460
                                        o_wb_ack <= 1'b0;
461
                                        o_wb_stall <= 1'b1;
462
                                        end
463
                                endcase
464
                        end
465
                end
466
//
467
//
468
//      READ DATA section: for both data and commands
469
//
470
        end else if (state == `WBQSPI_RD_DUMMY)
471
        begin
472
                o_wb_ack   <= 1'b0;
473
                o_wb_stall <= 1'b1;
474
 
475
                spi_wr <= 1'b1; // Non-stop
476
                // Need to read one byte of dummy data,
477
                // just to consume 8 clocks
478
                // spi_in <= { 8'h00, 24'h00 };
479
                spi_len <= 2'b00; // Read 8 bits
480
                spi_spd <= 1'b0;
481
                spi_hold <= 1'b0;
482
                spif_req<= (spif_req) && (i_wb_cyc);
483
 
484
                if ((~spi_busy)&&(~o_qspi_cs_n))
485
                        // Our command was accepted
486
                        state <= `WBQSPI_READ_CMD;
487
        end else if (state == `WBQSPI_QRD_ADDRESS)
488
        begin
489
                // We come in here immediately upon issuing a QRD read
490
                // command (8-bits), but we have to pause to give the
491
                // address (24-bits) and mode (8-bits) in quad speed.
492
                o_wb_ack   <= 1'b0;
493
                o_wb_stall <= 1'b1;
494
 
495
                spi_wr <= 1'b1; // Non-stop
496
                // spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
497
                //              spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
498
                spi_len <= 2'b10; // Write address, not mode byte
499
                spi_spd <= 1'b1;
500
                spi_dir <= 1'b0; // Still writing
501
                spi_hold <= 1'b0;
502
                spif_req<= (spif_req) && (i_wb_cyc);
503
 
504
                if ((~spi_busy)&&(spi_spd))
505
                        // Our command was accepted
506
                        state <= `WBQSPI_QRD_DUMMY;
507
        end else if (state == `WBQSPI_QRD_DUMMY)
508
        begin
509
                o_wb_ack   <= 1'b0;
510
                o_wb_stall <= 1'b1;
511
 
512
                spi_wr <= 1'b1; // Non-stop
513
                // spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
514
                spi_len <= 2'b10; // Write 8 bits
515
                spi_spd <= 1'b1;
516
                spi_dir <= 1'b0; // Still writing
517
                spi_hold <= 1'b0;
518
                spif_req<= (spif_req) && (i_wb_cyc);
519
 
520
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
521
                        // Our command was accepted
522
                        state <= `WBQSPI_READ_CMD;
523
        end else if (state == `WBQSPI_READ_CMD)
524
        begin // Issue our first command to read 32 bits.
525
                o_wb_ack   <= 1'b0;
526
                o_wb_stall <= 1'b1;
527
 
528
                spi_wr <= 1'b1;
529
                // spi_in <= { 8'hff, 24'h00 }; // Empty
530
                spi_len <= 2'b11; // Read 32 bits
531
                spi_dir <= 1'b1; // Now reading
532
                spi_hold <= 1'b0;
533
                spif_req<= (spif_req) && (i_wb_cyc);
534
                if ((spi_valid)&&(spi_len == 2'b11))
535
                        state <= `WBQSPI_READ_DATA;
536
        end else if (state == `WBQSPI_READ_DATA)
537
        begin
538
                // Pipelined read support
539
                spi_wr <=pipeline_read;
540
                // spi_in <= 32'h00;
541
                spi_len <= 2'b11;
542
                // Don't adjust the speed here, it was set in the setup
543
                spi_dir <= 1'b1;        // Now we get to read
544
                // Don't let the device go to idle until the bus cycle ends.
545
                //      This actually prevents a *really* nasty race condition,
546
                //      where the strobe comes in after the lower level device
547
                //      has decided to stop waiting.  The write is then issued,
548
                //      but no one is listening.  By leaving the device open,
549
                //      the device is kept in a state where a valid strobe
550
                //      here will be useful.  Of course, we don't accept
551
                //      all commands, just reads.  Further, the strobe needs
552
                //      to be high for two clocks cycles without changing
553
                //      anything on the bus--one for us to notice it and pull
554
                //      our head out of the sand, and a second for whoever
555
                //      owns the bus to realize their command went through.
556
                spi_hold <= 1'b1;
557
                spif_req<= (spif_req) && (i_wb_cyc);
558
                if ((spi_valid)&&(~spi_in[31]))
559
                begin // Single pulse acknowledge and write data out
560
                        o_wb_ack <= spif_req;
561
                        o_wb_stall <= (~spi_wr);
562
                        // adjust endian-ness to match the PC
563
                        o_wb_data <= { spi_out[7:0], spi_out[15:8],
564
                                spi_out[23:16], spi_out[31:24] };
565
                        state <= (spi_wr)?`WBQSPI_READ_DATA
566
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
567
                        spif_req <= spi_wr;
568
                        spi_hold <= (~spi_wr);
569
                        if (spi_wr)
570
                                spif_addr <= i_wb_addr;
571
                end else if (~i_wb_cyc)
572
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
573
                        // here, just go back to idle
574
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
575
                        spi_hold <= 1'b0;
576
                        o_wb_ack <= 1'b0;
577
                        o_wb_stall <= 1'b1;
578
                end else begin
579
                        o_wb_ack <= 1'b0;
580
                        o_wb_stall <= 1'b1;
581
                end
582
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
583
        begin // Wait 'til idle, but then go to fast read idle instead of full
584
                spi_wr     <= 1'b0;     // idle
585
                spi_hold   <= 1'b0;
586
                o_wb_stall <= 1'b1;
587
                o_wb_ack   <= 1'b0;
588
                spif_req   <= 1'b0;
589
                if (qspi_full_stop) // Wait for a full
590
                begin // clearing of the SPI port before moving on
591
                        state <= `WBQSPI_RDIDLE;
592
                        o_wb_stall <= 1'b0;
593
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
594
                end
595
        end else if (state == `WBQSPI_READ_ID_CMD)
596
        begin // We came into here immediately after issuing a 0x9f command
597
                // Now we need to read 32 bits of data.  Result should be
598
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
599
                // by the number of extended bytes available 8'h4d).
600
                o_wb_ack <= 1'b0;
601
                o_wb_stall<= 1'b1;
602
 
603
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
604
                spi_len <= 2'b11; // 32 bits of data are ... useful
605
                // spi_in <= 32'h00; // Irrelevant
606
                spi_spd <= 1'b0; // Slow speed
607
                spi_dir <= 1'b1; // Reading
608
                spi_hold <= 1'b0;
609
                spif_req <= (spif_req) && (i_wb_cyc);
610
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
611
                        // Our command was accepted, now go read the result
612
                        state <= `WBQSPI_READ_ID;
613
        end else if (state == `WBQSPI_READ_ID)
614
        begin
615
                o_wb_ack <= 1'b0; // Assuming we're still waiting
616
                o_wb_stall <= 1'b1;
617
 
618
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
619
                spi_hold <= 1'b0;
620
                spif_req <= (spif_req) && (i_wb_cyc);
621
 
622
                // Here, we just wait until the result comes back
623
                // The problem is, the result may be the previous result.
624
                // So we use spi_len as an indicator
625
                spi_len <= 2'b00;
626
                if((spi_valid)&&(spi_len==2'b00))
627
                begin // Put the results out as soon as possible
628
                        o_wb_data <= spi_out[31:0];
629
                        o_wb_ack <= spif_req;
630
                        spif_req <= 1'b0;
631
                end else if ((~spi_busy)&&(o_qspi_cs_n))
632
                begin
633
                        state <= `WBQSPI_IDLE;
634
                        o_wb_stall <= 1'b0;
635
                end
636
        end else if (state == `WBQSPI_READ_STATUS)
637
        begin // We enter after the command has been given, for now just
638
                // read and return
639
                spi_wr <= 1'b0;
640
                o_wb_ack <= 1'b0;
641
                spi_hold <= 1'b0;
642
                spif_req <= (spif_req) && (i_wb_cyc);
643
                if (spi_valid)
644
                begin
645
                        o_wb_ack <= spif_req;
646
                        o_wb_stall <= 1'b1;
647
                        spif_req <= 1'b0;
648
                        last_status <= spi_out[7:0];
649
                        write_in_progress <= spi_out[0];
650
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
651
                        begin // status, 'cause we're writing
652
                                o_wb_data <= { spi_out[0],
653
                                        dirty_sector, spi_busy,
654
                                        ~write_protect,
655
                                        quad_mode_enabled,
656
                                        {(29-ADDRESS_WIDTH){1'b0}},
657
                                        erased_sector, 14'h000 };
658
                        end else begin
659
                                o_wb_data <= { 24'h00, spi_out[7:0] };
660
                        end
661
                end
662
 
663
                if (qspi_full_stop)
664
                        state <= `WBQSPI_IDLE;
665
        end else if (state == `WBQSPI_READ_CONFIG)
666
        begin // We enter after the command has been given, for now just
667
                // read and return
668
                spi_wr <= 1'b0;
669
                o_wb_ack <= 1'b0;
670
                o_wb_stall <= 1'b1;
671
                spi_hold <= 1'b0;
672
                spif_req <= (spif_req) && (i_wb_cyc);
673
 
674
                if (spi_valid)
675
                begin
676
                        o_wb_data <= { 24'h00, spi_out[7:0] };
677
                        quad_mode_enabled <= spi_out[1];
678
                end
679
 
680
                if (qspi_full_stop)
681
                begin
682
                        state <= `WBQSPI_IDLE;
683
                        o_wb_ack   <= spif_req;
684
                        o_wb_stall <= 1'b0;
685
                        spif_req <= 1'b0;
686
                end
687
 
688
//
689
//
690
//      Write/erase data section
691
//
692
`ifndef READ_ONLY
693
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
694
        begin
695
                o_wb_stall <= 1'b1;
696
                o_wb_ack   <= 1'b0;
697
                spi_wr <= 1'b0;
698
                spif_req<= (spif_req) && (i_wb_cyc);
699
                if (~spi_busy)
700
                begin
701
                        spi_wr   <= 1'b1;
702
                        // spi_in   <= { 8'h05, 24'h0000 };
703
                        spi_hold <= 1'b1;
704
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
705
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
706
                        spi_spd  <= 1'b0; // Slow speed
707
                        spi_dir  <= 1'b0;
708
                end
709
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
710
        begin
711
                o_wb_stall <= 1'b1;
712
                o_wb_ack   <= 1'b0;
713
                // Repeat as often as necessary until we are clear
714
                spi_wr <= 1'b1;
715
                // spi_in <= 32'h0000; // Values here are actually irrelevant
716
                spi_hold <= 1'b1;
717
                spi_len <= 2'b00; // One byte at a time
718
                spi_spd  <= 1'b0; // Slow speed
719
                spi_dir  <= 1'b0;
720
                spif_req<= (spif_req) && (i_wb_cyc);
721
                if ((spi_valid)&&(~spi_out[0]))
722
                begin
723
                        state <= `WBQSPI_CHECK_WIP_DONE;
724
                        spi_wr   <= 1'b0;
725
                        spi_hold <= 1'b0;
726
                        write_in_progress <= 1'b0;
727
                        last_status <= spi_out[7:0];
728
                end
729
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
730
        begin
731
                o_wb_stall <= 1'b1;
732
                o_wb_ack   <= 1'b0;
733
                // Let's let the SPI port come back to a full idle,
734
                // and the chip select line go low before continuing
735
                spi_wr   <= 1'b0;
736
                spi_len  <= 2'b00;
737
                spi_hold <= 1'b0;
738
                spi_spd  <= 1'b0; // Slow speed
739
                spi_dir  <= 1'b0;
740
                spif_req<= (spif_req) && (i_wb_cyc);
741
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
742
                begin
743
                        spi_wr   <= 1'b0;
744
                        spi_hold <= 1'b0;
745
 
746
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
747
                        4'b00??: begin // Read data from ... somewhere
748
                                spi_wr     <= 1'b1;     // Write cmd to device
749
                                if (quad_mode_enabled)
750
                                begin
751
                                        // spi_in <= { 8'heb,
752
                                                // {(24-ADDRESS_WIDTH){1'b0}},
753
                                                // spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
754
                                        state <= `WBQSPI_QRD_ADDRESS;
755
                                        // spi_len    <= 2'b00; // single byte, cmd only
756
                                end else begin
757
                                        // spi_in <= { 8'h0b,
758
                                                // {(24-ADDRESS_WIDTH){1'b0}},
759
                                                // spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
760
                                        state <= `WBQSPI_RD_DUMMY;
761
                                        spi_len    <= 2'b11; // Send cmd and addr
762
                                end end
763
                        4'b10??: begin // Write data to ... anywhere
764
                                spi_wr <= 1'b1;
765
                                spi_len <= 2'b00; // 8 bits
766
                                // Send a write enable command
767
                                // spi_in <= { 8'h06, 24'h00 };
768
                                state <= `WBQSPI_WEN;
769
                                end
770
                        4'b0110: begin // Read status register
771
                                state <= `WBQSPI_READ_STATUS;
772
                                spi_wr <= 1'b1;
773
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
774
                                // spi_in <= { 8'h05, 24'h00};
775
                                end
776
                        4'b0111: begin
777
                                state <= `WBQSPI_READ_ID_CMD;
778
                                spi_wr <= 1'b1;
779
                                spi_len <= 2'b00;
780
                                // spi_in <= { 8'h9f, 24'h00};
781
                                end
782
                        default: begin //
783
                                o_wb_stall <= 1'b1;
784
                                o_wb_ack <= spif_req;
785
                                state <= `WBQSPI_WAIT_TIL_IDLE;
786
                                end
787
                        endcase
788
                // spif_cmd   <= i_wb_we;
789
                // spif_addr  <= i_wb_addr;
790
                // spif_data  <= i_wb_data;
791
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
792
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
793
                end
794
        end else if (state == `WBQSPI_WEN)
795
        begin // We came here after issuing a write enable command
796
                spi_wr <= 1'b0;
797
                o_wb_ack <= 1'b0;
798
                o_wb_stall <= 1'b1;
799
                spif_req<= (spif_req) && (i_wb_cyc);
800
                if (qspi_full_stop) // Let's come to a full stop
801
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
802
                        // state <= `WBQSPI_PP;
803
        end else if (state == `WBQSPI_PP)
804
        begin // We come here under a full stop / full port idle mode
805
                // Issue our command immediately
806
                spi_wr <= 1'b1;
807
                // spi_in <= { 8'h02,
808
                //              {(24-ADDRESS_WIDTH){1'b0}},
809
                //              spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
810
                spi_len <= 2'b11;
811
                spi_hold <= 1'b1;
812
                spi_spd  <= 1'b0;
813
                spi_dir  <= 1'b0; // Writing
814
                spif_req<= (spif_req) && (i_wb_cyc);
815
 
816
                // Once we get busy, move on
817
                if (spi_busy)
818
                        state <= `WBQSPI_WR_DATA;
819
                if (spif_sector == erased_sector)
820
                        dirty_sector <= 1'b1;
821
        end else if (state == `WBQSPI_QPP)
822
        begin // We come here under a full stop / full port idle mode
823
                // Issue our command immediately
824
                spi_wr <= 1'b1;
825
                // spi_in <= { 8'h32,
826
                //              {(24-ADDRESS_WIDTH){1'b0}},
827
                //              spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
828
                spi_len <= 2'b11;
829
                spi_hold <= 1'b1;
830
                spi_spd  <= 1'b0;
831
                spi_dir  <= 1'b0; // Writing
832
                spif_req<= (spif_req) && (i_wb_cyc);
833
 
834
                // Once we get busy, move on
835
                if (spi_busy)
836
                begin
837
                        // spi_wr is irrelevant here ...
838
                        // Set the speed value once, but wait til we get busy
839
                        // to do so.
840
                        spi_spd <= 1'b1;
841
                        state <= `WBQSPI_WR_DATA;
842
                end
843
                if (spif_sector == erased_sector)
844
                        dirty_sector <= 1'b1;
845
        end else if (state == `WBQSPI_WR_DATA)
846
        begin
847
                o_wb_stall <= 1'b1;
848
                o_wb_ack   <= 1'b0;
849
                spi_wr   <= 1'b1; // write without waiting
850
                // spi_in   <= {
851
                //      spif_data[ 7: 0],
852
                //      spif_data[15: 8],
853
                //      spif_data[23:16],
854
                //      spif_data[31:24] };
855
                spi_len  <= 2'b11; // Write 4 bytes
856
                spi_hold <= 1'b1;
857
                if (~spi_busy)
858
                begin
859
                        o_wb_ack <= spif_req; // Ack when command given
860
                        state <= `WBQSPI_WR_BUS_CYCLE;
861
                end
862
                spif_req<= (spif_req) && (i_wb_cyc);
863
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
864
        begin
865
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
866
                o_wb_stall <= 1'b1;
867
                spi_wr <= 1'b0;
868
                spi_hold <= 1'b1;
869
                write_in_progress <= 1'b1;
870
                spif_req<= (spif_req) && (i_wb_cyc);
871
                if (~i_wb_cyc)
872
                begin
873
                        state <= `WBQSPI_WAIT_TIL_IDLE;
874
                        spi_hold <= 1'b0;
875
                end else if (spi_wr)
876
                begin // Give the SPI a chance to get busy on the last write
877
                        // Do nothing here.
878
                end else if (wr_same_row)
879
                begin
880
                        spif_cmd  <= 1'b1;
881
                        spif_data <= i_wb_data;
882
                        spif_addr <= i_wb_addr;
883
                        spif_ctrl  <= 1'b0;
884
                        spif_req<= 1'b1;
885
                        // We'll keep the bus stalled on this request
886
                        // for a while
887
                        state <= `WBQSPI_WR_DATA;
888
                        o_wb_ack   <= 1'b0;
889
                        o_wb_stall <= 1'b0;
890
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
891
                begin
892
                        spi_hold <= 1'b0;
893
                        spi_wr   <= 1'b0;
894
                        state <= `WBQSPI_WAIT_TIL_IDLE;
895
                end // Otherwise we stay here
896
        end else if (state == `WBQSPI_WRITE_CONFIG)
897
        begin // We enter immediately after commanding a WEN
898
                o_wb_ack   <= 1'b0;
899
                o_wb_stall <= 1'b1;
900
 
901
                spi_len <= 2'b10;
902
                // spi_in <= { 8'h01, last_status, 6'h0, spif_data[1:0], 8'h00 };
903
                spi_wr <= 1'b0;
904
                spi_hold <= 1'b0;
905
                spif_req <= (spif_req) && (i_wb_cyc);
906
                if ((~spi_busy)&&(~spi_wr))
907
                begin
908
                        spi_wr <= 1'b1;
909
                        state <= `WBQSPI_WAIT_TIL_IDLE;
910
                        write_in_progress <= 1'b1;
911
                        quad_mode_enabled <= spif_data[1];
912
                end
913
        end else if (state == `WBQSPI_WRITE_STATUS)
914
        begin // We enter immediately after commanding a WEN
915
                o_wb_ack   <= 1'b0;
916
                o_wb_stall <= 1'b1;
917
 
918
                spi_len <= 2'b01;
919
                // spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
920
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
921
                spi_wr <= 1'b0;
922
                spi_hold <= 1'b0;
923
                spif_req <= (spif_req) && (i_wb_cyc);
924
                if ((~spi_busy)&&(~spi_wr))
925
                begin
926
                        spi_wr <= 1'b1;
927
                        last_status <= spif_data[7:0];
928
                        write_in_progress <= 1'b1;
929
                        if(((last_status[6])||(last_status[5]))
930
                                &&((~spif_data[6])&&(~spif_data[5])))
931
                                state <= `WBQSPI_CLEAR_STATUS;
932
                        else
933
                                state <= `WBQSPI_WAIT_TIL_IDLE;
934
                end
935
        end else if (state == `WBQSPI_ERASE_CMD)
936
        begin // Know that WIP is clear on entry, WEN has just been commanded
937
                spi_wr     <= 1'b0;
938
                o_wb_ack   <= 1'b0;
939
                o_wb_stall <= 1'b1;
940
                spi_hold   <= 1'b0;
941
                spi_spd <= 1'b0;
942
                spi_dir <= 1'b0;
943
                spif_req <= (spif_req) && (i_wb_cyc);
944
 
945
                // Here's the erase command
946
                // spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
947
                spi_len <= 2'b11; // 32 bit write
948
                // together with setting our copy of the WIP bit
949
                write_in_progress <= 1'b1;
950
                // keeping track of which sector we just erased
951
                erased_sector <= spif_data[(ADDRESS_WIDTH-3):14];
952
                // and marking this erase sector as no longer dirty
953
                dirty_sector <= 1'b0;
954
 
955
                // Wait for a full stop before issuing this command
956
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
957
                begin // When our command is accepted, move to the next state
958
                        spi_wr <= 1'b1;
959
                        state <= `WBQSPI_ERASE_BLOCK;
960
                end
961
        end else if (state == `WBQSPI_ERASE_BLOCK)
962
        begin
963
                spi_wr     <= 1'b0;
964
                spi_hold   <= 1'b0;
965
                o_wb_stall <= 1'b1;
966
                o_wb_ack   <= 1'b0;
967
                spif_req <= (spif_req) && (i_wb_cyc);
968
                // When the port clears, we can head back to idle
969
                if ((~spi_busy)&&(~spi_wr))
970
                begin
971
                        o_wb_ack <= spif_req;
972
                        state <= `WBQSPI_IDLE;
973
                end
974
        end else if (state == `WBQSPI_CLEAR_STATUS)
975
        begin // Issue a clear status command
976
                spi_wr <= 1'b1;
977
                spi_hold <= 1'b0;
978
                spi_len <= 2'b00; // 8 bit command
979
                // spi_in <= { 8'h30, 24'h00 };
980
                spi_spd <= 1'b0;
981
                spi_dir <= 1'b0;
982
                last_status[6:5] <= 2'b00;
983
                spif_req <= (spif_req) && (i_wb_cyc);
984
                if ((spi_wr)&&(~spi_busy))
985
                        state <= `WBQSPI_WAIT_TIL_IDLE;
986
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
987
        begin // We are now in read status register mode
988
 
989
                // No bus commands have (yet) been given
990
                o_wb_stall <= 1'b1;
991
                o_wb_ack   <= 1'b0;
992
                spif_req <= (spif_req) && (i_wb_cyc);
993
 
994
                // Stay in this mode unless/until we get a command, or
995
                //      the write is over
996
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
997
                                &&(write_in_progress));
998
                spi_len <= 2'b00; // 8 bit reads
999
                spi_spd <= 1'b0;  // SPI, not quad
1000
                spi_dir <= 1'b1;  // Read
1001
                if (spi_valid)
1002
                begin
1003
                        write_in_progress <= spi_out[0];
1004
                        if ((~spi_out[0])&&(write_in_progress))
1005
                                o_interrupt <= 1'b1;
1006
                end else
1007
                        o_interrupt <= 1'b0;
1008
 
1009
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
1010
                begin // We can now go to idle and process a command
1011
                        o_wb_stall <= 1'b0;
1012
                        o_wb_ack   <= 1'b0;
1013
                        state <= `WBQSPI_IDLE;
1014
                end
1015
`endif //       !READ_ONLY
1016
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
1017
        begin
1018
                spi_wr     <= 1'b0;
1019
                spi_hold   <= 1'b0;
1020
                o_wb_stall <= 1'b1;
1021
                o_wb_ack   <= 1'b0;
1022
                spif_req   <= 1'b0;
1023
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
1024
                begin // clearing of the SPI port before moving on
1025
                        state <= `WBQSPI_IDLE;
1026
                        o_wb_stall <= 1'b0;
1027
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
1028
                end
1029
        end
1030
        end
1031
 
1032
 
1033
        wire    [23:0]   bus_address, reg_address;
1034
        generate
1035
        if (ADDRESS_WIDTH<24)
1036
        begin
1037
                assign bus_address = { {(24-ADDRESS_WIDTH){1'b0}},
1038
                                        i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
1039
                assign reg_address = { {(24-ADDRESS_WIDTH){1'b0}},
1040
                                        spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
1041
        end else begin
1042
                assign bus_address = { i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
1043
                assign reg_address = { spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
1044
        end endgenerate
1045
 
1046
        // Set the spi_in register, and that register only
1047
        always @(posedge i_clk)
1048
        begin
1049
                if (state == `WBQSPI_IDLE)
1050
                begin
1051
                        if (quad_mode_enabled)
1052
                                spi_in <= { 8'heb, bus_address };
1053
                        else
1054
                                spi_in <= { 8'h0b, bus_address };
1055
                end else if (state == `WBQSPI_RDIDLE)
1056
                begin
1057
                        spi_in <= 32'h00;
1058
                        if ((i_wb_data_stb)&&(~i_wb_we))
1059
                        begin // Send the new address / mode
1060
                                spi_in <= { bus_address, 8'ha0 };
1061
                        end
1062
                end else if (state == `WBQSPI_WBDECODE)
1063
                begin
1064
                        if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
1065
                        begin
1066
                                // Data register access
1067
                                if (~spif_ctrl)
1068
                                begin
1069
                                        spi_in <= { 8'h06, 24'h00 };
1070
                                end else if ((spif_ctrl)&&(spif_cmd))
1071
                                begin
1072
`ifdef  READ_ONLY
1073
`else
1074
                                spi_in <= { 8'h06, 24'h00 };
1075
`endif
1076
                                end else begin // on (~spif_we)
1077
                                        case(spif_addr[1:0])
1078
                                        2'b00: ;// Read local register
1079
                                        2'b01: // Read configuration register
1080
                                                spi_in <= { 8'h35, 24'h00};
1081
                                        2'b10: // Read status register
1082
                                                spi_in <= { 8'h05, 24'h00};
1083
                                        2'b11: // Read ID register
1084
                                                spi_in <= { 8'h9f, 24'h00};
1085
                                        endcase
1086
                                end
1087
                        end
1088
                end else if (state == `WBQSPI_RD_DUMMY)
1089
                begin
1090
                        spi_in <= { 8'h00, 24'h00 };
1091
                end else if (state == `WBQSPI_QRD_ADDRESS)
1092
                begin
1093
                        spi_in <= { reg_address, 8'ha0 };
1094
                end else if (state == `WBQSPI_QRD_DUMMY)
1095
                begin
1096
                        spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
1097
                end else if (state == `WBQSPI_READ_CMD)
1098
                begin // Issue our first command to read 32 bits.
1099
                        spi_in <= { 8'hff, 24'h00 }; // Empty
1100
                end else if (state == `WBQSPI_READ_DATA)
1101
                begin
1102
                        spi_in <= 32'h00;
1103
                end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
1104
                begin // Wait 'til idle, but then go to fast read idle instead of full
1105
                end else if (state == `WBQSPI_READ_ID_CMD)
1106
                begin // We came into here immediately after issuing a 0x9f command
1107
                        spi_in <= 32'h00; // Irrelevant
1108
                end else if (state == `WBQSPI_READ_ID)
1109
                begin
1110
                end else if (state == `WBQSPI_READ_STATUS)
1111
                begin // We enter after the command has been given, for now just
1112
                end else if (state == `WBQSPI_READ_CONFIG)
1113
                begin // We enter after the command has been given, for now just
1114
`ifndef READ_ONLY
1115
                end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
1116
                begin
1117
                        if (~spi_busy)
1118
                                spi_in   <= { 8'h05, 24'h0000 };
1119
                end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
1120
                begin
1121
                        spi_in <= 32'h0000; // Values here are actually irrelevant
1122
                end else if (state == `WBQSPI_CHECK_WIP_DONE)
1123
                begin
1124
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
1125
                begin
1126
                        // The bottom 24 bits are either don't cares, or the
1127
                        // address we want.  Set them to be the address always,
1128
                        // to spare a touch on their logic.
1129
                        spi_in <= { 8'heb, reg_address };
1130
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
1131
                        4'b00??: begin // Read data from ... somewhere
1132
                                if (quad_mode_enabled)
1133
                                begin
1134
                                        spi_in[31:24] <= 8'heb;
1135
                                end else begin
1136
                                        spi_in[31:24] <= 8'h0b;
1137
                                end end
1138
                        4'b10??: // Write data to ... anywhere
1139
                                spi_in[31:24] <= 8'h06 ;
1140
                        4'b0110: // Read status register
1141
                                spi_in[31:24] <= 8'h05 ;
1142
                        4'b0111:
1143
                                spi_in[31:24] <= 8'h9f ;
1144
                        default: begin //
1145
                                end
1146
                        endcase
1147
                end
1148
        end else if (state == `WBQSPI_WEN)
1149
        begin // We came here after issuing a write enable command
1150
        end else if (state == `WBQSPI_PP)
1151
        begin // We come here under a full stop / full port idle mode
1152
                spi_in <= { 8'h02, reg_address };
1153
        end else if (state == `WBQSPI_QPP)
1154
        begin // We come here under a full stop / full port idle mode
1155
                spi_in <= { 8'h32, reg_address };
1156
        end else if (state == `WBQSPI_WR_DATA)
1157
        begin
1158
                spi_in   <= {
1159
                        spif_data[ 7: 0],
1160
                        spif_data[15: 8],
1161
                        spif_data[23:16],
1162
                        spif_data[31:24] };
1163
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
1164
        begin
1165
        end else if (state == `WBQSPI_WRITE_CONFIG)
1166
        begin // We enter immediately after commanding a WEN
1167
                // spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
1168
                spi_in <= { 8'h01, last_status, 6'h0, spif_data[1:0], 8'h00 };
1169
        end else if (state == `WBQSPI_WRITE_STATUS)
1170
        begin // We enter immediately after commanding a WEN
1171
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
1172
        end else if (state == `WBQSPI_ERASE_CMD)
1173
        begin // Know that WIP is clear on entry, WEN has just been commanded
1174
                // Here's the erase command
1175
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
1176
        end else if (state == `WBQSPI_ERASE_BLOCK)
1177
        begin
1178
        end else if (state == `WBQSPI_CLEAR_STATUS)
1179
        begin // Issue a clear status command
1180
                spi_in <= { 8'h30, 24'h00 };
1181
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
1182
        begin // We are now in read status register mode
1183
`endif //       !READ_ONLY
1184
        end
1185
        end
1186
 
1187
 
1188
        initial wr_same_row = 1'b0;
1189
        always @(posedge i_clk)
1190
                wr_same_row <= ((i_wb_data_stb)&&(i_wb_we)
1191
                        &&(i_wb_addr[5:0] == (spif_addr[5:0]+6'h1))
1192
                        &&(i_wb_addr[(ADDRESS_WIDTH-3):6]
1193
                                ==spif_addr[(ADDRESS_WIDTH-3):6]));
1194
        initial pipeline_read = 1'b0;
1195
        always @(posedge i_clk)
1196
                pipeline_read <=((i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
1197
 
1198
        // Command and control during the reset sequence
1199
        assign  o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
1200
        assign  o_qspi_sck  = (spif_override)?spif_ctrl:w_qspi_sck;
1201
        assign  o_qspi_mod  = (spif_override)?   2'b01 :w_qspi_mod;
1202
        assign  o_qspi_dat  = (spif_override)?   4'b00 :w_qspi_dat;
1203
endmodule

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