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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbuinput.v
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//
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// Project: FPGA library
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//
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// Purpose: Coordinates the receiption of bytes, which are then translated
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// into codewords describing postential bus transactions. This
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// includes turning the human readable bytes into more compact bits,
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// forming those bits into codewords, and decompressing any that reference
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// addresses within a compression table.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module wbuinput(i_clk, i_stb, i_byte, o_stb, o_codword);
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input i_clk, i_stb;
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input [7:0] i_byte;
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output wire o_stb;
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output wire [35:0] o_codword;
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wire hx_stb, hx_valid;
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wire [5:0] hx_hexbits;
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wbutohex tobits(i_clk, i_stb, i_byte,
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hx_stb, hx_valid, hx_hexbits);
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wire cw_stb;
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wire [35:0] cw_word;
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wbureadcw formcw(i_clk, hx_stb, hx_valid, hx_hexbits,
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cw_stb, cw_word);
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// `define DEBUGGING
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`ifdef DEBUGGING
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assign o_stb = cw_stb;
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assign o_codword = cw_word;
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`else
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wbudecompress unpack(i_clk,cw_stb,cw_word, o_stb, o_codword);
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`endif
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endmodule
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