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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbureadcw.v
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//
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// Project: FPGA library
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//
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// Purpose: Read bytes from a serial port (i.e. the jtagser) and translate
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// those bytes into a 6-byte codeword. This codeword may specify
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// a number of values to be read, the value to be written, or an address
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// to read/write from, or perhaps the end of a write sequence.
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//
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// See the encoding documentation file for more information.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Goal: single clock pipeline, 50 slices or less
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//
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module wbureadcw(i_clk, i_stb, i_valid, i_hexbits,
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o_stb, o_codword);
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input i_clk, i_stb, i_valid;
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input [5:0] i_hexbits;
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output reg o_stb;
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output reg [35:0] o_codword;
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// Timing:
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// Clock 0: i_stb is high, i_valid is low
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// Clock 1: shiftreg[5:0] is valid, cw_len is valid
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// r_len = 1
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// Clock 2: o_stb = 1, for cw_len = 1;
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// o_codword is 1-byte valid
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// i_stb may go high again on this clock as well.
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// Clock 3: o_stb = 0 (cw_len=1),
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// cw_len = 0,
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// r_len = 0 (unless i_stb)
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// Ready for next word
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reg [2:0] r_len, cw_len;
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reg [1:0] lastcw;
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wire w_stb;
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assign w_stb = ((r_len == cw_len)&&(cw_len != 0))
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||((i_stb)&&(~i_valid)&&(lastcw == 2'b01));
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// r_len is the length of the codeword as it exists
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// in our register
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initial r_len = 3'h0;
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always @(posedge i_clk)
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if ((i_stb)&&(~i_valid)) // Newline reset
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r_len <= 0;
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else if (w_stb) // reset/restart w/o newline
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r_len <= (i_stb)? 3'h1:3'h0;
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else if (i_stb) //in middle of word
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r_len <= r_len + 3'h1;
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reg [35:0] shiftreg;
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always @(posedge i_clk)
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if (w_stb)
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shiftreg[35:30] <= i_hexbits;
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else if (i_stb) case(r_len)
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3'b000: shiftreg[35:30] <= i_hexbits;
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3'b001: shiftreg[29:24] <= i_hexbits;
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3'b010: shiftreg[23:18] <= i_hexbits;
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3'b011: shiftreg[17:12] <= i_hexbits;
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3'b100: shiftreg[11: 6] <= i_hexbits;
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3'b101: shiftreg[ 5: 0] <= i_hexbits;
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default: begin end
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endcase
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always @(posedge i_clk)
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if (o_stb)
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lastcw <= o_codword[35:34];
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always @(posedge i_clk)
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if ((i_stb)&&(~i_valid)&&(lastcw == 2'b01))
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o_codword[35:30] <= 6'h2e;
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else
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o_codword <= shiftreg;
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// How long do we expect this codeword to be?
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initial cw_len = 3'b000;
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always @(posedge i_clk)
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if ((i_stb)&&(~i_valid))
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cw_len <= 0;
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else if ((i_stb)&&((cw_len == 0)||(w_stb)))
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begin
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if (i_hexbits[5:4] == 2'b11) // 2b vector read
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cw_len <= 3'h2;
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else if (i_hexbits[5:4] == 2'b10) // 1b vector read
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cw_len <= 3'h1;
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else if (i_hexbits[5:3] == 3'b010) // 2b compressed wr
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cw_len <= 3'h2;
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else if (i_hexbits[5:3] == 3'b001) // 2b compressed addr
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cw_len <= 3'b010 + { 1'b0, i_hexbits[2:1] };
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else // long write or set address
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cw_len <= 3'h6;
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end else if (w_stb)
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cw_len <= 0;
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always @(posedge i_clk)
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o_stb <= w_stb;
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endmodule
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