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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: xoddrserdes.v
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//
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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//
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// Purpose: Provide DDR outputs at 8x the clock rate (with a 4x clock given)
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// for such things as the memory clock output, and the data strobe
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// output (DQS) which needs to be synchronous with the memory clock output.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module xoddrserdesb(i_clk_fast, i_clk_slow, i_reset,
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i_data, o_pin_p, o_pin_n);
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input i_clk_fast, i_clk_slow, i_reset;
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input [7:0] i_data;
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output wire o_pin_p, o_pin_n;
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wire local_monitor_pin__unconnected;
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wire oe_for_fabric__unconnected;
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wire [1:0] local_shiftout__unconnected;
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wire local_tbyte_out__unconnected;
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wire send_to_iob;
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wire oe_for_iob;
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OSERDESE2 #(
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.DATA_RATE_OQ("DDR"),
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.DATA_RATE_TQ("BUF"),
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.DATA_WIDTH(8), // 8 data wires sent per clkdiv
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.INIT_OQ(1'b1),
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.SERDES_MODE("MASTER"),
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//
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.TRISTATE_WIDTH(1),
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.INIT_TQ(1'b1),
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.TBYTE_CTL("FALSE"),
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.TBYTE_SRC("FALSE")
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) oserdes_i(
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.CLK(i_clk_fast),
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.CLKDIV(i_clk_slow),
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.OCE(1'b1),
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.OFB(local_monitor_pin__unconnected),
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.OQ(send_to_iob),
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.RST(i_reset),
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//
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.TCE(1'b1),
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.TQ(oe_for_iob),
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.TFB(oe_for_fabric__unconnected),
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.T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0),
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//
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.SHIFTOUT1(local_shiftout__unconnected[0]),
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.SHIFTOUT2(local_shiftout__unconnected[1]),
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0),
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.TBYTEIN(1'b0),
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.TBYTEOUT(local_tbyte_out__unconnected),
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//
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// And now for the actual data we wish to send
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//
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.D1(i_data[0]), .D2(i_data[1]),
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.D3(i_data[2]), .D4(i_data[3]),
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.D5(i_data[4]), .D6(i_data[5]),
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.D7(i_data[6]), .D8(i_data[7])
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);
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OBUFDS iobuf_i(
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.I(send_to_iob),
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.O(o_pin_p), .OB(o_pin_n));
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endmodule
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