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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddrsdramsim.cpp
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//
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include <assert.h>
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#define PREFIX "DDR3-SDRAM"
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const unsigned ckCL = 11,
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ckRP = 11,
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ckRC = 10,
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ckRAS = 7,
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ckRFC = 320, // Clocks from refresh to activate
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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DDR_MR2 = 0x040 | (((ckCL-5)&7)<<3),
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DDR_MR1 = 0x0844,
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DDR_MR0 = 0x0200 | (((ckCL-4)&0x07)<<4) | ((ckCL>11)?0x4:0);
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/*
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const unsigned nREF = 4,
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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*/
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const unsigned nREF = 1,
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ckREFIn = ckREFI;
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#include "ddrsdramsim.h"
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BANKINFO::BANKINFO(void) {
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m_state = 0; m_row = 0; m_wcounter = 0; m_min_time_before_precharge=0;
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}
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void BANKINFO::tick(int cmd, unsigned addr) {
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if (m_wcounter)
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m_wcounter--;
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switch(cmd) {
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case DDR_REFRESH:
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assert(m_state == 0);
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break;
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case DDR_PRECHARGE:
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// assert((m_state&((1<<ckRP)-1)) == ((1<<ckRP)-1));
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m_state &= -2;
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// While the specification allows precharging an already
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// precharged bank, we can keep that from happening
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// here:
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// assert(m_state&7);
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// Only problem is, this will currently break our
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// refresh logic.
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/*
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if (m_min_time_before_precharge != 0) {
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printf("BANK-FAIL: TIME-BEFORE-PRECHARGE = %d (should be zero)\n", m_min_time_before_precharge);
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assert(m_min_time_before_precharge == 0);
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} if (m_min_time_before_activate != 0) {
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printf("BANK-FAIL: TIME-BEFORE-ACTIVATE = %d (should be zero)\n", m_min_time_before_activate);
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assert(m_min_time_before_activate==0);
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}
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*/
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break;
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case DDR_ACTIVATE:
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assert((m_state&((1<<ckRP)-1)) == 0);
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if (((m_state&7)!=0)&&((addr&0x7fff) != m_row)) {
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printf("BANK-FAIL: Attempt to Activate an already active bank without closing it first (m_state = %x)\n", m_state);
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assert((m_state&7)==0);
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}
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/*
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if (m_wcounter != 0) {
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printf("BANK-FAIL: ACTIVATE too soon after write (wcounter = %d)\n", m_wcounter);
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assert(m_wcounter == 0);
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} if (m_min_time_before_activate!=0) {
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printf("BANK-FAIL: ACTIVATE too soon after last activate, (ctr=%d)\n", m_min_time_before_activate);
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assert(m_min_time_before_activate==0);
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}
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*/
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m_state = 1;
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m_row = addr & 0x7fff;
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m_min_time_before_precharge = ckRAS;
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m_min_time_before_activate = ckRC;
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break;
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case DDR_READ: case DDR_WRITE:
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if (DDR_READ)
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assert(m_wcounter == 0);
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else
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m_wcounter = 3+4+4;
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if ((m_state&((1<<ckRP)-1)) != ((1<<ckRP)-1)) {
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printf(PREFIX "::R/W Error: m_state = %08x, ckRP = %d (%08x)\n",
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m_state, ckRP, ((1<<ckRP)-1));
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assert((m_state&((1<<ckRP)-1)) == ((1<<ckRP)-1));
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}
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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break;
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case DDR_ZQS:
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assert((m_state&((1<<ckRP)-1)) == 0);
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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break;
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case DDR_NOOP:
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m_state <<= 1;
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m_state |= (m_state&2)>>1;
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m_state &= ((1<<ckRP)-1);
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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break;
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default:
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break;
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}
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}
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int gbl_state, gbl_counts;
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DDRSDRAMSIM::DDRSDRAMSIM(int lglen) {
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m_memlen = (1<<(lglen-2));
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m_mem = new unsigned[m_memlen];
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m_reset_state = 0;
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m_reset_counts= 0;
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assert(NTIMESLOTS > ckCL+3);
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m_bus = new BUSTIMESLOT[NTIMESLOTS];
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for(int i=0; i<NTIMESLOTS; i++)
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m_bus[i].m_used = 0;
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for(int i=0; i<NTIMESLOTS; i++)
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m_bus[i].m_rtt = 0;
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m_busloc = 0;
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}
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unsigned DDRSDRAMSIM::operator()(int reset_n, int cke,
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int csn, int rasn, int casn, int wen,
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int dqs, int dm, int odt, int busoe,
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int addr, int ba, int data) {
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BUSTIMESLOT *ts, *nxtts;
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int cmd = (reset_n?0:32)|(cke?0:16)|(csn?8:0)
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|(rasn?4:0)|(casn?2:0)|(wen?1:0);
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if ((m_reset_state!=0)&&(reset_n==0)) {
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m_reset_state = 0;
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m_reset_counts = 0;
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} else if (m_reset_state < 16) {
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switch(m_reset_state) {
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case 0:
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m_reset_counts++;
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if (reset_n) {
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assert(m_reset_counts > 40000);
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m_reset_counts = 0;
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m_reset_state = 1;
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} break;
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case 1:
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m_reset_counts++;
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if (cke) {
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assert(m_reset_counts > 100000);
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m_reset_counts = 0;
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m_reset_state = 2;
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} break;
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case 2:
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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assert(m_reset_counts > 147);
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m_reset_counts = 0;
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m_reset_state = 3;
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assert(cmd == DDR_MRSET);
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// Set MR2
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assert(ba == 2);
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assert(addr == DDR_MR2);
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} break;
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case 3:
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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// assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_state = 4;
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assert(cmd == DDR_MRSET);
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// Set MR1
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assert(ba == 1);
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assert(addr == DDR_MR1);
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} break;
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case 4:
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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printf(PREFIX "::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_state = 5;
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assert(cmd == DDR_MRSET);
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// Set MR0
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assert(ba == 0);
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assert(addr == DDR_MR0);
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} break;
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case 5:
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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printf(PREFIX "::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 11);
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m_reset_counts = 0;
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m_reset_state = 6;
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assert(cmd == DDR_ZQS);
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assert(addr == 0x400);
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} break;
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case 6:
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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printf(PREFIX "::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 512);
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m_reset_counts = 0;
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| 245 |
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m_reset_state = 7;
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| 246 |
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assert(cmd == DDR_PRECHARGE);
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assert(addr == 0x400);
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| 248 |
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} break;
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| 249 |
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case 7:
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| 250 |
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m_reset_counts++;
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| 251 |
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assert(cke);
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| 252 |
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if (cmd != DDR_NOOP) {
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| 253 |
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printf(PREFIX "::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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| 254 |
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assert(m_reset_counts > 3);
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| 255 |
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m_reset_counts = 0;
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| 256 |
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m_reset_state = 8;
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| 257 |
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assert(cmd == DDR_REFRESH);
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| 258 |
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m_clocks_since_refresh = 0;
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| 259 |
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} break;
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| 260 |
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case 8:
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| 261 |
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m_reset_counts++;
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| 262 |
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assert(cke);
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| 263 |
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assert(cmd == DDR_NOOP);
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| 264 |
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if (m_reset_counts > 140) {
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| 265 |
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m_reset_state = 16;
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| 266 |
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printf(PREFIX ": Leaving reset state\n");
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| 267 |
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}
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| 268 |
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break;
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| 269 |
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default:
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| 270 |
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break;
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| 271 |
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}
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| 272 |
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| 273 |
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gbl_state = m_reset_state;
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| 274 |
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gbl_counts= m_reset_counts;
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| 275 |
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m_nrefresh_issued = nREF;
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| 276 |
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m_clocks_since_refresh++;
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| 277 |
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for(int i=0; i<NBANKS; i++)
|
| 278 |
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m_bank[i].tick(cmd, 0);
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| 279 |
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} else if (!cke) {
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| 280 |
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assert(0&&"Clock not enabled!");
|
| 281 |
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} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
|
| 282 |
|
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if (DDR_REFRESH == cmd) {
|
| 283 |
|
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m_clocks_since_refresh = 0;
|
| 284 |
|
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if (m_nrefresh_issued >= (int)nREF)
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| 285 |
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m_nrefresh_issued = 1;
|
| 286 |
|
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else
|
| 287 |
|
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m_nrefresh_issued++;
|
| 288 |
|
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} else {
|
| 289 |
|
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m_clocks_since_refresh++;
|
| 290 |
|
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assert(DDR_NOOP == cmd);
|
| 291 |
|
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}
|
| 292 |
|
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for(int i=0; i<NBANKS; i++)
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| 293 |
|
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m_bank[i].tick(cmd,0);
|
| 294 |
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|
| 295 |
|
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if (m_nrefresh_issued == nREF)
|
| 296 |
|
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printf(PREFIX "::Refresh cycle complete\n");
|
| 297 |
|
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} else {
|
| 298 |
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// In operational mode!!
|
| 299 |
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| 300 |
|
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m_clocks_since_refresh++;
|
| 301 |
|
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assert(m_clocks_since_refresh < (int)ckREFIn);
|
| 302 |
|
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switch(cmd) {
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| 303 |
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case DDR_MRSET:
|
| 304 |
|
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assert(0&&"Modes should only be set in reset startup");
|
| 305 |
|
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for(int i=0; i<NBANKS; i++)
|
| 306 |
|
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m_bank[i].tick(DDR_MRSET,0);
|
| 307 |
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break;
|
| 308 |
|
|
case DDR_REFRESH:
|
| 309 |
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for(int i=0; i<NBANKS; i++)
|
| 310 |
|
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m_bank[i].tick(DDR_REFRESH,0);
|
| 311 |
|
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m_clocks_since_refresh = 0;
|
| 312 |
|
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assert(0 && "Internal err: Refresh should be handled above");
|
| 313 |
|
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break;
|
| 314 |
|
|
case DDR_PRECHARGE:
|
| 315 |
|
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if (addr & 0x400) {
|
| 316 |
|
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// Precharge all
|
| 317 |
|
|
for(int i=0; i<NBANKS; i++)
|
| 318 |
|
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m_bank[i].tick(DDR_PRECHARGE,0);
|
| 319 |
|
|
} else {
|
| 320 |
|
|
m_bank[ba].tick(DDR_PRECHARGE,0);
|
| 321 |
|
|
for(int i=0; i<NBANKS; i++)
|
| 322 |
|
|
if (ba != i)
|
| 323 |
|
|
m_bank[i].tick(DDR_NOOP,0);
|
| 324 |
|
|
}
|
| 325 |
|
|
break;
|
| 326 |
|
|
case DDR_ACTIVATE:
|
| 327 |
|
|
if (m_clocks_since_refresh < (int)ckRFC) {
|
| 328 |
|
|
printf(PREFIX "::ACTIVATE -- not enough clocks since refresh, %d < %d should be true\n", m_clocks_since_refresh, ckRFC);
|
| 329 |
|
|
assert(m_clocks_since_refresh >= (int)ckRFC);
|
| 330 |
|
|
}
|
| 331 |
|
|
printf(PREFIX "::Activating bank %d, address %08x\n", ba, addr);
|
| 332 |
|
|
m_bank[ba].tick(DDR_ACTIVATE,addr);
|
| 333 |
|
|
for(int i=0; i<NBANKS; i++)
|
| 334 |
|
|
if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
|
| 335 |
|
|
break;
|
| 336 |
|
|
case DDR_WRITE:
|
| 337 |
|
|
{
|
| 338 |
|
|
// This SIM doesn't handle out of order writes
|
| 339 |
|
|
assert((addr&7)==0);
|
| 340 |
|
|
m_bank[ba].tick(DDR_WRITE, addr);
|
| 341 |
|
|
for(int i=0; i<NBANKS; i++)
|
| 342 |
|
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
| 343 |
|
|
unsigned caddr = m_bank[ba].m_row;
|
| 344 |
|
|
caddr <<= 3;
|
| 345 |
|
|
caddr |= ba;
|
| 346 |
|
|
caddr <<= 10;
|
| 347 |
|
|
caddr |= addr;
|
| 348 |
|
|
caddr &= ~7;
|
| 349 |
|
|
caddr >>= 1;
|
| 350 |
|
|
|
| 351 |
|
|
BUSTIMESLOT *tp;
|
| 352 |
|
|
int offset = m_busloc+ckCL+1;
|
| 353 |
|
|
|
| 354 |
|
|
tp = &m_bus[(offset+0)&(NTIMESLOTS-1)];
|
| 355 |
|
|
// printf("Setting bus timeslots from (now=%d)+%d=%d to now+%d+3\n", m_busloc, ckCL,(m_busloc+ckCL)&(NTIMESLOTS-1), ckCL);
|
| 356 |
|
|
tp->m_addr = caddr ;
|
| 357 |
|
|
tp->m_used = 1;
|
| 358 |
|
|
tp->m_read = 0;
|
| 359 |
|
|
|
| 360 |
|
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
| 361 |
|
|
tp->m_addr = caddr+1;
|
| 362 |
|
|
tp->m_used = 1;
|
| 363 |
|
|
tp->m_read = 0;
|
| 364 |
|
|
|
| 365 |
|
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
| 366 |
|
|
tp->m_addr = caddr+2;
|
| 367 |
|
|
tp->m_used = 1;
|
| 368 |
|
|
tp->m_read = 0;
|
| 369 |
|
|
|
| 370 |
|
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
| 371 |
|
|
tp->m_addr = caddr+3;
|
| 372 |
|
|
tp->m_used = 1;
|
| 373 |
|
|
tp->m_read = 0;
|
| 374 |
|
|
} break;
|
| 375 |
|
|
case DDR_READ:
|
| 376 |
|
|
{
|
| 377 |
|
|
// This SIM doesn't handle out of order reads
|
| 378 |
|
|
assert((addr&7)==0);
|
| 379 |
|
|
m_bank[ba].tick(DDR_READ, addr);
|
| 380 |
|
|
for(int i=0; i<NBANKS; i++)
|
| 381 |
|
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
| 382 |
|
|
unsigned caddr = m_bank[ba].m_row;
|
| 383 |
|
|
caddr <<= 3;
|
| 384 |
|
|
caddr |= ba;
|
| 385 |
|
|
caddr <<= 10;
|
| 386 |
|
|
caddr |= addr;
|
| 387 |
|
|
caddr &= ~7;
|
| 388 |
|
|
caddr >>= 1;
|
| 389 |
|
|
|
| 390 |
|
|
BUSTIMESLOT *tp;
|
| 391 |
|
|
|
| 392 |
|
|
int offset = (m_busloc+ckCL+1)&(NTIMESLOTS-1);
|
| 393 |
|
|
tp = &m_bus[(offset)&(NTIMESLOTS-1)];
|
| 394 |
|
|
tp->m_data = m_mem[caddr];
|
| 395 |
|
|
tp->m_addr = caddr;
|
| 396 |
|
|
tp->m_used = 1;
|
| 397 |
|
|
tp->m_read = 1;
|
| 398 |
|
|
|
| 399 |
|
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
| 400 |
|
|
tp->m_data = m_mem[caddr+1];
|
| 401 |
|
|
tp->m_addr = caddr+1;
|
| 402 |
|
|
tp->m_used = 1;
|
| 403 |
|
|
tp->m_read = 1;
|
| 404 |
|
|
|
| 405 |
|
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
| 406 |
|
|
tp->m_data = m_mem[caddr+2];
|
| 407 |
|
|
tp->m_addr = caddr+2;
|
| 408 |
|
|
tp->m_used = 1;
|
| 409 |
|
|
tp->m_read = 1;
|
| 410 |
|
|
|
| 411 |
|
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
| 412 |
|
|
tp->m_data = m_mem[caddr+3];
|
| 413 |
|
|
tp->m_addr = caddr+3;
|
| 414 |
|
|
tp->m_used = 1;
|
| 415 |
|
|
tp->m_read = 1;
|
| 416 |
|
|
} break;
|
| 417 |
|
|
case DDR_ZQS:
|
| 418 |
|
|
assert(0&&"Sim does not support ZQS outside of startup");
|
| 419 |
|
|
break;
|
| 420 |
|
|
case DDR_NOOP:
|
| 421 |
|
|
for(int i=0; i<NBANKS; i++)
|
| 422 |
|
|
m_bank[i].tick(DDR_NOOP,addr);
|
| 423 |
|
|
break;
|
| 424 |
|
|
default: // We are deselecteda
|
| 425 |
|
|
for(int i=0; i<NBANKS; i++)
|
| 426 |
|
|
m_bank[i].tick(DDR_NOOP,addr);
|
| 427 |
|
|
break;
|
| 428 |
|
|
}
|
| 429 |
|
|
|
| 430 |
|
|
if (false) {
|
| 431 |
|
|
bool flag = false;
|
| 432 |
|
|
for(int i=0; i<5; i++) {
|
| 433 |
|
|
int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
|
| 434 |
|
|
nxtts = &m_bus[bl];
|
| 435 |
|
|
if (nxtts->m_used) {
|
| 436 |
|
|
flag = true;
|
| 437 |
|
|
break;
|
| 438 |
|
|
}
|
| 439 |
|
|
} if (flag) {
|
| 440 |
|
|
printf("DQS = %d BUSLOC = %d\n", dqs, (m_busloc+1)&(NTIMESLOTS-1));
|
| 441 |
|
|
for(int i=0; i<5; i++) {
|
| 442 |
|
|
int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
|
| 443 |
|
|
nxtts = &m_bus[bl];
|
| 444 |
|
|
printf("BUS[%2d] ", bl);
|
| 445 |
|
|
if (nxtts->m_used)
|
| 446 |
|
|
printf(" USED");
|
| 447 |
|
|
if (nxtts->m_read)
|
| 448 |
|
|
printf(" READ");
|
| 449 |
|
|
if (nxtts->m_rtt)
|
| 450 |
|
|
printf(" RTT");
|
| 451 |
|
|
printf("\n");
|
| 452 |
|
|
}}
|
| 453 |
|
|
}
|
| 454 |
|
|
|
| 455 |
|
|
ts = &m_bus[(m_busloc+1)&(NTIMESLOTS-1)];
|
| 456 |
|
|
if (dqs)
|
| 457 |
|
|
assert((ts->m_rtt)&&(m_last_rtt));
|
| 458 |
|
|
else if (!m_last_dqs)
|
| 459 |
|
|
assert(!m_last_rtt);
|
| 460 |
|
|
}
|
| 461 |
|
|
|
| 462 |
|
|
m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
|
| 463 |
|
|
|
| 464 |
|
|
ts = &m_bus[m_busloc];
|
| 465 |
|
|
nxtts = &m_bus[(m_busloc+1)&(NTIMESLOTS-1)];
|
| 466 |
|
|
unsigned vl = ts->m_data;
|
| 467 |
|
|
assert( ((!ts->m_used)||(busoe))
|
| 468 |
|
|
|| ((ts->m_used)&&(ts->m_read)&&(!busoe))
|
| 469 |
|
|
|| ((ts->m_used)&&(!ts->m_read)&&(busoe))
|
| 470 |
|
|
);
|
| 471 |
|
|
|
| 472 |
|
|
m_last_dqs = dqs;
|
| 473 |
|
|
m_last_rtt = ts->m_rtt;
|
| 474 |
|
|
|
| 475 |
|
|
if (ts->m_used) {
|
| 476 |
|
|
if (ts->m_read)
|
| 477 |
|
|
assert((!dqs)&&(!m_last_dqs));
|
| 478 |
|
|
else
|
| 479 |
|
|
assert((dqs) && (m_last_dqs));
|
| 480 |
|
|
} else if (!nxtts->m_used)
|
| 481 |
|
|
assert(!dqs);
|
| 482 |
|
|
|
| 483 |
|
|
assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
|
| 484 |
|
|
if ((ts->m_used)&&(!ts->m_read)&&(!dm)) {
|
| 485 |
|
|
printf(PREFIX "::Setting MEM[%08x] = %08x\n", ts->m_addr, data);
|
| 486 |
|
|
m_mem[ts->m_addr] = data;
|
| 487 |
|
|
}
|
| 488 |
|
|
|
| 489 |
|
|
m_bus[(m_busloc+3)&(NTIMESLOTS-1)].m_rtt = (odt)&&(reset_n);
|
| 490 |
|
|
ts->m_used = 0;
|
| 491 |
|
|
ts->m_read = 0;
|
| 492 |
|
|
ts->m_addr = -1;
|
| 493 |
|
|
ts->m_rtt = 0;
|
| 494 |
|
|
return (!busoe)?vl:data;
|
| 495 |
|
|
}
|
| 496 |
|
|
|
