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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: fastmaster_tb.cpp
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: This is a piped version of the testbench for the wishbone
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// master verilog module, whether it be fastmaster.v or
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// busmaster.v. Both fastmaster.v and busmaster.v are designed to be
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// complete code sets implementing all of the functionality of the Digilent
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// Arty board---save the hardware dependent features to include the DDR3
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// memory. If done well, the programs talking to this one should be
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// able to talk to the board and apply the same tests to the board itself.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <signal.h>
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#include <time.h>
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#include <ctype.h>
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#include "verilated.h"
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#ifdef FASTCLK
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#include "Vfastmaster.h"
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#define BASECLASS Vfastmaster
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#error "This should never be incldued"
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#else
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#include "Vbusmaster.h"
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#define BASECLASS Vbusmaster
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#endif
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#include "testb.h"
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// #include "twoc.h"
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#include "pipecmdr.h"
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#include "eqspiflashsim.h"
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#include "sdspisim.h"
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#include "uartsim.h"
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#include "enetctrlsim.h"
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#include "memsim.h"
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#ifdef OLEDSIM
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#include "oledsim.h"
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#endif
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#include "zipelf.h"
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#include "byteswap.h"
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#include "port.h"
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const int LGMEMSIZE = 28;
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//
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// Define where our memory is at, so we can load into it properly
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// The following comes from the "skipaddr" reference in the I/O handling
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// section. For example, if address line 23 is high, the address is for
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// SDRAM base. The extra +2 is because each bus address references four
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// bytes, and so there are two phantom address lines that need to be
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// accounted for.
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#define MEMBASE (1<<(15+2))
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#define FLASHBASE (1<<(22+2))
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#define SDRAMBASE (1<<(26+2))
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//
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// Setting the length to the base address works because the base address for
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// each of these memory regions is given by a 'one' in the first bit not used
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// by the respective device. If the memory is ever placed elsewhere, that will
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// no longer work, and a proper length will need to be entered in here.
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#define MEMLEN MEMBASE
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#define FLASHLEN FLASHBASE
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#define SDRAMLEN SDRAMBASE
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// No particular "parameters" need definition or redefinition here.
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class TESTBENCH : public PIPECMDR<BASECLASS> {
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public:
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unsigned long m_tx_busy_count;
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EQSPIFLASHSIM m_flash;
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SDSPISIM m_sdcard;
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ENETCTRLSIM *m_mid;
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UARTSIM m_uart;
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MEMSIM m_ram;
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#ifdef OLEDSIM_H
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OLEDWIN m_oled;
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#endif
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int m_halt_in_count;
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unsigned m_last_led, m_last_pic, m_last_tx_state, m_net_ticks;
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time_t m_start_time;
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bool m_last_writeout, m_cpu_started;
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int m_last_bus_owner, m_busy, m_bomb;
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unsigned long m_gps_err, m_gps_step, m_gps_newstep, m_traceticks;
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unsigned m_gps_stepc;
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bool m_done;
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TESTBENCH(int fpgaport, int serialport, bool copy_to_stdout, bool debug)
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: PIPECMDR(fpgaport, copy_to_stdout),
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m_flash(24, debug), m_uart(serialport), m_ram(1<<26)
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{
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if (debug)
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printf("Copy-to-stdout is %s\n", (copy_to_stdout)?"true":"false");
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m_start_time = time(NULL);
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m_mid = new ENETCTRLSIM;
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m_cpu_started =false;
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#ifdef OLEDSIM_H
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Glib::signal_idle().connect(sigc::mem_fun((*this),&TESTBENCH::on_tick));
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#endif
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m_done = false;
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m_bomb = 0;
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m_traceticks = 0;
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//
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m_core->i_aux_cts_n = 0; // The sim doesnt use h/w flow control
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//
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m_halt_in_count = 0;
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}
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void reset(void) {
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m_core->i_clk = 1;
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m_core->eval();
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}
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void trace(const char *vcd_trace_file_name) {
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fprintf(stderr, "Opening TRACE(%s)\n", vcd_trace_file_name);
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opentrace(vcd_trace_file_name);
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m_traceticks = 0;
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}
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void close(void) {
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// TESTB<BASECLASS>::closetrace();
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m_done = true;
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}
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void setsdcard(const char *fn) {
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m_sdcard.load(fn);
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}
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void load(uint32_t addr, const char *buf, uint32_t len) {
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if ((addr >= MEMBASE)&&(addr + len <= MEMBASE+MEMLEN)) {
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char *bswapd = new char[len+8];
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assert( ((len&3)==0) && ((addr&3)==0) );
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memcpy(bswapd, buf, len);
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byteswapbuf(len>>2, (uint32_t *)bswapd);
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memcpy(&m_core->v__DOT__blkram__DOT__mem[addr-MEMBASE],
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bswapd, len);
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delete[] bswapd;
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} else if ((addr >= FLASHBASE)&&(addr + len<= FLASHBASE+FLASHLEN))
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m_flash.load(addr-FLASHBASE, buf, len);
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else if ((addr >= SDRAMBASE)&&(addr + len<= SDRAMBASE+SDRAMLEN))
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m_ram.load(addr-SDRAMBASE, buf, len);
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else {
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fprintf(stderr, "ERR: Address range %07x-%07x does not exist in memory\n",
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addr, addr+len);
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exit(EXIT_FAILURE);
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}
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}
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bool gie(void) {
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return (m_core->v__DOT__swic__DOT__thecpu__DOT__r_gie);
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}
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void dump(const uint32_t *regp) {
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uint32_t uccv, iccv;
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fflush(stderr);
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fflush(stdout);
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printf("ZIPM--DUMP: ");
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if (gie())
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printf("Interrupts-enabled\n");
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else
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printf("Supervisor mode\n");
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printf("\n");
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iccv = m_core->v__DOT__swic__DOT__thecpu__DOT__w_iflags;
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uccv = m_core->v__DOT__swic__DOT__thecpu__DOT__w_uflags;
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printf("sR0 : %08x ", regp[0]);
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printf("sR1 : %08x ", regp[1]);
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printf("sR2 : %08x ", regp[2]);
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printf("sR3 : %08x\n",regp[3]);
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printf("sR4 : %08x ", regp[4]);
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printf("sR5 : %08x ", regp[5]);
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printf("sR6 : %08x ", regp[6]);
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printf("sR7 : %08x\n",regp[7]);
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printf("sR8 : %08x ", regp[8]);
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printf("sR9 : %08x ", regp[9]);
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printf("sR10: %08x ", regp[10]);
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printf("sR11: %08x\n",regp[11]);
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printf("sR12: %08x ", regp[12]);
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printf("sSP : %08x ", regp[13]);
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printf("sCC : %08x ", iccv);
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printf("sPC : %08x\n",regp[15]);
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printf("\n");
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printf("uR0 : %08x ", regp[16]);
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printf("uR1 : %08x ", regp[17]);
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printf("uR2 : %08x ", regp[18]);
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printf("uR3 : %08x\n",regp[19]);
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printf("uR4 : %08x ", regp[20]);
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printf("uR5 : %08x ", regp[21]);
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printf("uR6 : %08x ", regp[22]);
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printf("uR7 : %08x\n",regp[23]);
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printf("uR8 : %08x ", regp[24]);
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printf("uR9 : %08x ", regp[25]);
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printf("uR10: %08x ", regp[26]);
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printf("uR11: %08x\n",regp[27]);
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printf("uR12: %08x ", regp[28]);
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printf("uSP : %08x ", regp[29]);
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printf("uCC : %08x ", uccv);
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printf("uPC : %08x\n",regp[31]);
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printf("\n");
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fflush(stderr);
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fflush(stdout);
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}
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void execsim(const uint32_t imm) {
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uint32_t *regp = m_core->v__DOT__swic__DOT__thecpu__DOT__regset;
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int rbase;
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rbase = (gie())?16:0;
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fflush(stdout);
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if ((imm & 0x03fffff)==0)
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return;
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// fprintf(stderr, "SIM-INSN(0x%08x)\n", imm);
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if ((imm & 0x0fffff)==0x00100) {
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// SIM Exit(0)
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close();
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exit(0);
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} else if ((imm & 0x0ffff0)==0x00310) {
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// SIM Exit(User-Reg)
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int rcode;
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rcode = regp[(imm&0x0f)+16] & 0x0ff;
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close();
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exit(rcode);
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} else if ((imm & 0x0ffff0)==0x00300) {
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// SIM Exit(Reg)
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int rcode;
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rcode = regp[(imm&0x0f)+rbase] & 0x0ff;
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close();
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exit(rcode);
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} else if ((imm & 0x0fff00)==0x00100) {
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// SIM Exit(Imm)
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int rcode;
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rcode = imm & 0x0ff;
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close();
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exit(rcode);
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} else if ((imm & 0x0fffff)==0x002ff) {
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// Full/unconditional dump
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printf("SIM-DUMP\n");
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dump(regp);
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} else if ((imm & 0x0ffff0)==0x00200) {
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| 274 |
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// Dump a register
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int rid = (imm&0x0f)+rbase;
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printf("%8ld @%08x R[%2d] = 0x%08x\n", m_tickcount,
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m_core->v__DOT__swic__DOT__thecpu__DOT__ipc,
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| 278 |
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rid, regp[rid]);
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| 279 |
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} else if ((imm & 0x0ffff0)==0x00210) {
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| 280 |
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// Dump a user register
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| 281 |
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int rid = (imm&0x0f);
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| 282 |
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printf("%8ld @%08x uR[%2d] = 0x%08x\n", m_tickcount,
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m_core->v__DOT__swic__DOT__thecpu__DOT__ipc,
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| 284 |
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rid, regp[rid+16]);
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| 285 |
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} else if ((imm & 0x0ffff0)==0x00230) {
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| 286 |
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// SOUT[User Reg]
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| 287 |
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int rid = (imm&0x0f)+16;
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| 288 |
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printf("%c", regp[rid]&0x0ff);
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| 289 |
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} else if ((imm & 0x0fffe0)==0x00220) {
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| 290 |
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// SOUT[User Reg]
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| 291 |
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int rid = (imm&0x0f)+rbase;
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| 292 |
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printf("%c", regp[rid]&0x0ff);
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| 293 |
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} else if ((imm & 0x0fff00)==0x00400) {
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| 294 |
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// SOUT[Imm]
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| 295 |
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printf("%c", imm&0x0ff);
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| 296 |
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} else { // if ((insn & 0x0f7c00000)==0x77800000)
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| 297 |
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uint32_t immv = imm & 0x03fffff;
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| 298 |
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// Simm instruction that we dont recognize
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| 299 |
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// if (imm)
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// printf("SIM 0x%08x\n", immv);
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printf("SIM 0x%08x (ipc = %08x, upc = %08x)\n", immv,
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m_core->v__DOT__swic__DOT__thecpu__DOT__ipc,
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m_core->v__DOT__swic__DOT__thecpu__DOT__r_upc
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);
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} fflush(stdout);
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| 306 |
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}
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| 307 |
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bool on_tick(void) {
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| 309 |
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if (!m_done) {
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| 310 |
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tick();
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| 311 |
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return true; // Keep going 'til the kingdom comes
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| 312 |
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} else return false;
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| 313 |
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}
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| 314 |
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| 315 |
|
|
void tick(void) {
|
| 316 |
|
|
if (m_done)
|
| 317 |
|
|
return;
|
| 318 |
|
|
if ((m_tickcount & ((1<<28)-1))==0) {
|
| 319 |
|
|
double ticks_per_second = m_tickcount;
|
| 320 |
|
|
time_t seconds_passed = time(NULL)-m_start_time;
|
| 321 |
|
|
if (seconds_passed != 0) {
|
| 322 |
|
|
ticks_per_second /= (double)(time(NULL) - m_start_time);
|
| 323 |
|
|
printf(" ******** %.6f TICKS PER SECOND\n",
|
| 324 |
|
|
ticks_per_second);
|
| 325 |
|
|
}
|
| 326 |
|
|
}
|
| 327 |
|
|
|
| 328 |
|
|
if (m_halt_in_count > 0) {
|
| 329 |
|
|
if (m_halt_in_count-- <= 0) {
|
| 330 |
|
|
m_done = true;
|
| 331 |
|
|
}
|
| 332 |
|
|
}
|
| 333 |
|
|
|
| 334 |
|
|
if (TESTB<BASECLASS>::m_trace)
|
| 335 |
|
|
m_traceticks++;
|
| 336 |
|
|
|
| 337 |
|
|
// Set up the bus before any clock tick
|
| 338 |
|
|
#ifdef OLEDSIM_H
|
| 339 |
|
|
m_oled(m_core->o_oled_pmoden, m_core->o_oled_reset_n,
|
| 340 |
|
|
m_core->o_oled_vccen, m_core->o_oled_cs_n,
|
| 341 |
|
|
m_core->o_oled_sck, m_core->o_oled_dcn,
|
| 342 |
|
|
m_core->o_oled_mosi);
|
| 343 |
|
|
#endif
|
| 344 |
|
|
m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
|
| 345 |
|
|
m_core->o_qspi_sck, m_core->o_qspi_dat);
|
| 346 |
|
|
|
| 347 |
|
|
m_core->i_mdio = (*m_mid)((m_core->o_net_reset_n==0)?1:0, m_core->o_mdclk,
|
| 348 |
|
|
((m_core->o_mdwe)&&(!m_core->o_mdio))?0:1);
|
| 349 |
|
|
|
| 350 |
|
|
/*
|
| 351 |
|
|
printf("MDIO: %d %d %d %d/%d -> %d\n",
|
| 352 |
|
|
m_core->o_net_reset_n,
|
| 353 |
|
|
m_core->o_mdclk,
|
| 354 |
|
|
m_core->o_mdwe,
|
| 355 |
|
|
m_core->o_mdio,
|
| 356 |
|
|
((m_core->o_mdwe)&&(!m_core->o_mdio))?0:1,
|
| 357 |
|
|
m_core->i_mdio);
|
| 358 |
|
|
*/
|
| 359 |
|
|
|
| 360 |
|
|
m_core->i_aux_rx = m_uart(m_core->o_aux_tx,
|
| 361 |
|
|
m_core->v__DOT__console__DOT__uart_setup);
|
| 362 |
|
|
m_core->i_gps_rx = 1;
|
| 363 |
|
|
|
| 364 |
|
|
m_core->i_sd_data = m_sdcard((m_core->o_sd_data&8)?1:0,
|
| 365 |
|
|
m_core->o_sd_sck, m_core->o_sd_cmd);
|
| 366 |
|
|
m_core->i_sd_data &= 1;
|
| 367 |
|
|
m_core->i_sd_data |= (m_core->o_sd_data&0x0e);
|
| 368 |
|
|
|
| 369 |
|
|
// Turn the network into a simple loopback device.
|
| 370 |
|
|
if (++m_net_ticks>5)
|
| 371 |
|
|
m_net_ticks = 0;
|
| 372 |
|
|
m_core->i_net_rx_clk = (m_net_ticks >= 2)&&(m_net_ticks < 5);
|
| 373 |
|
|
m_core->i_net_tx_clk = (m_net_ticks >= 0)&&(m_net_ticks < 3);
|
| 374 |
|
|
if (!m_core->i_net_rx_clk) {
|
| 375 |
|
|
m_core->i_net_dv = m_core->o_net_tx_en;
|
| 376 |
|
|
m_core->i_net_rxd = m_core->o_net_txd;
|
| 377 |
|
|
m_core->i_net_crs = m_core->o_net_tx_en;
|
| 378 |
|
|
} m_core->i_net_rxerr = 0;
|
| 379 |
|
|
if (!m_core->o_net_reset_n) {
|
| 380 |
|
|
m_core->i_net_dv = 0;
|
| 381 |
|
|
m_core->i_net_crs= 0;
|
| 382 |
|
|
}
|
| 383 |
|
|
|
| 384 |
|
|
m_ram.apply(m_core->o_ram_cyc, m_core->o_ram_stb,
|
| 385 |
|
|
m_core->o_ram_we, m_core->o_ram_addr,
|
| 386 |
|
|
m_core->o_ram_wdata, m_core->o_ram_sel,
|
| 387 |
|
|
m_core->i_ram_ack, m_core->i_ram_stall,
|
| 388 |
|
|
m_core->i_ram_rdata);
|
| 389 |
|
|
|
| 390 |
|
|
PIPECMDR::tick();
|
| 391 |
|
|
|
| 392 |
|
|
// Sim instructions
|
| 393 |
|
|
if ((m_core->v__DOT__swic__DOT__thecpu__DOT__op_sim)
|
| 394 |
|
|
&&(m_core->v__DOT__swic__DOT__thecpu__DOT__op_valid)
|
| 395 |
|
|
&&(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_ce)
|
| 396 |
|
|
&&(!m_core->v__DOT__swic__DOT__thecpu__DOT__new_pc)) {
|
| 397 |
|
|
//
|
| 398 |
|
|
execsim(m_core->v__DOT__swic__DOT__thecpu__DOT__op_sim_immv);
|
| 399 |
|
|
}
|
| 400 |
|
|
|
| 401 |
|
|
// #define DEBUGGING_OUTPUT
|
| 402 |
|
|
#ifdef DEBUGGING_OUTPUT
|
| 403 |
|
|
bool writeout = false;
|
| 404 |
|
|
|
| 405 |
|
|
/*
|
| 406 |
|
|
// Ethernet triggers
|
| 407 |
|
|
if (m_core->o_net_tx_en)
|
| 408 |
|
|
writeout = true;
|
| 409 |
|
|
if (m_core->v__DOT__netctrl__DOT__n_rx_busy)
|
| 410 |
|
|
writeout = true;
|
| 411 |
|
|
if (m_core->v__DOT__netctrl__DOT__r_txd_en)
|
| 412 |
|
|
writeout = true;
|
| 413 |
|
|
if (m_core->v__DOT__netctrl__DOT__w_rxwr)
|
| 414 |
|
|
writeout = true;
|
| 415 |
|
|
*/
|
| 416 |
|
|
|
| 417 |
|
|
/*
|
| 418 |
|
|
// GPS Clock triggers
|
| 419 |
|
|
if (m_core->v__DOT__ppsck__DOT__tick)
|
| 420 |
|
|
writeout = true;
|
| 421 |
|
|
if (m_core->v__DOT__gps_step != m_gps_step) {
|
| 422 |
|
|
writeout = true;
|
| 423 |
|
|
// printf("STEP");
|
| 424 |
|
|
} if (m_core->v__DOT__gps_err != m_gps_err) {
|
| 425 |
|
|
writeout = true;
|
| 426 |
|
|
// printf("ERR");
|
| 427 |
|
|
} if (m_core->v__DOT__ppsck__DOT__step_correction != m_gps_stepc) {
|
| 428 |
|
|
writeout = true;
|
| 429 |
|
|
// printf("DSTP");
|
| 430 |
|
|
} if (m_core->v__DOT__ppsck__DOT__getnewstep__DOT__genblk2__DOT__genblk1__DOT__r_out != m_gps_newstep)
|
| 431 |
|
|
writeout = true;
|
| 432 |
|
|
*/
|
| 433 |
|
|
|
| 434 |
|
|
/*
|
| 435 |
|
|
m_gps_step = m_core->v__DOT__gps_step;
|
| 436 |
|
|
m_gps_err = m_core->v__DOT__gps_err;
|
| 437 |
|
|
m_gps_stepc= m_core->v__DOT__ppsck__DOT__step_correction;
|
| 438 |
|
|
m_gps_newstep=m_core->v__DOT__ppsck__DOT__getnewstep__DOT__genblk2__DOT__genblk1__DOT__r_out;
|
| 439 |
|
|
*/
|
| 440 |
|
|
|
| 441 |
|
|
if (m_core->o_oled_cs_n == 0)
|
| 442 |
|
|
writeout = true;
|
| 443 |
|
|
if (m_core->o_oled_sck == 0)
|
| 444 |
|
|
writeout = true;
|
| 445 |
|
|
if (m_core->v__DOT__rgbctrl__DOT__dev_wr)
|
| 446 |
|
|
writeout = true;
|
| 447 |
|
|
if (m_core->v__DOT__rgbctrl__DOT__r_busy)
|
| 448 |
|
|
writeout = true;
|
| 449 |
|
|
if (m_core->v__DOT__rgbctrl__DOT__dev_busy)
|
| 450 |
|
|
writeout = true;
|
| 451 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__instruction_decoder__DOT__r_lock)
|
| 452 |
|
|
writeout = true;
|
| 453 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__genblk3__DOT__r_op_lock)
|
| 454 |
|
|
writeout = true;
|
| 455 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__genblk9__DOT__r_prelock_stall)
|
| 456 |
|
|
writeout = true;
|
| 457 |
|
|
|
| 458 |
|
|
if (m_core->v__DOT__swic__DOT__dma_controller__DOT__dma_state != 0)
|
| 459 |
|
|
writeout = true;
|
| 460 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__genblk9__DOT__r_bus_lock)
|
| 461 |
|
|
writeout = true;
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
/*
|
| 465 |
|
|
// GPS Tracking triggers
|
| 466 |
|
|
if (m_core->v__DOT__ppsck__DOT__err_tick)
|
| 467 |
|
|
writeout = true;
|
| 468 |
|
|
if (m_core->v__DOT__ppsck__DOT__sub_tick)
|
| 469 |
|
|
writeout = true;
|
| 470 |
|
|
if (m_core->v__DOT__ppsck__DOT__shift_tick)
|
| 471 |
|
|
writeout = true;
|
| 472 |
|
|
if (m_core->v__DOT__ppsck__DOT__fltr_tick)
|
| 473 |
|
|
writeout = true;
|
| 474 |
|
|
if (m_core->v__DOT__ppsck__DOT__config_tick)
|
| 475 |
|
|
writeout = true;
|
| 476 |
|
|
if (m_core->v__DOT__ppsck__DOT__mpy_sync)
|
| 477 |
|
|
writeout = true;
|
| 478 |
|
|
if (m_core->v__DOT__ppsck__DOT__mpy_sync_two)
|
| 479 |
|
|
writeout = true;
|
| 480 |
|
|
if (m_core->v__DOT__ppsck__DOT__delay_step_clk)
|
| 481 |
|
|
writeout = true;
|
| 482 |
|
|
*/
|
| 483 |
|
|
|
| 484 |
|
|
// if (m_core->v__DOT__wbu_cyc)
|
| 485 |
|
|
// writeout = true;
|
| 486 |
|
|
// if (m_core->v__DOT__dwb_cyc)
|
| 487 |
|
|
// writeout = true;
|
| 488 |
|
|
|
| 489 |
|
|
// CPU Debugging triggers
|
| 490 |
|
|
// Write out if the CPU is active at all
|
| 491 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__master_ce)
|
| 492 |
|
|
writeout = true;
|
| 493 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__dbgv)
|
| 494 |
|
|
writeout = true;
|
| 495 |
|
|
if ((m_core->v__DOT__swic__DOT__dbg_cyc)&&(m_core->v__DOT__swic__DOT__dbg_stb))
|
| 496 |
|
|
writeout = true;
|
| 497 |
|
|
if ((m_core->v__DOT__swic__DOT__dbg_cyc)&&(m_core->v__DOT__swic__DOT__dbg_ack))
|
| 498 |
|
|
writeout = true;
|
| 499 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__pf_cyc)
|
| 500 |
|
|
writeout = true;
|
| 501 |
|
|
if (m_core->v__DOT__swic__DOT__thecpu__DOT__ipc < 0x10000000)
|
| 502 |
|
|
writeout = false;
|
| 503 |
|
|
|
| 504 |
|
|
writeout = true;
|
| 505 |
|
|
/*
|
| 506 |
|
|
*/
|
| 507 |
|
|
if ((writeout)||(m_last_writeout)) {
|
| 508 |
|
|
printf("%08lx:", m_tickcount);
|
| 509 |
|
|
|
| 510 |
|
|
/*
|
| 511 |
|
|
printf("%d/%02x %d/%02x%s ",
|
| 512 |
|
|
m_core->i_rx_stb, m_core->i_rx_data,
|
| 513 |
|
|
m_core->o_tx_stb, m_core->o_tx_data,
|
| 514 |
|
|
m_core->i_tx_busy?"/BSY":" ");
|
| 515 |
|
|
*/
|
| 516 |
|
|
|
| 517 |
|
|
// To get some understanding of what is on the bus,
|
| 518 |
|
|
// and hence some context for everything else,
|
| 519 |
|
|
// this offers a view of the bus.
|
| 520 |
|
|
printf("(%d,%d->%d)%s(%c:%s,%s->%s)",
|
| 521 |
|
|
m_core->v__DOT__wbu_cyc,
|
| 522 |
|
|
m_core->v__DOT__dwb_cyc, // was zip_cyc
|
| 523 |
|
|
m_core->v__DOT__wb_cyc,
|
| 524 |
|
|
"", // (m_core->v__DOT__wbu_zip_delay__DOT__r_stb)?"!":" ",
|
| 525 |
|
|
//
|
| 526 |
|
|
m_core->v__DOT__wbu_zip_arbiter__DOT__r_a_owner?'Z':'j',
|
| 527 |
|
|
(m_core->v__DOT__wbu_stb)?"1":" ", // WBU strobe
|
| 528 |
|
|
(m_core->v__DOT__swic__DOT__ext_stb)?"1":" ", // zip_stb
|
| 529 |
|
|
(m_core->v__DOT__wb_stb)?"1":" "); // m_core->v__DOT__wb_stb, output of delay(ed) strobe
|
| 530 |
|
|
//
|
| 531 |
|
|
printf("|%c[%08x/%08x]@%08x|%x %c%c%c",
|
| 532 |
|
|
(m_core->v__DOT__wb_we)?'W':'R',
|
| 533 |
|
|
m_core->v__DOT__wb_data,
|
| 534 |
|
|
m_core->v__DOT__dwb_idata,
|
| 535 |
|
|
m_core->v__DOT__wb_addr<<2,
|
| 536 |
|
|
m_core->v__DOT__wb_sel,
|
| 537 |
|
|
(m_core->v__DOT__dwb_ack)?'A':
|
| 538 |
|
|
(m_core->v__DOT____Vcellinp__genbus____pinNumber9)?'a':' ',
|
| 539 |
|
|
(m_core->v__DOT__dwb_stall)?'S':
|
| 540 |
|
|
(m_core->v__DOT____Vcellinp__genbus____pinNumber10)?'s':' ',
|
| 541 |
|
|
(m_core->v__DOT__wb_err)?'E':'.');
|
| 542 |
|
|
|
| 543 |
|
|
// CPU Pipeline debugging
|
| 544 |
|
|
printf("%s%s%s%s%s%s%s%s%s%s%s",
|
| 545 |
|
|
// (m_core->v__DOT__swic__DOT__dbg_ack)?"A":"-",
|
| 546 |
|
|
// (m_core->v__DOT__swic__DOT__dbg_stall)?"S":"-",
|
| 547 |
|
|
// (m_core->v__DOT__swic__DOT__sys_dbg_cyc)?"D":"-",
|
| 548 |
|
|
(m_core->v__DOT__swic__DOT__cpu_lcl_cyc)?"L":"-",
|
| 549 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_halted)?"Z":"-",
|
| 550 |
|
|
(m_core->v__DOT__swic__DOT__cpu_break)?"!":"-",
|
| 551 |
|
|
(m_core->v__DOT__swic__DOT__cmd_halt)?"H":"-",
|
| 552 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_gie)?"G":"-",
|
| 553 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__pf_cyc)?"P":"-",
|
| 554 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__pf_valid)?"V":"-",
|
| 555 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__pf_illegal)?"i":" ",
|
| 556 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__new_pc)?"N":"-",
|
| 557 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"G":"-",
|
| 558 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"L":"-");
|
| 559 |
|
|
printf("|%s%s%s%s%s%s",
|
| 560 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_dcd_valid)?"D":"-",
|
| 561 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__dcd_ce)?"d":"-",
|
| 562 |
|
|
"x", // (m_core->v__DOT__swic__DOT__thecpu__DOT__dcdA_stall)?"A":"-",
|
| 563 |
|
|
"x", // (m_core->v__DOT__swic__DOT__thecpu__DOT__dcdB_stall)?"B":"-",
|
| 564 |
|
|
"x", // (m_core->v__DOT__swic__DOT__thecpu__DOT__dcdF_stall)?"F":"-",
|
| 565 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__dcd_illegal)?"i":"-");
|
| 566 |
|
|
|
| 567 |
|
|
printf("|%s%s%s%s%s%s%s%s%s%s",
|
| 568 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__op_valid)?"O":"-",
|
| 569 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__op_ce)?"k":"-",
|
| 570 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__op_stall)?"s":"-",
|
| 571 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__op_illegal)?"i":"-",
|
| 572 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_op_break)?"B":"-",
|
| 573 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__genblk3__DOT__r_op_lock)?"L":"-",
|
| 574 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_op_pipe)?"P":"-",
|
| 575 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_break_pending)?"p":"-",
|
| 576 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_op_gie)?"G":"-",
|
| 577 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__op_valid_alu)?"A":"-");
|
| 578 |
|
|
printf("|%s%s%s%d",
|
| 579 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__genblk9__DOT__r_prelock_stall)?"P":".",
|
| 580 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__genblk9__DOT__r_prelock_primed)?"p":".",
|
| 581 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__genblk9__DOT__r_bus_lock)?"L":".",
|
| 582 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__genblk9__DOT__r_bus_lock);
|
| 583 |
|
|
printf("|%s%s%s%s%s",
|
| 584 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_ce)?"a":"-",
|
| 585 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_stall)?"s":"-",
|
| 586 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__doalu__DOT__r_busy)?"B":"-",
|
| 587 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_alu_gie)?"G":"-",
|
| 588 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_alu_illegal)?"i":"-");
|
| 589 |
|
|
printf("|%s%s%s%2x %s%s%s %2d %2d",
|
| 590 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__op_valid_mem)?"M":"-",
|
| 591 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__mem_ce)?"m":"-",
|
| 592 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__adf_ce_unconditional)?"!":"-",
|
| 593 |
|
|
(m_core->v__DOT__swic__DOT__cmd_addr),
|
| 594 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__bus_err)?"BE":" ",
|
| 595 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__ibus_err_flag)?"IB":" ",
|
| 596 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_ubus_err_flag)?"UB":" ",
|
| 597 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__domem__DOT__rdaddr,
|
| 598 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__domem__DOT__wraddr);
|
| 599 |
|
|
printf("|%s%s",
|
| 600 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__div_busy)?"D":"-",
|
| 601 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__div_error)?"E":"-");
|
| 602 |
|
|
printf("|%s%s[%2x]%08x",
|
| 603 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__wr_reg_ce)?"W":"-",
|
| 604 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__wr_flags_ce)?"F":"-",
|
| 605 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__wr_reg_id,
|
| 606 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__wr_gpreg_vl);
|
| 607 |
|
|
|
| 608 |
|
|
// Program counter debugging
|
| 609 |
|
|
printf(" PC0x%08x/%08x/%08x-I:%08x %s0x%08x%s",
|
| 610 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf_pc,
|
| 611 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__ipc,
|
| 612 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__r_upc,
|
| 613 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf_instruction,
|
| 614 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":
|
| 615 |
|
|
((m_core->v__DOT__swic__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_ljmp)?"JM":" "),
|
| 616 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc<<2,
|
| 617 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_clear_icache)?"-CLRC":" "
|
| 618 |
|
|
);
|
| 619 |
|
|
// More in-depth
|
| 620 |
|
|
printf(" [%c%08x,%c%08x,%c%08x]",
|
| 621 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__r_dcd_valid)?'D':'-',
|
| 622 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__dcd_pc<<2,
|
| 623 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__op_valid)?'O':'-',
|
| 624 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__op_pc<<2,
|
| 625 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_valid)?'A':'-',
|
| 626 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__r_alu_pc<<2);
|
| 627 |
|
|
|
| 628 |
|
|
// Prefetch debugging
|
| 629 |
|
|
printf(" [PC%08x,LST%08x]->[%d%s%s](%d,%08x/%08x)->%08x@%08x",
|
| 630 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf_pc<<2,
|
| 631 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__lastpc<<2,
|
| 632 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__rvsrc,
|
| 633 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__rvsrc)
|
| 634 |
|
|
?((m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__r_v_from_pc)?"P":" ")
|
| 635 |
|
|
:((m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__r_v_from_pc)?"p":" "),
|
| 636 |
|
|
(!m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__rvsrc)
|
| 637 |
|
|
?((m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__r_v_from_last)?"l":" ")
|
| 638 |
|
|
:((m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__r_v_from_last)?"L":" "),
|
| 639 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__isrc,
|
| 640 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__r_pc_cache,
|
| 641 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf__DOT__r_last_cache,
|
| 642 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf_instruction,
|
| 643 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__pf_instruction_pc<<2);
|
| 644 |
|
|
|
| 645 |
|
|
// Decode Stage debugging
|
| 646 |
|
|
// (nothing)
|
| 647 |
|
|
|
| 648 |
|
|
// Op Stage debugging
|
| 649 |
|
|
printf(" (Op %02x,%02x)(%08x,%08x->%02x)",
|
| 650 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__dcd_opn,
|
| 651 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__r_op_opn,
|
| 652 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__op_Av,
|
| 653 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__op_Bv,
|
| 654 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__r_op_R);
|
| 655 |
|
|
|
| 656 |
|
|
printf(" %s[",
|
| 657 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__wr_reg_ce?"WR":"--");
|
| 658 |
|
|
{ int reg;
|
| 659 |
|
|
const static char *rnames[] = {
|
| 660 |
|
|
"sR0", "sR1", "sR2", "sR3",
|
| 661 |
|
|
"sR4", "sR5", "sR6", "sR7",
|
| 662 |
|
|
"sR8", "sR9", "sRa", "sRb",
|
| 663 |
|
|
"sRc", "sSP", "sCC", "sPC",
|
| 664 |
|
|
"uR0", "uR1", "uR2", "uR3",
|
| 665 |
|
|
"uR4", "uR5", "uR6", "uR7",
|
| 666 |
|
|
"uR8", "uR9", "uRa", "uRb",
|
| 667 |
|
|
"uRc", "uSP", "uCC", "uPC"
|
| 668 |
|
|
};
|
| 669 |
|
|
reg = m_core->v__DOT__swic__DOT__thecpu__DOT__wr_reg_id & 0x01f;
|
| 670 |
|
|
printf("%s", rnames[reg]);
|
| 671 |
|
|
}
|
| 672 |
|
|
printf("]=%08x(%08x)",
|
| 673 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__wr_gpreg_vl,
|
| 674 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__wr_spreg_vl
|
| 675 |
|
|
);
|
| 676 |
|
|
|
| 677 |
|
|
printf(" %s[%s%s%s%s]",
|
| 678 |
|
|
m_core->v__DOT__swic__DOT__thecpu__DOT__wr_flags_ce?"F":"-",
|
| 679 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_flags&1)?"Z":".",
|
| 680 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_flags&2)?"C":".",
|
| 681 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_flags&4)?"N":".",
|
| 682 |
|
|
(m_core->v__DOT__swic__DOT__thecpu__DOT__alu_flags&8)?"V":".");
|
| 683 |
|
|
|
| 684 |
|
|
/*
|
| 685 |
|
|
printf(" DBG%s%s%s[%s/%02x]=%08x/%08x",
|
| 686 |
|
|
(m_core->v__DOT__swic__DOT__dbg_cyc)?"CYC":" ",
|
| 687 |
|
|
(m_core->v__DOT__swic__DOT__dbg_stb)?"STB":((m_core->v__DOT__swic__DOT__dbg_ack)?"ACK":" "),
|
| 688 |
|
|
((m_core->v__DOT__swic__DOT__dbg_cyc)&&(m_core->v__DOT__swic__DOT__dbg_stb))?((m_core->v__DOT__swic__DOT__dbg_we)?"-W":"-R"):" ",
|
| 689 |
|
|
(!m_core->v__DOT__swic__DOT__dbg_cyc) ? " ":
|
| 690 |
|
|
((m_core->v__DOT__swic__DOT__dbg_addr)?"D":"C"),
|
| 691 |
|
|
(m_core->v__DOT__swic__DOT__cmd_addr),
|
| 692 |
|
|
(m_core->v__DOT__swic__DOT__dbg_idata),
|
| 693 |
|
|
m_core->v__DOT__zip_dbg_data);
|
| 694 |
|
|
|
| 695 |
|
|
printf(" %s,0x%08x", (m_core->i_ram_ack)?"RCK":" ",
|
| 696 |
|
|
m_core->i_ram_rdata);
|
| 697 |
|
|
*/
|
| 698 |
|
|
|
| 699 |
|
|
|
| 700 |
|
|
/*
|
| 701 |
|
|
printf(" SDSPI[%d,%d(%d),(%d)]",
|
| 702 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy,
|
| 703 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
| 704 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_state,
|
| 705 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_rsp_state);
|
| 706 |
|
|
printf(" LL[%d,%2x->CK=%d/%2x,%s,ST=%2d,TX=%2x,RX=%2x->%d,%2x] ",
|
| 707 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_stb,
|
| 708 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_cmd_dat,
|
| 709 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_z_counter,
|
| 710 |
|
|
// (m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter==0)?1:0,
|
| 711 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_clk_counter,
|
| 712 |
|
|
(m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_idle)?"IDLE":" ",
|
| 713 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_state,
|
| 714 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_byte,
|
| 715 |
|
|
m_core->v__DOT__sdcard_controller__DOT__lowlevel__DOT__r_ireg,
|
| 716 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_stb,
|
| 717 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_out_dat
|
| 718 |
|
|
);
|
| 719 |
|
|
printf(" CRC=%02x/%2d",
|
| 720 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc,
|
| 721 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_cmd_crc_cnt);
|
| 722 |
|
|
printf(" SPI(%d,%d,%d/%d,%d)->?",
|
| 723 |
|
|
m_core->o_sf_cs_n,
|
| 724 |
|
|
m_core->o_sd_cs_n,
|
| 725 |
|
|
m_core->o_spi_sck, m_core->v__DOT__sdcard_sck,
|
| 726 |
|
|
m_core->o_spi_mosi);
|
| 727 |
|
|
|
| 728 |
|
|
printf(" CK=%d,LN=%d",
|
| 729 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_sdspi_clk,
|
| 730 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_lgblklen);
|
| 731 |
|
|
|
| 732 |
|
|
|
| 733 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_use_fifo){
|
| 734 |
|
|
printf(" FIFO");
|
| 735 |
|
|
if (m_core->v__DOT__sdcard_controller__DOT__r_fifo_wr)
|
| 736 |
|
|
printf("-WR(%04x,%d,%d,%d)",
|
| 737 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_reg,
|
| 738 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_rd_crc_stb,
|
| 739 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_pkt_state,
|
| 740 |
|
|
m_core->v__DOT__sdcard_controller__DOT__r_have_data_response_token);
|
| 741 |
|
|
else
|
| 742 |
|
|
printf("-RD(%04x,%d,%d,%d)",
|
| 743 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_reg,
|
| 744 |
|
|
m_core->v__DOT__sdcard_controller__DOT__fifo_wr_crc_stb,
|
| 745 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_state,
|
| 746 |
|
|
m_core->v__DOT__sdcard_controller__DOT__ll_fifo_wr_complete
|
| 747 |
|
|
);
|
| 748 |
|
|
}
|
| 749 |
|
|
*/
|
| 750 |
|
|
|
| 751 |
|
|
/*
|
| 752 |
|
|
// Network debugging
|
| 753 |
|
|
printf("ETH[TX:%s%s%x%s]",
|
| 754 |
|
|
(m_core->i_net_tx_clk)?"CK":" ",
|
| 755 |
|
|
(m_core->o_net_tx_en)?" ":"(",
|
| 756 |
|
|
m_core->o_net_txd,
|
| 757 |
|
|
(m_core->o_net_tx_en)?" ":")");
|
| 758 |
|
|
printf("/%s(%04x,%08x[%08x])",
|
| 759 |
|
|
(m_core->v__DOT__netctrl__DOT__n_tx_busy)?"BSY":" ",
|
| 760 |
|
|
m_core->v__DOT__netctrl__DOT__n_tx_addr,
|
| 761 |
|
|
m_core->v__DOT__netctrl__DOT__n_next_tx_data,
|
| 762 |
|
|
m_core->v__DOT__netctrl__DOT__n_tx_data);
|
| 763 |
|
|
printf("[RX:%s%s%s%s%x%s]",
|
| 764 |
|
|
(m_core->i_net_rx_clk)?"CK":" ",
|
| 765 |
|
|
(m_core->i_net_crs)?"CR":" ",
|
| 766 |
|
|
(m_core->i_net_rxerr)?"ER":" ",
|
| 767 |
|
|
(m_core->i_net_dv)?" ":"(",
|
| 768 |
|
|
m_core->i_net_rxd,
|
| 769 |
|
|
(m_core->i_net_dv)?" ":")");
|
| 770 |
|
|
printf("%s%s%s",
|
| 771 |
|
|
(m_core->v__DOT__netctrl__DOT__n_rx_valid)?"V":" ",
|
| 772 |
|
|
(m_core->v__DOT__netctrl__DOT__n_rx_clear)?"C":" ",
|
| 773 |
|
|
(m_core->v__DOT__netctrl__DOT__n_rx_net_err)?"E":" ");
|
| 774 |
|
|
printf("/%s(%04x,%s%08x)",
|
| 775 |
|
|
(m_core->v__DOT__netctrl__DOT__n_rx_busy)?"BSY":" ",
|
| 776 |
|
|
m_core->v__DOT__netctrl__DOT__w_rxaddr,
|
| 777 |
|
|
(m_core->v__DOT__netctrl__DOT__w_rxwr)?"W":" ",
|
| 778 |
|
|
m_core->v__DOT__netctrl__DOT__w_rxdata);
|
| 779 |
|
|
|
| 780 |
|
|
printf(" TXMAC %x%s -> %2x -> %x%s",
|
| 781 |
|
|
m_core->v__DOT__netctrl__DOT__r_txd,
|
| 782 |
|
|
(m_core->v__DOT__netctrl__DOT__r_txd_en)?"!":" ",
|
| 783 |
|
|
(m_core->v__DOT__netctrl__DOT__txmaci__DOT__r_pos),
|
| 784 |
|
|
m_core->v__DOT__netctrl__DOT__w_macd,
|
| 785 |
|
|
(m_core->v__DOT__netctrl__DOT__w_macen)?"!":" ");
|
| 786 |
|
|
printf(" TXCRC %x%s ->%2x/0x%08x-> %x%s",
|
| 787 |
|
|
m_core->v__DOT__netctrl__DOT__w_padd,
|
| 788 |
|
|
(m_core->v__DOT__netctrl__DOT__w_paden)?"!":" ",
|
| 789 |
|
|
m_core->v__DOT__netctrl__DOT__txcrci__DOT__r_p,
|
| 790 |
|
|
m_core->v__DOT__netctrl__DOT__txcrci__DOT__r_crc,
|
| 791 |
|
|
m_core->v__DOT__netctrl__DOT__w_txcrcd,
|
| 792 |
|
|
(m_core->v__DOT__netctrl__DOT__w_txcrcen)?"!":" ");
|
| 793 |
|
|
|
| 794 |
|
|
printf(" RXCRC %x%s -> 0x%08x/%2x/%2x/%s -> %x%s",
|
| 795 |
|
|
m_core->v__DOT__netctrl__DOT__w_npred,
|
| 796 |
|
|
(m_core->v__DOT__netctrl__DOT__w_npre)?"!":" ",
|
| 797 |
|
|
m_core->v__DOT__netctrl__DOT__rxcrci__DOT__r_crc,
|
| 798 |
|
|
(m_core->v__DOT__netctrl__DOT__rxcrci__DOT__r_mq),
|
| 799 |
|
|
(m_core->v__DOT__netctrl__DOT__rxcrci__DOT__r_mp),
|
| 800 |
|
|
(m_core->v__DOT__netctrl__DOT__rxcrci__DOT__r_err)?"E":" ",
|
| 801 |
|
|
m_core->v__DOT__netctrl__DOT__w_rxcrcd,
|
| 802 |
|
|
(m_core->v__DOT__netctrl__DOT__w_rxcrc)?"!":" ");
|
| 803 |
|
|
|
| 804 |
|
|
printf(" RXIP %x%s ->%4x%s->%4x/%2d/%2d/%s",
|
| 805 |
|
|
m_core->v__DOT__netctrl__DOT__w_rxcrcd,
|
| 806 |
|
|
(m_core->v__DOT__netctrl__DOT__w_rxcrc)?"!":" ",
|
| 807 |
|
|
(m_core->v__DOT__netctrl__DOT__rxipci__DOT__r_word)&0x0ffff,
|
| 808 |
|
|
(m_core->v__DOT__netctrl__DOT__rxipci__DOT__r_v)?"!":" ",
|
| 809 |
|
|
(m_core->v__DOT__netctrl__DOT__rxipci__DOT__r_check)&0x0ffff,
|
| 810 |
|
|
(m_core->v__DOT__netctrl__DOT__rxipci__DOT__r_idx),
|
| 811 |
|
|
(m_core->v__DOT__netctrl__DOT__rxipci__DOT__r_hlen),
|
| 812 |
|
|
(m_core->v__DOT__netctrl__DOT__w_iperr)?"E"
|
| 813 |
|
|
:(m_core->v__DOT__netctrl__DOT__rxipci__DOT__r_ip)?" ":"z");
|
| 814 |
|
|
printf(" RXMAC %x%s ->%2x-> %x%s",
|
| 815 |
|
|
m_core->v__DOT__netctrl__DOT__w_rxcrcd,
|
| 816 |
|
|
(m_core->v__DOT__netctrl__DOT__w_rxcrc)?"!":" ",
|
| 817 |
|
|
(m_core->v__DOT__netctrl__DOT__rxmaci__DOT__r_p)&0x0ff,
|
| 818 |
|
|
m_core->v__DOT__netctrl__DOT__w_rxmacd,
|
| 819 |
|
|
(m_core->v__DOT__netctrl__DOT__w_rxmac)?"!":" ");
|
| 820 |
|
|
*/
|
| 821 |
|
|
|
| 822 |
|
|
/*
|
| 823 |
|
|
// Flash debugging support
|
| 824 |
|
|
printf("%s/%s %s %s[%s%s%s%s%s] %s@%08x[%08x/%08x] -- SPI %s%s[%x/%x](%d,%d)",
|
| 825 |
|
|
((m_core->v__DOT__wb_stb)&&((m_core->v__DOT__skipaddr>>3)==1))?"D":" ",
|
| 826 |
|
|
((m_core->v__DOT__wb_stb)&&(m_core->v__DOT__flctl_sel))?"C":" ",
|
| 827 |
|
|
(m_core->v__DOT__flashmem__DOT__bus_wb_stall)?"STALL":" ",
|
| 828 |
|
|
(m_core->v__DOT__flash_ack)?"ACK":" ",
|
| 829 |
|
|
(m_core->v__DOT__flashmem__DOT__bus_wb_ack)?"BS":" ",
|
| 830 |
|
|
(m_core->v__DOT__flashmem__DOT__rd_data_ack)?"RD":" ",
|
| 831 |
|
|
(m_core->v__DOT__flashmem__DOT__ew_data_ack)?"EW":" ",
|
| 832 |
|
|
(m_core->v__DOT__flashmem__DOT__id_data_ack)?"ID":" ",
|
| 833 |
|
|
(m_core->v__DOT__flashmem__DOT__ct_data_ack)?"CT":" ",
|
| 834 |
|
|
(m_core->v__DOT__wb_we)?"W":"R",
|
| 835 |
|
|
(m_core->v__DOT__wb_addr),
|
| 836 |
|
|
(m_core->v__DOT__wb_data),
|
| 837 |
|
|
(m_core->v__DOT__flash_data),
|
| 838 |
|
|
(m_core->o_qspi_cs_n)?"CS":" ",
|
| 839 |
|
|
(m_core->o_qspi_sck)?"CK":" ",
|
| 840 |
|
|
(m_core->o_qspi_dat),
|
| 841 |
|
|
(m_core->i_qspi_dat),
|
| 842 |
|
|
(m_core->o_qspi_dat)&1,
|
| 843 |
|
|
((m_core->i_qspi_dat)&2)?1:0),
|
| 844 |
|
|
|
| 845 |
|
|
printf(" REQ[%s%s%s%s]",
|
| 846 |
|
|
m_core->v__DOT__flashmem__DOT__rd_qspi_req?"RD":" ",
|
| 847 |
|
|
m_core->v__DOT__flashmem__DOT__ew_qspi_req?"EW":" ",
|
| 848 |
|
|
m_core->v__DOT__flashmem__DOT__id_qspi_req?"ID":" ",
|
| 849 |
|
|
m_core->v__DOT__flashmem__DOT__ct_qspi_req?"CT":" ");
|
| 850 |
|
|
|
| 851 |
|
|
printf(" %s[%s%2d%s%s0x%08x]",
|
| 852 |
|
|
(m_core->v__DOT__flashmem__DOT__spi_wr)?"CMD":" ",
|
| 853 |
|
|
(m_core->v__DOT__flashmem__DOT__spi_hold)?"HLD":" ",
|
| 854 |
|
|
(m_core->v__DOT__flashmem__DOT__spi_len+1)*8,
|
| 855 |
|
|
(m_core->v__DOT__flashmem__DOT__spi_dir)?"RD":"WR",
|
| 856 |
|
|
(m_core->v__DOT__flashmem__DOT__spi_spd)?"Q":" ",
|
| 857 |
|
|
m_core->v__DOT__flashmem__DOT__spi_word);
|
| 858 |
|
|
|
| 859 |
|
|
printf(" STATE[%2x%s,%2x%s,%2x%s,%2x%s]",
|
| 860 |
|
|
m_core->v__DOT__flashmem__DOT__rdproc__DOT__rd_state, (m_core->v__DOT__flashmem__DOT__rd_spi_wr)?"W":" ",
|
| 861 |
|
|
m_core->v__DOT__flashmem__DOT__ewproc__DOT__wr_state, (m_core->v__DOT__flashmem__DOT__ew_spi_wr)?"W":" ",
|
| 862 |
|
|
m_core->v__DOT__flashmem__DOT__idotp__DOT__id_state, (m_core->v__DOT__flashmem__DOT__id_spi_wr)?"W":" ",
|
| 863 |
|
|
m_core->v__DOT__flashmem__DOT__ctproc__DOT__ctstate, (m_core->v__DOT__flashmem__DOT__ct_spi_wr)?"W":" ");
|
| 864 |
|
|
printf("%s%s%s%s",
|
| 865 |
|
|
(m_core->v__DOT__flashmem__DOT__rdproc__DOT__accepted)?"RD-ACC":"",
|
| 866 |
|
|
(m_core->v__DOT__flashmem__DOT__ewproc__DOT__accepted)?"EW-ACC":"",
|
| 867 |
|
|
(m_core->v__DOT__flashmem__DOT__idotp__DOT__accepted)?"ID-ACC":"",
|
| 868 |
|
|
(m_core->v__DOT__flashmem__DOT__ctproc__DOT__accepted)?"CT-ACC":"");
|
| 869 |
|
|
|
| 870 |
|
|
printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
|
| 871 |
|
|
(m_core->v__DOT__flashmem__DOT__preproc__DOT__pending)?" PENDING":"",
|
| 872 |
|
|
(m_core->v__DOT__flashmem__DOT__preproc__DOT__lcl_key)?" KEY":"",
|
| 873 |
|
|
(m_core->v__DOT__flashmem__DOT__preproc__DOT__ctreg_stb)?" CTSTB":"",
|
| 874 |
|
|
(m_core->v__DOT__flashmem__DOT__bus_ctreq)?" BUSCTRL":"",
|
| 875 |
|
|
(m_core->v__DOT__flashmem__DOT__bus_other_req)?" BUSOTHER":"",
|
| 876 |
|
|
(m_core->v__DOT__flashmem__DOT__preproc__DOT__wp)?" WRWP":"",
|
| 877 |
|
|
(m_core->v__DOT__flashmem__DOT__bus_wip)?" WIP":"",
|
| 878 |
|
|
(m_core->v__DOT__flashmem__DOT__ewproc__DOT__cyc)?" WRCYC":"",
|
| 879 |
|
|
(m_core->v__DOT__flashmem__DOT__bus_pipewr)?" WRPIPE":"",
|
| 880 |
|
|
(m_core->v__DOT__flashmem__DOT__bus_endwr)?" ENDWR":"",
|
| 881 |
|
|
(m_core->v__DOT__flashmem__DOT__ct_ack)?" CTACK":"",
|
| 882 |
|
|
(m_core->v__DOT__flashmem__DOT__rd_bus_ack)?" RDACK":"",
|
| 883 |
|
|
(m_core->v__DOT__flashmem__DOT__id_bus_ack)?" IDACK":"",
|
| 884 |
|
|
(m_core->v__DOT__flashmem__DOT__ew_bus_ack)?" EWACK":"",
|
| 885 |
|
|
(m_core->v__DOT__flashmem__DOT__preproc__DOT__lcl_ack)?" LCLACK":"",
|
| 886 |
|
|
(m_core->v__DOT__flashmem__DOT__rdproc__DOT__r_leave_xip)?" LVXIP":"",
|
| 887 |
|
|
(m_core->v__DOT__flashmem__DOT__preproc__DOT__new_req)?" NREQ":"");
|
| 888 |
|
|
*/
|
| 889 |
|
|
|
| 890 |
|
|
|
| 891 |
|
|
/*
|
| 892 |
|
|
// Debugging the GPS tracking circuit
|
| 893 |
|
|
printf("COUNT %016lx STEP %016lx+%08x->%016lx ERR %016lx %s",
|
| 894 |
|
|
m_core->v__DOT__gps_now,
|
| 895 |
|
|
m_core->v__DOT__gps_step,
|
| 896 |
|
|
m_core->v__DOT__ppsck__DOT__step_correction,
|
| 897 |
|
|
m_core->v__DOT__ppsck__DOT__getnewstep__DOT__genblk2__DOT__genblk1__DOT__r_out,
|
| 898 |
|
|
m_core->v__DOT__gps_err,
|
| 899 |
|
|
(m_core->v__DOT__ppsck__DOT__tick)?"TICK":" ");
|
| 900 |
|
|
*/
|
| 901 |
|
|
|
| 902 |
|
|
|
| 903 |
|
|
/*
|
| 904 |
|
|
// Debug the OLED
|
| 905 |
|
|
|
| 906 |
|
|
{ const char *pwr; int pwrk;
|
| 907 |
|
|
if (m_core->o_oled_pmoden) {
|
| 908 |
|
|
if (!m_core->o_oled_reset_n)
|
| 909 |
|
|
pwr = "RST";
|
| 910 |
|
|
else if (m_core->o_oled_vccen)
|
| 911 |
|
|
pwr = "ON ";
|
| 912 |
|
|
else
|
| 913 |
|
|
pwr = "VIO";
|
| 914 |
|
|
} else if (m_core->o_oled_vccen)
|
| 915 |
|
|
pwr = "ERR";
|
| 916 |
|
|
else
|
| 917 |
|
|
pwr = "OFF";
|
| 918 |
|
|
pwrk = (m_core->o_oled_reset_n)?4:0;
|
| 919 |
|
|
pwrk|= (m_core->o_oled_vccen)?2:0;
|
| 920 |
|
|
pwrk|= (m_core->o_oled_pmoden);
|
| 921 |
|
|
// First the top-level ports
|
| 922 |
|
|
printf(" OLED[%s/%d,%s%s%s-%d]",
|
| 923 |
|
|
pwr, pwrk,
|
| 924 |
|
|
(!m_core->o_oled_cs_n)?"CS":" ",
|
| 925 |
|
|
(m_core->o_oled_sck)?"CK":" ",
|
| 926 |
|
|
(m_core->o_oled_dcn)?"/D":"/C",
|
| 927 |
|
|
(m_core->o_oled_mosi));
|
| 928 |
|
|
}
|
| 929 |
|
|
// Now the low-level internals
|
| 930 |
|
|
printf("LL[");
|
| 931 |
|
|
switch(m_core->v__DOT__rgbctrl__DOT__lwlvl__DOT__state){
|
| 932 |
|
|
case 0: printf("I,"); break;
|
| 933 |
|
|
case 1: printf("S,"); break;
|
| 934 |
|
|
case 2: printf("B,"); break;
|
| 935 |
|
|
case 3: printf("R,"); break;
|
| 936 |
|
|
case 4: printf("!,"); break;
|
| 937 |
|
|
case 5: printf(".,"); break;
|
| 938 |
|
|
default: printf("U%d",
|
| 939 |
|
|
m_core->v__DOT__rgbctrl__DOT__lwlvl__DOT__state);
|
| 940 |
|
|
}
|
| 941 |
|
|
printf("%2d,%s%2d,%08x]",
|
| 942 |
|
|
m_core->v__DOT__rgbctrl__DOT__lwlvl__DOT__spi_len,
|
| 943 |
|
|
(m_core->v__DOT__rgbctrl__DOT__lwlvl__DOT__pre_last_counter)?"P":" ",
|
| 944 |
|
|
|
| 945 |
|
|
m_core->v__DOT__rgbctrl__DOT__lwlvl__DOT__counter,
|
| 946 |
|
|
m_core->v__DOT__rgbctrl__DOT__lwlvl__DOT__r_word);
|
| 947 |
|
|
printf("[%s%s%s/%2d/%d]",
|
| 948 |
|
|
(m_core->v__DOT__rgbctrl__DOT__dev_wr)?"W":" ",
|
| 949 |
|
|
(m_core->v__DOT__rgbctrl__DOT__r_busy)?"BSY":" ",
|
| 950 |
|
|
(m_core->v__DOT__rgbctrl__DOT__dev_busy)?"D-BSY":" ",
|
| 951 |
|
|
m_core->v__DOT__rgbctrl__DOT__r_len,
|
| 952 |
|
|
m_core->v__DOT__rgbctrl__DOT__dev_len);
|
| 953 |
|
|
printf((m_core->v__DOT__oled_int)?"I":" "); // And the interrupt
|
| 954 |
|
|
*/
|
| 955 |
|
|
|
| 956 |
|
|
/*
|
| 957 |
|
|
// Debug the DMA
|
| 958 |
|
|
printf(" DMAC[%d]: %08x/%08x/%08x(%03x)%d%d%d%d -- (%d,%d,%c)%c%c:@%08x-[%4d,%4d/%4d,%4d-#%4d]%08x",
|
| 959 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__dma_state,
|
| 960 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_waddr,
|
| 961 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_raddr,
|
| 962 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_len,
|
| 963 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_blocklen_sub_one,
|
| 964 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__last_read_request,
|
| 965 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__last_read_ack,
|
| 966 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__last_write_request,
|
| 967 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__last_write_ack,
|
| 968 |
|
|
m_core->v__DOT__swic__DOT__dc_cyc,
|
| 969 |
|
|
// m_core->v__DOT__swic__DOT__dc_stb,
|
| 970 |
|
|
(m_core->v__DOT__swic__DOT__dma_controller__DOT__dma_state == 2)?1:0,
|
| 971 |
|
|
|
| 972 |
|
|
((m_core->v__DOT__swic__DOT__dma_controller__DOT__dma_state == 4)
|
| 973 |
|
|
||(m_core->v__DOT__swic__DOT__dma_controller__DOT__dma_state == 5)
|
| 974 |
|
|
||(m_core->v__DOT__swic__DOT__dma_controller__DOT__dma_state == 6))?'W':'R',
|
| 975 |
|
|
//(m_core->v__DOT__swic__DOT__dc_we)?'W':'R',
|
| 976 |
|
|
(m_core->v__DOT__swic__DOT__dc_ack)?'A':' ',
|
| 977 |
|
|
(m_core->v__DOT__swic__DOT__dc_stall)?'S':' ',
|
| 978 |
|
|
m_core->v__DOT__swic__DOT__dc_addr,
|
| 979 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__rdaddr,
|
| 980 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__nread,
|
| 981 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__nracks,
|
| 982 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__nwacks,
|
| 983 |
|
|
m_core->v__DOT__swic__DOT__dma_controller__DOT__nwritten,
|
| 984 |
|
|
m_core->v__DOT__swic__DOT__dc_data);
|
| 985 |
|
|
printf((m_core->v__DOT__swic__DOT__dma_controller__DOT__trigger)?"T":" ");
|
| 986 |
|
|
printf((m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_incs)?"+":".");
|
| 987 |
|
|
printf((m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_incd)?"+":".");
|
| 988 |
|
|
printf("%s[%2x]",
|
| 989 |
|
|
(m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_on_dev_trigger)?"!":" ",
|
| 990 |
|
|
(m_core->v__DOT__swic__DOT__dma_controller__DOT__cfg_dev_trigger));
|
| 991 |
|
|
*/
|
| 992 |
|
|
|
| 993 |
|
|
printf(" INT:0x%08x/0x%08x",
|
| 994 |
|
|
m_core->v__DOT__swic__DOT__main_int_vector,
|
| 995 |
|
|
m_core->v__DOT__swic__DOT__alt_int_vector);
|
| 996 |
|
|
|
| 997 |
|
|
printf("\n"); fflush(stdout);
|
| 998 |
|
|
} m_last_writeout = writeout;
|
| 999 |
|
|
#endif
|
| 1000 |
|
|
|
| 1001 |
|
|
/*
|
| 1002 |
|
|
if (m_core->v__DOT__swic__DOT__cpu_break) {
|
| 1003 |
|
|
m_bomb++;
|
| 1004 |
|
|
} else if (m_bomb) {
|
| 1005 |
|
|
if (m_bomb++ > 12)
|
| 1006 |
|
|
m_done = true;
|
| 1007 |
|
|
fprintf(stderr, "BREAK-BREAK-BREAK (m_bomb = %d)%s\n",
|
| 1008 |
|
|
m_bomb, (m_done)?" -- DONE!":"");
|
| 1009 |
|
|
}
|
| 1010 |
|
|
*/
|
| 1011 |
|
|
}
|
| 1012 |
|
|
|
| 1013 |
|
|
bool done(void) {
|
| 1014 |
|
|
if (!m_trace)
|
| 1015 |
|
|
return m_done;
|
| 1016 |
|
|
else
|
| 1017 |
|
|
return (m_done)||(m_traceticks > 6000000);
|
| 1018 |
|
|
}
|
| 1019 |
|
|
};
|
| 1020 |
|
|
|
| 1021 |
|
|
TESTBENCH *tb;
|
| 1022 |
|
|
|
| 1023 |
|
|
void busmaster_kill(int v) {
|
| 1024 |
|
|
tb->close();
|
| 1025 |
|
|
fprintf(stderr, "KILLED!!\n");
|
| 1026 |
|
|
exit(EXIT_SUCCESS);
|
| 1027 |
|
|
}
|
| 1028 |
|
|
|
| 1029 |
|
|
void usage(void) {
|
| 1030 |
|
|
puts("USAGE: busmaster_tb [-cdpsth] <ZipElfProgram> <SDCardBackFile>\n"
|
| 1031 |
|
|
"\n"
|
| 1032 |
|
|
" -c Copies all FPGA control/command communications to the\n"
|
| 1033 |
|
|
" standard output\n"
|
| 1034 |
|
|
" -d Sets the debug flag. This turns on the trace feature, dumping\n"
|
| 1035 |
|
|
" the trace to trace.vcd by default. This can be overridden by\n"
|
| 1036 |
|
|
" the -t option\n"
|
| 1037 |
|
|
" -h Prints this usage statement\n"
|
| 1038 |
|
|
" -p # Sets the TCP/IP port number for the command port\n"
|
| 1039 |
|
|
" -s # Sets the TCP/IP port number for the simulated serial port\n"
|
| 1040 |
|
|
" -t <fname> Creates a VCD trace file with the name <fname>\n");
|
| 1041 |
|
|
}
|
| 1042 |
|
|
|
| 1043 |
|
|
int main(int argc, char **argv) {
|
| 1044 |
|
|
const char *elfload = NULL, *sdload = "/dev/zero",
|
| 1045 |
|
|
*trace_file = NULL; // "trace.vcd";
|
| 1046 |
|
|
bool debug_flag = false, willexit = false;
|
| 1047 |
|
|
int fpga_port = FPGAPORT, serial_port = -(FPGAPORT+1);
|
| 1048 |
|
|
int copy_comms_to_stdout = -1;
|
| 1049 |
|
|
#ifdef OLEDSIM_H
|
| 1050 |
|
|
Gtk::Main main_instance(argc, argv);
|
| 1051 |
|
|
#endif
|
| 1052 |
|
|
Verilated::commandArgs(argc, argv);
|
| 1053 |
|
|
|
| 1054 |
|
|
for(int argn=1; argn < argc; argn++) {
|
| 1055 |
|
|
if (argv[argn][0] == '-') for(int j=1;
|
| 1056 |
|
|
(j<512)&&(argv[argn][j]);j++) {
|
| 1057 |
|
|
switch(tolower(argv[argn][j])) {
|
| 1058 |
|
|
case 'c': copy_comms_to_stdout = 1; break;
|
| 1059 |
|
|
case 'd': debug_flag = true;
|
| 1060 |
|
|
if (trace_file == NULL)
|
| 1061 |
|
|
trace_file = "trace.vcd";
|
| 1062 |
|
|
break;
|
| 1063 |
|
|
case 'p': fpga_port = atoi(argv[++argn]); j=1000; break;
|
| 1064 |
|
|
case 's': serial_port=atoi(argv[++argn]); j=1000; break;
|
| 1065 |
|
|
case 't': trace_file = argv[++argn]; j=1000; break;
|
| 1066 |
|
|
case 'h': usage(); break;
|
| 1067 |
|
|
default:
|
| 1068 |
|
|
fprintf(stderr, "ERR: Unexpected flag, -%c\n\n",
|
| 1069 |
|
|
argv[argn][j]);
|
| 1070 |
|
|
usage();
|
| 1071 |
|
|
break;
|
| 1072 |
|
|
}
|
| 1073 |
|
|
} else if (iself(argv[argn])) {
|
| 1074 |
|
|
elfload = argv[argn];
|
| 1075 |
|
|
} else if (0 == access(argv[argn], R_OK)) {
|
| 1076 |
|
|
sdload = argv[argn];
|
| 1077 |
|
|
} else {
|
| 1078 |
|
|
fprintf(stderr, "ERR: Cannot read %s\n", argv[argn]);
|
| 1079 |
|
|
perror("O/S Err:");
|
| 1080 |
|
|
exit(EXIT_FAILURE);
|
| 1081 |
|
|
}
|
| 1082 |
|
|
}
|
| 1083 |
|
|
|
| 1084 |
|
|
if (elfload) {
|
| 1085 |
|
|
if (serial_port < 0)
|
| 1086 |
|
|
serial_port = 0;
|
| 1087 |
|
|
if (copy_comms_to_stdout < 0)
|
| 1088 |
|
|
copy_comms_to_stdout = 0;
|
| 1089 |
|
|
tb = new TESTBENCH(fpga_port, serial_port,
|
| 1090 |
|
|
(copy_comms_to_stdout)?true:false, debug_flag);
|
| 1091 |
|
|
willexit = true;
|
| 1092 |
|
|
} else {
|
| 1093 |
|
|
if (serial_port < 0)
|
| 1094 |
|
|
serial_port = -serial_port;
|
| 1095 |
|
|
if (copy_comms_to_stdout < 0)
|
| 1096 |
|
|
copy_comms_to_stdout = 1;
|
| 1097 |
|
|
tb = new TESTBENCH(fpga_port, serial_port,
|
| 1098 |
|
|
(copy_comms_to_stdout)?true:false, debug_flag);
|
| 1099 |
|
|
}
|
| 1100 |
|
|
|
| 1101 |
|
|
if (debug_flag) {
|
| 1102 |
|
|
printf("Opening Bus-master with\n");
|
| 1103 |
|
|
printf("\tDebug Access port = %d\n", fpga_port);
|
| 1104 |
|
|
printf("\tSerial Console = %d%s\n", serial_port,
|
| 1105 |
|
|
(serial_port == 0) ? " (Standard output)" : "");
|
| 1106 |
|
|
printf("\tDebug comms will%s be copied to the standard output%s.",
|
| 1107 |
|
|
(copy_comms_to_stdout)?"":" not",
|
| 1108 |
|
|
((copy_comms_to_stdout)&&(serial_port == 0))
|
| 1109 |
|
|
? " as well":"");
|
| 1110 |
|
|
printf("\tVCD File = %s\n", trace_file);
|
| 1111 |
|
|
} if (trace_file)
|
| 1112 |
|
|
tb->trace(trace_file);
|
| 1113 |
|
|
signal(SIGINT, busmaster_kill);
|
| 1114 |
|
|
|
| 1115 |
|
|
tb->reset();
|
| 1116 |
|
|
tb->setsdcard(sdload);
|
| 1117 |
|
|
|
| 1118 |
|
|
if (elfload) {
|
| 1119 |
|
|
uint32_t entry;
|
| 1120 |
|
|
ELFSECTION **secpp = NULL, *secp;
|
| 1121 |
|
|
elfread(elfload, entry, secpp);
|
| 1122 |
|
|
|
| 1123 |
|
|
if (secpp) for(int i=0; secpp[i]->m_len; i++) {
|
| 1124 |
|
|
secp = secpp[i];
|
| 1125 |
|
|
tb->load(secp->m_start, secp->m_data, secp->m_len);
|
| 1126 |
|
|
}
|
| 1127 |
|
|
|
| 1128 |
|
|
tb->m_core->v__DOT__swic__DOT__thecpu__DOT__ipc = entry;
|
| 1129 |
|
|
tb->tick();
|
| 1130 |
|
|
tb->m_core->v__DOT__swic__DOT__thecpu__DOT__ipc = entry;
|
| 1131 |
|
|
tb->m_core->v__DOT__swic__DOT__cmd_halt = 0;
|
| 1132 |
|
|
tb->tick();
|
| 1133 |
|
|
}
|
| 1134 |
|
|
|
| 1135 |
|
|
#ifdef OLEDSIM_H
|
| 1136 |
|
|
Gtk::Main::run(tb->m_oled);
|
| 1137 |
|
|
#else
|
| 1138 |
|
|
if (willexit) {
|
| 1139 |
|
|
while(!tb->done())
|
| 1140 |
|
|
tb->tick();
|
| 1141 |
|
|
} else
|
| 1142 |
|
|
while(!tb->done())
|
| 1143 |
|
|
tb->tick();
|
| 1144 |
|
|
|
| 1145 |
|
|
#endif
|
| 1146 |
|
|
|
| 1147 |
|
|
exit(0);
|
| 1148 |
|
|
}
|
| 1149 |
|
|
|
