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[/] [openarty/] [trunk/] [sw/] [host/] [etxscope.cpp] - Blame information for rev 30

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1 30 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    etxscope.cpp
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//
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// Project:     XuLA2-LX25 SoC based upon the ZipCPU
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//
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// Purpose:     This file decodes the debug bits produced by the enetpackets.v
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//              Verilog module, and stored in a Wishbone Scope.  It is useful
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//      for determining if the packet transmitter works at all or not.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <strings.h>
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#include <ctype.h>
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#include <string.h>
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#include <signal.h>
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#include <assert.h>
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#include "port.h"
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#include "regdefs.h"
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#include "scopecls.h"
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#define WBSCOPE         R_NETSCOPE
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#define WBSCOPEDATA     R_NETSCOPED
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FPGA    *m_fpga;
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void    closeup(int v) {
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        m_fpga->kill();
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        exit(0);
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}
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class   ETXSCOPE : public SCOPE {
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public:
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        ETXSCOPE(FPGA *fpga, unsigned addr, bool vecread = true)
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                : SCOPE(fpga, addr, false, vecread) {};
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        ~ETXSCOPE(void) {}
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        virtual void    decode(DEVBUS::BUSW val) const {
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                int     trigger, addr, cancel, cmd, complete, busy, en, txd;
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                int     lrxclk, ltxclk, txstb;
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                trigger = (val>>31)&1;
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                ltxclk  = (val>>30)&1;
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                lrxclk  = (val>>29)&1;
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                addr    = (val>>10)&0x0ffff;
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                txstb   = (val>> 9)&1;
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                cancel  = (val>> 8)&1;
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                cmd     = (val>> 7)&1;
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                complete= (val>> 6)&1;
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                busy    = (val>> 5)&1;
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                en      = (val>> 4)&1;
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                txd     = (val    )&15;
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                printf("%s %s %s ",
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                        (lrxclk)?"LRX":"   ",
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                        (ltxclk)?"LTX":"   ",
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                        (txstb)?"TXSTB":"     ");
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                printf("%s %04x %s%s%s%s %s/%x",
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                        (trigger)?"TR":"  ",
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                        (addr),
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                        (cancel)?"X":"   ",
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                        (cmd)?" CMD":"    ",
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                        (complete)?"DON":"   ",
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                        (busy)?"BSY":"   ",
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                        (en)?"EN":"  ", txd);
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        }
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};
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int main(int argc, char **argv) {
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        FPGAOPEN(m_fpga);
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        signal(SIGSTOP, closeup);
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        signal(SIGHUP, closeup);
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        ETXSCOPE *scope = new ETXSCOPE(m_fpga, WBSCOPE);
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        if (!scope->ready()) {
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                printf("Scope is not yet ready:\n");
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                scope->decode_control();
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        } else
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                scope->read();
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        delete  m_fpga;
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}
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