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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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dgisselq |
// Filename: regdefs.cpp
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dgisselq |
//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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dgisselq |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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dgisselq |
//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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dgisselq |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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dgisselq |
// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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#include <stdio.h>
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#include <stdlib.h>
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#include <strings.h>
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#include <ctype.h>
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#include "regdefs.h"
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const REGNAME raw_bregs[] = {
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{ R_VERSION, "VERSION" },
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{ R_ICONTROL, "ICONTROL" },
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{ R_ICONTROL, "INT" },
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{ R_ICONTROL, "PIC" },
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{ R_BUSERR, "BUSERR" },
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{ R_BUSERR, "BUS" },
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{ R_PWCOUNT, "PWRCOUNT" },
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{ R_BTNSW, "BTNSW" },
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{ R_BTNSW, "BTNS" },
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{ R_BTNSW, "BTN" },
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{ R_BTNSW, "SW" },
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{ R_BTNSW, "SWITCHES" },
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{ R_BTNSW, "SWITCH" },
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{ R_LEDS, "LEDS" },
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{ R_LEDS, "LED" },
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{ R_UART_SETUP, "UARTSETUP" },
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{ R_UART_SETUP, "UART" },
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{ R_UART_SETUP, "AUXSETUP" },
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{ R_UART_SETUP, "AUX" },
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{ R_GPS_SETUP, "GPSSETUP" },
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{ R_GPS_FIFO, "GPSFIFO" },
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{ R_GPS_SETUP, "GPSUART" },
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{ R_CLR0, "CLRLED0" },
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{ R_CLR1, "CLRLED1" },
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{ R_CLR2, "CLRLED2" },
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{ R_CLR3, "CLRLED3" },
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{ R_CLR0, "CLR0" },
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{ R_CLR1, "CLR1" },
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{ R_CLR2, "CLR2" },
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{ R_CLR3, "CLR3" },
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{ R_DATE, "DATE" },
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{ R_GPIO, "GPIO" },
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{ R_UARTRX, "AUXRX" },
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{ R_UARTRX, "RX" },
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{ R_UART_FIFO, "AUXFIFO" },
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{ R_UARTTX, "AUXTX" },
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{ R_UARTTX, "TX" },
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//
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{ R_GPSRX, "GPSRX" },
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{ R_GPSTX, "GPSTX" },
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// Scope registers--these scopes may or may not be present depending
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// upon your current configuration.
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{ R_QSCOPE, "SCOPE" }, // Scope zero
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{ R_QSCOPE, "SCOP" },
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{ R_QSCOPED, "SCOPDATA" },
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{ R_QSCOPED, "SCDATA" },
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{ R_QSCOPED, "SCOPED" },
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{ R_QSCOPED, "SCOPD" },
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{ R_CPUSCOPE, "CPUSCOPE" },
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{ R_CPUSCOPED, "CPUSCOPD" },
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{ R_CPUSCOPED, "CPUSCOPED" },
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{ R_GPSCOPE, "GPSSCOPE" }, // Scope one
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{ R_GPSCOPE, "GPSSCOP" },
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{ R_GPSCOPED, "GPSSCDATA" },
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{ R_GPSCOPED, "GPSSCD" },
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{ R_GPSCOPED, "GPSDATA" },
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{ R_CFGSCOPE, "CFGSCOPE" }, // Scope one
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{ R_CFGSCOPE, "CFGSCOP" },
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{ R_CFGSCOPED, "CFGSCDATA" },
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{ R_CFGSCOPED, "CFGSCD" },
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{ R_BUSSCOPE, "BUSSCOPE" }, // Scope one
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{ R_BUSSCOPED, "BUSSCOPD" },
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{ R_RAMSCOPE, "RAMSCOPE" }, // Scope two
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{ R_RAMSCOPE, "RAMSCOP" },
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{ R_RAMSCOPED, "RAMSCOPD" },
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{ R_NETSCOPE, "NETSCOPE" }, // Scope three
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{ R_NETSCOPE, "NETSCOP" },
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{ R_NETSCOPED, "NETSCOPED" },
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{ R_NETSCOPED, "NETSCOPD" },
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// RTC registers
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{ R_CLOCK, "CLOCK" },
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{ R_CLOCK, "TIME" },
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{ R_TIMER, "TIMER" },
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{ R_STOPWATCH, "STOPWACH" },
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{ R_STOPWATCH, "STOPWATCH" },
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{ R_CKALARM, "CKALARM" },
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{ R_CKALARM, "ALARM" },
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// SDCard registers
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{ R_SDCARD_CTRL, "SDCARD" },
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{ R_SDCARD_DATA, "SDDATA" },
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{ R_SDCARD_FIFOA, "SDFIF0" },
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{ R_SDCARD_FIFOA, "SDFIFO" },
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{ R_SDCARD_FIFOA, "SDFIFA" },
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{ R_SDCARD_FIFOA, "SDFIFO0" },
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{ R_SDCARD_FIFOA, "SDFIFOA" },
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{ R_SDCARD_FIFOB, "SDFIF1" },
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{ R_SDCARD_FIFOB, "SDFIFB" },
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{ R_SDCARD_FIFOB, "SDFIFO1" },
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{ R_SDCARD_FIFOB, "SDFIFOB" },
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// GPS control loop control
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{ R_GPS_ALPHA, "ALPHA" },
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{ R_GPS_BETA, "BETA" },
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{ R_GPS_GAMMA, "GAMMA" },
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{ R_GPS_STEP, "GPSSTEP" },
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// Network packet interface (not built yet)
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// OLED Control
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{ R_OLED_CMD, "OLED" },
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{ R_OLED_CDATA, "OLEDCA" },
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{ R_OLED_CDATB, "OLEDCB" },
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{ R_OLED_DATA, "ODATA" },
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// Unused section
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// GPS Testbench
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{ R_GPSTB_FREQ, "GPSFREQ" },
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{ R_GPSTB_JUMP, "GPSJUMP" },
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{ R_GPSTB_ERRHI, "ERRHI" },
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{ R_GPSTB_ERRLO, "ERRLO" },
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{ R_GPSTB_COUNTHI, "CNTHI" },
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{ R_GPSTB_COUNTLO, "CNTLO" },
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{ R_GPSTB_STEPHI, "STEPHI" },
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{ R_GPSTB_STEPLO, "STEPLO" },
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// Ethernet, packet control registers
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{ R_NET_RXCMD, "RXCMD" },
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{ R_NET_RXCMD, "NETRX" },
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{ R_NET_TXCMD, "TXCMD" },
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{ R_NET_TXCMD, "NETTX" },
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{ R_NET_MACHI, "MACHI" },
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{ R_NET_MACLO, "MACLO" },
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{ R_NET_RXMISS, "NETMISS" },
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{ R_NET_RXERR, "NETERR" },
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{ R_NET_RXCRC, "NETXCRC" },
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// Ethernet MDIO registers
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{ R_MDIO_BMCR, "BMCR" },
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{ R_MDIO_BMSR, "BMSR" },
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{ R_MDIO_PHYIDR1, "PHYIDR1" },
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{ R_MDIO_PHYIDR2, "PHYIDR2" },
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{ R_MDIO_ANAR, "ANAR" },
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{ R_MDIO_ANLPAR, "ANLPAR" },
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{ R_MDIO_ANER, "ANER" },
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{ R_MDIO_ANNPTR, "ANNPTR" },
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{ R_MDIO_PHYSTS, "PHYSTS" },
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{ R_MDIO_FCSCR, "FCSCR" },
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{ R_MDIO_RECR, "RECR" },
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{ R_MDIO_PCSR, "PCSR" },
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{ R_MDIO_RBR, "RBR" },
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{ R_MDIO_LEDCR, "LEDCR" },
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{ R_MDIO_PHYCR, "PHYCR" },
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{ R_MDIO_BTSCR, "BTSCR" },
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{ R_MDIO_CDCTRL, "CDCTRL" },
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{ R_MDIO_EDCR, "EDCR" },
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//
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// Flash configuration register names
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{ R_QSPI_EREG, "QSPIEREG" },
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{ R_QSPI_EREG, "QSPIE" },
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{ R_QSPI_STAT, "QSPIS" },
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{ R_QSPI_NVCONF,"QSPINVCF" },
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{ R_QSPI_NVCONF,"QSPINV" },
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{ R_QSPI_VCONF, "QSPIVCNF" },
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{ R_QSPI_VCONF, "QSPIV" },
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{ R_QSPI_EVCONF,"QSPIEVCF" },
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{ R_QSPI_EVCONF,"QSPIEV" },
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{ R_QSPI_LOCK, "QSPILOCK" },
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{ R_QSPI_FLAG, "QSPIFLAG" },
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{ R_QSPI_ID, "QSPIID" },
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{ R_QSPI_IDA, "QSPIIDA" },
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{ R_QSPI_IDB, "QSPIIDB" },
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{ R_QSPI_IDC, "QSPIIDC" },
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{ R_QSPI_IDD, "QSPIIDD" },
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{ R_QSPI_OTPWP, "QSPIOTPWP" },
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{ R_QSPI_OTP, "QSPIOTP" },
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//
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{ R_CFG_CRC, "FPGACRC" },
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{ R_CFG_FAR, "FPGAFAR" },
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{ R_CFG_FDRI, "FPGAFDRI" },
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{ R_CFG_FDRO, "FPGAFDRO" },
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{ R_CFG_CMD, "FPGACMD" },
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{ R_CFG_CTL0, "FPGACTL0" },
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{ R_CFG_MASK, "FPGAMASK" },
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{ R_CFG_STAT, "FPGASTAT" },
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{ R_CFG_LOUT, "FPGALOUT" },
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{ R_CFG_COR0, "FPGACOR0" },
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{ R_CFG_MFWR, "FPGAMFWR" },
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{ R_CFG_CBC, "FPGACBC" },
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{ R_CFG_IDCODE, "FPGAIDCODE" },
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{ R_CFG_AXSS, "FPGAAXSS" },
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{ R_CFG_COR0, "FPGACOR1" },
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{ R_CFG_WBSTAR, "WBSTAR" },
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{ R_CFG_TIMER, "CFGTIMER" },
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{ R_CFG_BOOTSTS,"BOOTSTS" },
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{ R_CFG_CTL1, "FPGACTL1" },
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{ R_CFG_BSPI, "FPGABSPI" },
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//
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{ R_ZIPCTRL, "ZIPCTRL" },
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{ R_ZIPCTRL, "ZIPC" },
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{ R_ZIPCTRL, "CPU" },
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{ R_ZIPCTRL, "CPUC" },
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{ R_ZIPDATA, "ZIPDATA" },
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{ R_ZIPDATA, "ZIPD" },
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{ R_ZIPDATA, "CPUD" },
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| 234 |
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{ EQSPIFLASH, "FLASH" },
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| 235 |
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{ MEMBASE, "BLKRAM" },
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{ MEMBASE, "MEM" },
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| 237 |
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{ RAMBASE, "DDR3SDRAM" },
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| 238 |
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{ RAMBASE, "SDRAM" },
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| 239 |
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{ RAMBASE, "RAM" }
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};
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#define RAW_NREGS (sizeof(raw_bregs)/sizeof(bregs[0]))
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const REGNAME *bregs = raw_bregs;
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| 245 |
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const int NREGS = RAW_NREGS;
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| 246 |
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| 247 |
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unsigned addrdecode(const char *v) {
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| 248 |
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if (isalpha(v[0])) {
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| 249 |
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for(int i=0; i<NREGS; i++)
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if (strcasecmp(v, bregs[i].m_name)==0)
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return bregs[i].m_addr;
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fprintf(stderr, "Unknown register: %s\n", v);
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exit(-2);
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| 254 |
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} else
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return strtoul(v, NULL, 0);
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| 256 |
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}
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| 257 |
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| 258 |
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const char *addrname(const unsigned v) {
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| 259 |
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for(int i=0; i<NREGS; i++)
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| 260 |
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if (bregs[i].m_addr == v)
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return bregs[i].m_name;
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| 262 |
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return NULL;
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| 263 |
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}
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| 264 |
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