| 1 |
4 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//
|
| 3 |
|
|
// Filename: regdefs.h
|
| 4 |
|
|
//
|
| 5 |
|
|
// Project: OpenArty, an entirely open SoC based upon the Arty platform
|
| 6 |
|
|
//
|
| 7 |
|
|
// Purpose:
|
| 8 |
|
|
//
|
| 9 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 10 |
|
|
// Gisselquist Technology, LLC
|
| 11 |
|
|
//
|
| 12 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 13 |
|
|
//
|
| 14 |
|
|
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
| 15 |
|
|
//
|
| 16 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
| 17 |
|
|
// modify it under the terms of the GNU General Public License as published
|
| 18 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
| 19 |
|
|
// your option) any later version.
|
| 20 |
|
|
//
|
| 21 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
| 22 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
| 23 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 24 |
|
|
// for more details.
|
| 25 |
|
|
//
|
| 26 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 27 |
|
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
| 28 |
|
|
// target there if the PDF file isn't present.) If not, see
|
| 29 |
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
| 30 |
|
|
//
|
| 31 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
| 32 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
| 33 |
|
|
//
|
| 34 |
|
|
//
|
| 35 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 36 |
|
|
//
|
| 37 |
|
|
//
|
| 38 |
|
|
//
|
| 39 |
|
|
#include <stdio.h>
|
| 40 |
|
|
#include <stdlib.h>
|
| 41 |
|
|
#include <strings.h>
|
| 42 |
|
|
#include <ctype.h>
|
| 43 |
|
|
#include "regdefs.h"
|
| 44 |
|
|
|
| 45 |
|
|
const REGNAME raw_bregs[] = {
|
| 46 |
|
|
{ R_VERSION, "VERSION" },
|
| 47 |
|
|
{ R_ICONTROL, "ICONTROL" },
|
| 48 |
|
|
{ R_ICONTROL, "INT" },
|
| 49 |
|
|
{ R_ICONTROL, "PIC" },
|
| 50 |
|
|
{ R_BUSERR, "BUSERR" },
|
| 51 |
|
|
{ R_BUSERR, "BUS" },
|
| 52 |
|
|
{ R_PWCOUNT, "PWRCOUNT" },
|
| 53 |
|
|
{ R_BTNSW, "BTNSW" },
|
| 54 |
|
|
{ R_BTNSW, "BTNS" },
|
| 55 |
|
|
{ R_BTNSW, "BTN" },
|
| 56 |
|
|
{ R_BTNSW, "SW" },
|
| 57 |
|
|
{ R_BTNSW, "SWITCHES" },
|
| 58 |
|
|
{ R_BTNSW, "SWITCH" },
|
| 59 |
|
|
{ R_LEDS, "LEDS" },
|
| 60 |
|
|
{ R_LEDS, "LED" },
|
| 61 |
|
|
{ R_UART_SETUP, "UARTSETUP" },
|
| 62 |
|
|
{ R_UART_SETUP, "UART" },
|
| 63 |
|
|
{ R_UART_SETUP, "AUXSETUP" },
|
| 64 |
|
|
{ R_UART_SETUP, "AUX" },
|
| 65 |
|
|
{ R_GPS_SETUP, "GPSSETUP" },
|
| 66 |
|
|
{ R_GPS_SETUP, "GPSUART" },
|
| 67 |
|
|
{ R_CLR0, "CLRLED0" },
|
| 68 |
|
|
{ R_CLR1, "CLRLED1" },
|
| 69 |
|
|
{ R_CLR2, "CLRLED2" },
|
| 70 |
|
|
{ R_CLR3, "CLRLED3" },
|
| 71 |
|
|
{ R_CLR0, "CLR0" },
|
| 72 |
|
|
{ R_CLR1, "CLR1" },
|
| 73 |
|
|
{ R_CLR2, "CLR2" },
|
| 74 |
|
|
{ R_CLR3, "CLR3" },
|
| 75 |
|
|
{ R_DATE, "DATE" },
|
| 76 |
|
|
{ R_GPIO, "GPIO" },
|
| 77 |
|
|
{ R_UARTRX, "AUXRX" },
|
| 78 |
|
|
{ R_UARTRX, "RX" },
|
| 79 |
|
|
{ R_UARTTX, "AUXTX" },
|
| 80 |
|
|
{ R_UARTTX, "TX" },
|
| 81 |
|
|
//
|
| 82 |
|
|
{ R_GPSRX, "GPSRX" },
|
| 83 |
|
|
{ R_GPSTX, "GPSTX" },
|
| 84 |
|
|
// Scope registers--these scopes may or may not be present depending
|
| 85 |
|
|
// upon your current configuration.
|
| 86 |
6 |
dgisselq |
{ R_QSCOPE, "SCOPE" }, // Scope zero
|
| 87 |
4 |
dgisselq |
{ R_QSCOPE, "SCOP" },
|
| 88 |
|
|
{ R_QSCOPED, "SCOPDATA" },
|
| 89 |
|
|
{ R_QSCOPED, "SCDATA" },
|
| 90 |
|
|
{ R_QSCOPED, "SCOPED" },
|
| 91 |
|
|
{ R_QSCOPED, "SCOPD" },
|
| 92 |
6 |
dgisselq |
{ R_GPSCOPE, "GPSSCOPE" }, // Scope one
|
| 93 |
4 |
dgisselq |
{ R_GPSCOPE, "GPSSCOP" },
|
| 94 |
|
|
{ R_GPSCOPED, "GPSSCDATA" },
|
| 95 |
|
|
{ R_GPSCOPED, "GPSSCD" },
|
| 96 |
|
|
{ R_GPSCOPED, "GPSDATA" },
|
| 97 |
14 |
dgisselq |
{ R_CFGSCOPE, "CFGSCOPE" }, // Scope one
|
| 98 |
|
|
{ R_CFGSCOPE, "CFGSCOP" },
|
| 99 |
|
|
{ R_CFGSCOPED, "CFGSCDATA" },
|
| 100 |
|
|
{ R_CFGSCOPED, "CFGSCD" },
|
| 101 |
6 |
dgisselq |
{ R_RAMSCOPE, "RAMSCOPE" }, // Scope two
|
| 102 |
4 |
dgisselq |
{ R_RAMSCOPE, "RAMSCOP" },
|
| 103 |
|
|
{ R_RAMSCOPED, "RAMSCOPD" },
|
| 104 |
6 |
dgisselq |
{ R_NETSCOPE, "NETSCOPE" }, // Scope three
|
| 105 |
|
|
{ R_NETSCOPE, "NETSCOP" },
|
| 106 |
|
|
{ R_NETSCOPED, "NETSCOPED" },
|
| 107 |
|
|
{ R_NETSCOPED, "NETSCOPD" },
|
| 108 |
4 |
dgisselq |
// RTC registers
|
| 109 |
|
|
{ R_CLOCK, "CLOCK" },
|
| 110 |
|
|
{ R_CLOCK, "TIME" },
|
| 111 |
|
|
{ R_TIMER, "TIMER" },
|
| 112 |
|
|
{ R_STOPWATCH, "STOPWACH" },
|
| 113 |
|
|
{ R_STOPWATCH, "STOPWATCH" },
|
| 114 |
|
|
{ R_CKALARM, "CKALARM" },
|
| 115 |
|
|
{ R_CKALARM, "ALARM" },
|
| 116 |
|
|
// SDCard registers
|
| 117 |
|
|
{ R_SDCARD_CTRL, "SDCARD" },
|
| 118 |
|
|
{ R_SDCARD_DATA, "SDDATA" },
|
| 119 |
|
|
{ R_SDCARD_FIFOA, "SDFIF0" },
|
| 120 |
|
|
{ R_SDCARD_FIFOA, "SDFIFO" },
|
| 121 |
|
|
{ R_SDCARD_FIFOA, "SDFIFA" },
|
| 122 |
|
|
{ R_SDCARD_FIFOA, "SDFIFO0" },
|
| 123 |
|
|
{ R_SDCARD_FIFOA, "SDFIFOA" },
|
| 124 |
|
|
{ R_SDCARD_FIFOB, "SDFIF1" },
|
| 125 |
|
|
{ R_SDCARD_FIFOB, "SDFIFB" },
|
| 126 |
|
|
{ R_SDCARD_FIFOB, "SDFIFO1" },
|
| 127 |
|
|
{ R_SDCARD_FIFOB, "SDFIFOB" },
|
| 128 |
|
|
// GPS control loop control
|
| 129 |
|
|
{ R_GPS_ALPHA, "ALPHA" },
|
| 130 |
|
|
{ R_GPS_BETA, "BETA" },
|
| 131 |
|
|
{ R_GPS_GAMMA, "GAMMA" },
|
| 132 |
|
|
{ R_GPS_STEP, "GPSSTEP" },
|
| 133 |
|
|
// Network packet interface (not built yet)
|
| 134 |
|
|
// OLED Control
|
| 135 |
|
|
{ R_OLED_CMD, "OLED" },
|
| 136 |
|
|
{ R_OLED_CDATA, "OLEDCA" },
|
| 137 |
|
|
{ R_OLED_CDATB, "OLEDCB" },
|
| 138 |
|
|
{ R_OLED_DATA, "ODATA" },
|
| 139 |
|
|
// Unused section
|
| 140 |
|
|
// GPS Testbench
|
| 141 |
|
|
{ R_GPSTB_FREQ, "GPSFREQ" },
|
| 142 |
|
|
{ R_GPSTB_JUMP, "GPSJUMP" },
|
| 143 |
|
|
{ R_GPSTB_ERRHI, "ERRHI" },
|
| 144 |
|
|
{ R_GPSTB_ERRLO, "ERRLO" },
|
| 145 |
|
|
{ R_GPSTB_COUNTHI, "CNTHI" },
|
| 146 |
|
|
{ R_GPSTB_COUNTLO, "CNTLO" },
|
| 147 |
|
|
{ R_GPSTB_STEPHI, "STEPHI" },
|
| 148 |
|
|
{ R_GPSTB_STEPLO, "STEPLO" },
|
| 149 |
|
|
//
|
| 150 |
|
|
// Ethernet MDIO registers
|
| 151 |
|
|
{ R_MDIO_BMCR, "BMCR" },
|
| 152 |
|
|
{ R_MDIO_BMSR, "BMSR" },
|
| 153 |
|
|
{ R_MDIO_PHYIDR1, "PHYIDR1" },
|
| 154 |
|
|
{ R_MDIO_PHYIDR2, "PHYIDR2" },
|
| 155 |
|
|
{ R_MDIO_ANAR, "ANAR" },
|
| 156 |
|
|
{ R_MDIO_ANLPAR, "ANLPAR" },
|
| 157 |
|
|
{ R_MDIO_ANER, "ANER" },
|
| 158 |
|
|
{ R_MDIO_ANNPTR, "ANNPTR" },
|
| 159 |
|
|
{ R_MDIO_PHYSTS, "PHYSTS" },
|
| 160 |
|
|
{ R_MDIO_FCSCR, "FCSCR" },
|
| 161 |
|
|
{ R_MDIO_RECR, "RECR" },
|
| 162 |
|
|
{ R_MDIO_PCSR, "PCSR" },
|
| 163 |
|
|
{ R_MDIO_RBR, "RBR" },
|
| 164 |
|
|
{ R_MDIO_LEDCR, "LEDCR" },
|
| 165 |
|
|
{ R_MDIO_PHYCR, "PHYCR" },
|
| 166 |
|
|
{ R_MDIO_BTSCR, "BTSCR" },
|
| 167 |
|
|
{ R_MDIO_CDCTRL, "CDCTRL" },
|
| 168 |
|
|
{ R_MDIO_EDCR, "EDCR" },
|
| 169 |
|
|
//
|
| 170 |
|
|
// Flash configuration register names
|
| 171 |
|
|
{ R_QSPI_EREG, "QSPIEREG" },
|
| 172 |
|
|
{ R_QSPI_EREG, "QSPIE" },
|
| 173 |
|
|
{ R_QSPI_STAT, "QSPIS" },
|
| 174 |
|
|
{ R_QSPI_NVCONF,"QSPINVCONF" },
|
| 175 |
|
|
{ R_QSPI_NVCONF,"QSPINV" },
|
| 176 |
|
|
{ R_QSPI_VCONF, "QSPIVCONF" },
|
| 177 |
|
|
{ R_QSPI_VCONF, "QSPIV" },
|
| 178 |
|
|
{ R_QSPI_EVCONF,"QSPIEVCONF" },
|
| 179 |
|
|
{ R_QSPI_EVCONF,"QSPIEV" },
|
| 180 |
|
|
{ R_QSPI_LOCK, "QSPILOCK" },
|
| 181 |
|
|
{ R_QSPI_FLAG, "QSPIFLAG" },
|
| 182 |
|
|
{ R_QSPI_ID, "QSPIID" },
|
| 183 |
|
|
{ R_QSPI_IDA, "QSPIIDA" },
|
| 184 |
|
|
{ R_QSPI_IDB, "QSPIIDB" },
|
| 185 |
|
|
{ R_QSPI_IDC, "QSPIIDC" },
|
| 186 |
|
|
{ R_QSPI_IDD, "QSPIIDD" },
|
| 187 |
|
|
{ R_QSPI_OTPWP, "QSPIOTPWP" },
|
| 188 |
|
|
{ R_QSPI_OTP, "QSPIOTP" },
|
| 189 |
|
|
//
|
| 190 |
|
|
{ R_CFG_CRC, "FPGACRC" },
|
| 191 |
|
|
{ R_CFG_FAR, "FPGAFAR" },
|
| 192 |
|
|
{ R_CFG_FDRI, "FPGAFDRI" },
|
| 193 |
|
|
{ R_CFG_FDRO, "FPGAFDRO" },
|
| 194 |
|
|
{ R_CFG_CMD, "FPGACMD" },
|
| 195 |
|
|
{ R_CFG_CTL0, "FPGACTL0" },
|
| 196 |
|
|
{ R_CFG_MASK, "FPGAMASK" },
|
| 197 |
|
|
{ R_CFG_STAT, "FPGASTAT" },
|
| 198 |
|
|
{ R_CFG_LOUT, "FPGALOUT" },
|
| 199 |
|
|
{ R_CFG_COR0, "FPGACOR0" },
|
| 200 |
|
|
{ R_CFG_MFWR, "FPGAMFWR" },
|
| 201 |
|
|
{ R_CFG_CBC, "FPGACBC" },
|
| 202 |
|
|
{ R_CFG_IDCODE, "FPGAIDCODE" },
|
| 203 |
|
|
{ R_CFG_AXSS, "FPGAAXSS" },
|
| 204 |
|
|
{ R_CFG_COR0, "FPGACOR1" },
|
| 205 |
|
|
{ R_CFG_WBSTAR, "WBSTAR" },
|
| 206 |
|
|
{ R_CFG_TIMER, "CFGTIMER" },
|
| 207 |
|
|
{ R_CFG_BOOTSTS,"BOOTSTS" },
|
| 208 |
|
|
{ R_CFG_CTL1, "FPGACTL1" },
|
| 209 |
|
|
{ R_CFG_BSPI, "FPGABSPI" },
|
| 210 |
|
|
//
|
| 211 |
|
|
{ R_ZIPCTRL, "ZIPCTRL" },
|
| 212 |
|
|
{ R_ZIPCTRL, "ZIPC" },
|
| 213 |
|
|
{ R_ZIPCTRL, "CPU" },
|
| 214 |
|
|
{ R_ZIPCTRL, "CPUC" },
|
| 215 |
|
|
{ R_ZIPDATA, "ZIPDATA" },
|
| 216 |
|
|
{ R_ZIPDATA, "ZIPD" },
|
| 217 |
|
|
{ R_ZIPDATA, "CPUD" },
|
| 218 |
|
|
{ EQSPIFLASH, "FLASH" },
|
| 219 |
|
|
{ MEMBASE, "BLKRAM" },
|
| 220 |
|
|
{ MEMBASE, "MEM" },
|
| 221 |
|
|
{ RAMBASE, "DDR3SDRAM" },
|
| 222 |
|
|
{ RAMBASE, "SDRAM" },
|
| 223 |
|
|
{ RAMBASE, "RAM" }
|
| 224 |
|
|
};
|
| 225 |
|
|
|
| 226 |
|
|
#define RAW_NREGS (sizeof(raw_bregs)/sizeof(bregs[0]))
|
| 227 |
|
|
|
| 228 |
|
|
const REGNAME *bregs = raw_bregs;
|
| 229 |
|
|
const int NREGS = RAW_NREGS;
|
| 230 |
|
|
|
| 231 |
|
|
unsigned addrdecode(const char *v) {
|
| 232 |
|
|
if (isalpha(v[0])) {
|
| 233 |
|
|
for(int i=0; i<NREGS; i++)
|
| 234 |
|
|
if (strcasecmp(v, bregs[i].m_name)==0)
|
| 235 |
|
|
return bregs[i].m_addr;
|
| 236 |
|
|
fprintf(stderr, "Unknown register: %s\n", v);
|
| 237 |
|
|
exit(-2);
|
| 238 |
|
|
} else
|
| 239 |
|
|
return strtoul(v, NULL, 0);
|
| 240 |
|
|
}
|
| 241 |
|
|
|
| 242 |
|
|
const char *addrname(const unsigned v) {
|
| 243 |
|
|
for(int i=0; i<NREGS; i++)
|
| 244 |
|
|
if (bregs[i].m_addr == v)
|
| 245 |
|
|
return bregs[i].m_name;
|
| 246 |
|
|
return NULL;
|
| 247 |
|
|
}
|
| 248 |
|
|
|
