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///////////////////////////////////////////////////////////////////////////////////////////////////

//                                                                                               //

//  file name:   memstate2.v                                                                       //

//  description: memory opertions for  z80                                                       //

//  project:     wb_z80                                                                          //

//                                                                                               //

//  Author: B.J. Porcella                                                                        //

//  e-mail: bporcella@sbcglobal.net                                                              //

//                                                                                               //

//                                                                                               //

//                                                                                               //

///////////////////////////////////////////////////////////////////////////////////////////////////

//                                                                                               //

// Copyright (C) 2000-2002 B.J. Porcella                                                         //

//                         Real Time Solutions                                                   //

//                                                                                               //

//                                                                                               //

// This source file may be used and distributed without                                          //

// restriction provided that this copyright statement is not                                     //

// removed from the file and that any derivative work contains                                   //

// the original copyright notice and the associated disclaimer.                                  //

//                                                                                               //

//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY                                       //

// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED                                     //

// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS                                     //

// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR                                        //

// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,                                           //

// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES                                      //

// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE                                     //

// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR                                          //

// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF                                    //

// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT                                    //

// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT                                    //

// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE                                           //

// POSSIBILITY OF SUCH DAMAGE.                                                                   //

//                                                                                               //

//-------1---------2---------3--------Comments on file  -------------7---------8---------9--------0

// The memory state controller controls the wb bus, and provides address sequencing.

// Insructions are fetched in order (using PC) until the istate machine indicates that 

// a complete instruction is in the first pipline stage (ir1). In general, operands are being

// fetched (stored) to satisfy ir1 while concurrently instructions are being executed from ir2.

// this situation can result in a number of potential hazards.   As an example, if the ir2

// instruction changes the flag register and the ir1 instruction is a conditional jump, 

// a hazard is generated by the hazard logic, and execution of the ir1 operation is delayed 

// until the completion of the flag update.

//

// Reset starts execution at 0.  

// The PC and SP are described in this file.   modifications to other index registers - 

// HL IX and IY are computed here -- 

// For the block moves address updates are computed here   -- and commanded here.

// Strobes for the second address update are generally co-incident with count updates, but

// we provide seperate strobe update lines for clarity.

//

//  BASIC ARCHITECTURE OF THIS FILE   pc  and sp not shown, but are inputs to src mux.

//                    _____           and may be updated from adder output.

//                   |     |

//                   |     |          pc-1 register is required to implement relative jumps.

//                   |     |                     

//      _____        |lit  |      |\             

//     |     |       |     |      |  \           

//     |     |       |src2 |      |    \          _____          _____ 

//     |     |       |     |----->|     |        |     |        |     |

//     |src  |       |_____|      |adder|------->|     |        |     |

//     |mux  |                    |     |        |     |        |     |

//     |     |------------------->|    /         |2/1  |------->|wb   |

//     |     |              |     |  /           |mux  |        |adr  |

//     |_____|              |     |/             |     |        |     |

//                           ------------------->|     |        |     |

//                                               |_____|        |_____|

//

//

//

//

//  Operand Stores:

//  At first cut, I thought I'ld execute operand stores immediately from the memory sequencer

//  (essentially before ir2 got the store data).  While this might be modestly faster in 

//  systems that take multiple clocks to complete a memory store, On consideration, I decided 

//  to forgo the extra speed for conceptual simplicity....   execute operand stores on op_ph1,

//  and let the inst_exec engine suply the operand.

//

//  On second thought, above is not only wastful of time, but also inconsistent with the overall

//  schems of things - and so somewhat more complex. If we simply execute the OS from ir1, 

//  There is less state to contdend with, as well as extra speed.

//

//  Block Moves fundamentally execute from ir2.  We initiate the first operand fetch from ir1.

//

//  3/18/2004 Second time through.   In impleenting the execution logic it became clear that

//  there were "minor" problems with the handling of the DD and FD prefix insts (especially

//  DDCD and FDCB  ---  collectively called PFxCB below.  On review, I had to question the

//  value of "breaking up" the ir0 execution engine between the istate sequencer and the 

//  memstate sequencer.   While I dislike state sequencers of much more than 16 states  --  

//  the interaction between these sequencers was becomming harder to track than a single

//  state macine.   Thus - this file is getting re-worked.   I will call it memstate2 (at least

//  for awhile) as I wish to keep the old file around.  I want to show (in the state machine

//  logic) what the next memory operation is....   guess the best method consistent with my

//  documentation practices is to define a register (mem_op)  = { if, wb_we, wb_cyc }.  

//  This will require auxillary logic for computing the address ---  but most of the decodes

//  required will be there anyway.   

//  On further reflection, I think I will bite-the-bullet and use an always to define next_state.

//  I don't like to use always to define wires, but I also want to dicument the setting of 

//  exec_ir2 in the same place - that is 3 different things.  

//  

//  Hazards:

//  There are 2 kinds of hazards:  mem_hazard => we are storing into the next instruction location

//                                 reg_hazard => we are modifying a register (ir2) that we are using

//                                                here (ir1)

//  In the former case, we throw out the instruction that arrives on the next tick, and restart the

//  instruction pipeline,   In the latter case, we simply wait a tick for the ir2 operaton to 

//  complete before starting the ir1 operation  

//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0

//

//  $Id: memstate2.v,v 1.1.1.1 2004-06-18 08:38:46 mihal Exp $

//

//  $Date: 2004-06-18 08:38:46 $

//  $Revision: 1.1.1.1 $

//  $Author: mihal $

//  $Locker:  $

//  $State: Exp $

//

// Change History:

//      $Log: not supported by cvs2svn $

//      Revision 1.4  2004/04/16 18:16:57  bporcella

//      try lint

//

//      Revision 1.3  2004/04/16 17:06:54  bporcella

//      no code change  -  added a comment and test lint

//

//      Revision 1.2  2004/04/16 16:21:04  bporcella

//      no code change  -  added a comment and test lint

//

//      Revision 1.1.1.1  2004/04/13 23:50:19  bporcella

//      import first files

//

//

//

//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0

module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o,  add_out,

                exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,

                upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,

                beq0, ceq0,

                ar, fr, br, cr, dr, er, hr, lr,

                ixr, iyr,

                wb_dat_i, wb_ack, clk, rst,

                wb_int_rq,

                add16

);

//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0

// mod only to checkout lint

// mod again for lint check  --   first check pretty wierd

// 3rd lint try

output [15:0]  wb_adr;

output         wb_we;

output         wb_cyc;

output         wb_stb;

output         wb_lock;     // bit set and clear insts should be atomic - could matter sometime

output         wb_tga_io;

output         wb_dat_o;   // from nn

output [15:0]  add_out;     // output of adder  (may not wb_adr)

output         exec_ir2;

output [9:0]   ir1, ir2;

output         ir1dd, ir2dd;

output          ir1fd, ir2fd;

output [15:0]   nn;

output [15:0]   sp;

//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0

input           upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr;

input           beq0, ceq0;

input [7:0]     ar, fr, br, cr, dr, er, hr, lr;

input [15:0]    ixr, iyr;

input [7:0]     wb_dat_i;

input           wb_ack, clk, rst;

input           wb_int_rq;

input [15:0]    add16;         //  ir2 execution engine output for sp updates

//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0

`include "opcodes.v"            //  states of the main memory sequencer

parameter   TAG_IO    = 2'b01,   // need to review general wb usage to undrstand how best to 

            TAG_INT   = 2'b10;   // document this.

            //                  12na

parameter   IPIPE_NOP       = 4'b0000,

            IPIPE_A2        = 4'b0001,

            IPIPE_ENN       = 4'b0010,

            IPIPE_ENNA2     = 4'b0011,

            IPIPE_EN2       = 4'b0100,

            IPIPE_EN2A2     = 4'b0101,

            IPIPE_ENNEN2    = 4'b0110,

            IPIPE_ENNEN2A2  = 4'b0111,

            IPIPE_EN1       = 4'b1000,

            IPIPE_EN1A2     = 4'b1001,

            IPIPE_BOGUS     = 4'b1010,  // no reason (yet) to load both n and ir1

            IPIPE_BOUS2     = 4'b1011,

            IPIPE_EN12      = 4'b1100,

            IPIPE_EN12A2    = 4'b1101,

            IPIPE_BOGUS3    = 4'b1110,

            IPIPE_BOGUS4    = 4'b1111;

//  well at first cut I tried to make this 2 state macines both less than 16 states.

//  this is 56 states at first cut.   Assignemnt is subject to change.

// ------  mem state decoder state machine states --------------------------------

parameter       DEC_IDLE      = 6'h00,

                DEC_HALT      = 6'h01,

                DEC_IF1       = 6'h02,

                DEC_IF2       = 6'h03,

                DEC_IF2A      = 6'h04,

                DEC_EXEC      = 6'h05,

                DEC_CB        = 6'h06,

                DEC_DDFD      = 6'h07,

                DEC_ED        = 6'h08,

                DEC_EDNN1     = 6'h09,

                DEC_EDNN2     = 6'h0a,

                DEC_EDRD1     = 6'h0b,

                DEC_EDRD2     = 6'h0c,

                DEC_EDWR      = 6'h0d,

                DEC_EDBCP1    = 6'h0e,

                DEC_EDBCP2    = 6'h0f,

                DEC_EDBCP3    = 6'h10,

                DEC_EDBIN1    = 6'h11,

                DEC_EDBIN2    = 6'h12,

                DEC_EDBIN3    = 6'h13,

                DEC_EDBOUT1   = 6'h14,

                DEC_EDBOUT2   = 6'h15,

                DEC_EDBOUT3   = 6'h16,

                DEC_EDBMV1    = 6'h17,

                DEC_EDBMV2    = 6'h18,

                DEC_EDBMV3    = 6'h19,

                DEC_N         = 6'h1a,

                DEC_NIN       = 6'h1b,

                DEC_NN        = 6'h1c,

                DEC_NNCALL1   = 6'h1d,

                DEC_NNCALL2   = 6'h1e,

                DEC_NNOS1     = 6'h1f,

                DEC_NNOS2     = 6'h20,

                DEC_NNOS3     = 6'h21,

                DEC_NNOF1     = 6'h22,

                DEC_NNOF2     = 6'h23,

                DEC_NNOF3     = 6'h24,

                DEC_NNOF4     = 6'h25,

                DEC_DDOS      = 6'h26,

                DEC_DDOF      = 6'h27,

                DEC_OF        = 6'h28,

                DEC_POP       = 6'h29,

                DEC_PUSH      = 6'h2a,

                DEC_RMW       = 6'h2b,

                DEC_RMW2      = 6'h2c,

                DEC_CBM       = 6'h2d,

                DEC_PFxCB     = 6'h2e,

                DEC_PFxCB2    = 6'h2f,

                DEC_PFxCB3    = 6'h30,

                DEC_PFxCB4    = 6'h31,

                DEC_INT1      = 6'h32,

                DEC_INT2      = 6'h33,

                DEC_INT3      = 6'h34,

                DEC_INT4      = 6'h35,

                DEC_INT5      = 6'h36,

                DEC_RET       = 6'h37,

                DEC_NNJMP     = 6'h38,

                DEC_RET2      = 6'h39 ;

//  initial decode assignemnts.   These assignemens are made to wires on an initial decode

//  to help document next state transitions

parameter      I1_CB    = 4'h0,

               I1_DDFD  = 4'h1,

               I1_ED    = 4'h2,

               I1_JMP   = 4'h3,

               I1_N     = 4'h4,

               I1_NN    = 4'h5,

               I1_OF    = 4'h6,

               I1_OS    = 4'h7,

               I1_POP   = 4'h8,

               I1_PUSH  = 4'h9,

               I1_RET   = 4'ha,

               I1_RMW   = 4'hb,

               I1_RST   = 4'hc,

               I1_R2R   = 4'hd ;

// A note here on the choices of mnemonics.....   in general, the target registers of 

// memory ops are specified by an instruction register  (ir1 for stores ir2 for loads).

// so Menomics in general are specifying the address source.   However, there are exceptions.

//

parameter       MEM_NOP      = 5'h00,

                MEM_IFPP1    = 5'h01,

                MEM_OS1      = 5'h02,      //  only invoked on I1 OS  multiple address sources and data sources

                MEM_OF1      = 5'h03,     //  Address from HL  unless   LD A,(BC) or LD A,(DE)  (used for rmw)

                MEM_OFSP     = 5'h04,     //  works for both POP and RET 

                MEM_OSSP     = 5'h05,     //  if DEC_EXEC  op from ir1  else msb nn  (implies we store from lsb nn)

                                          //  used in CALL also.  

                MEM_OFIXpD   = 5'h06,     //  used for prefix op fetches  - all single bytes

                MEM_OSIXpD   = 5'h07,     //  data source is same as MEM_OS1

                MEM_OSADR    = 5'h08,     //  used (at lesat)  for prefixed rmw --  perhaps others.

                MEM_CALL     = 5'h09,     // pc<=nn, nn<=pc, wb_adr<=sp   OS 

                MEM_OSNN     = 5'h0a,     //  if DEC_EXEC  op from ir1  else msb nn

                MEM_OFNN     = 5'h0b,     // striaghtfoward

                MEM_OFADRP1  = 5'h0c,     // used (at least) when double ops above

                MEM_OSADRP1  = 5'h0d,     //  ""              ""              ""

                MEM_IFRST    = 5'h0e,     // special address transfer

                MEM_IFREL_N  = 5'h0f,     // special address transfer for jmp rel

                MEM_JMPHL    = 5'h10,     // another special jump transfer

                MEM_IFNN     = 5'h11,        //  used by call and return

                MEM_OFHL_PM  = 5'h12,             // special block move ops  

                MEM_OSHL_PM  = 5'h13,             // special block move ops

                MEM_OSDE_PM  = 5'h14,             // special block move ops

                MEM_IOF_C    = 5'h15,             // special i/o ops

                MEM_IOS_C    = 5'h16,             // operand is ar

                MEM_IOF_N    = 5'h17,

                MEM_IOS_N    = 5'h18,

                MEM_OS_HL_N  = 5'h19,

                MEM_OSSP_PCM2 = 5'h1a,              // int code  (call 

                MEM_OSSP_P   = 5'h1b,              //

                MEM_INTA     = 5'h1c,

                MEM_IFINT    = 5'h1d,

                MEM_DECPC    = 5'h1e ;

//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0

wire        use_sp;

wire        use_pc;

wire        use_hl;

wire        use_de;

wire        use_bc;

wire        use_flags;

wire        cb_mem;

wire        br_test8t;  // branch test true  (8 test field)

wire        br_test4t;  // branch test true  (4 test field)

wire        ofos;

wire        any_os;   // most terms above only valid on mem_exec  this includes all stores

wire        wb_rdy_nhz;

wire        dec_blk_inc;

wire        we_next;

wire        hazard;

wire        wb_int;

wire [15:0] hl, de, bc;

wire        mem_exec_dec;

wire  use_a  ;

wire  use_b  ;

wire  use_c  ;

wire  use_d  ;

wire  use_e  ;

wire  use_h  ;

wire  use_l  ;

// don't forget that as 1r1 is executed it is transferred to ir2.  Anything I need to know

// about subsequent operations must be stored.

//               6              5              4                15

// assign {next_dec_state, next_mem_state, next_pipe_state} = next_state;

wire  [5:0]        next_dec_state;

wire  [4:0]        next_mem_state;

wire  [3:0]        next_pipe_state;

wire               ed_dbl_rd;

//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0

reg [15:0]   pc;

reg [15:0]   sp;

reg [15:0]   wb_adr;

reg          wb_we;

reg          wb_cyc;

reg          wb_stb;

reg          wb_lock;

reg          wb_tga_io;

reg          blk_inc_flg;

reg [9:0]    ir1, ir2;

reg          ir1dd, ir2dd;

reg          ir1fd, ir2fd;

reg [15:0]   nn;

reg   [15:0]       next_state;      // a wire assigned in an alowys loop.

reg   [5:0]  dec_state;    // the register set each clock from next_dec_state;

reg          of16_reg,  os16_reg, rmw8_reg, call_reg, ret_reg, ioi;

reg          push_reg;

reg          pop_reg;

reg          inst_haz;

reg          exec_ir2;

reg          blk_rpt_flg;

reg          blk_io_flg;

reg          flag_os1;

reg          int_en, en_int_next;

reg          wb_irq_sync;

//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0

//

// ir is 10 bits most significant codes ir1[9:8] = { EDgrp, CBgrp }  DDgrp and FDgrp are modifiers

assign wb_dat_o = nn[15:8];

wire   sf, zf, f5f, hf, f3f, pvf, nf, cf;

assign { sf, zf, f5f, hf, f3f, pvf, nf, cf} = fr;

assign hl = {hr, lr};

assign de = {dr, er};

assign bc = {br, cr};

//  this "groups" the instructions to determine first memory operation

parameter  I1DCNT = 4;  // parameter used below simply to make possible change easier.

assign mem_exec_dec =

    {I1DCNT {CBgrp        == ir1}} & I1_CB  |//       CBgrp is rotates and bi

    {I1DCNT {DDgrp        == ir1}} & I1_DDFD|//      DDgrp   

    {I1DCNT {FDgrp        == ir1}} & I1_DDFD|//      FDgrp          FD

    {I1DCNT {EDgrp        == ir1}} & I1_ED  |//      EDgrp          ED

    {I1DCNT {JPsHL        == ir1}} & I1_JMP |//      JP HL        ; E9 // doc

    {I1DCNT {ADCsA_N      == ir1}} & I1_N   |//      ADC A,N      ; CE XX

    {I1DCNT {ADDsA_N      == ir1}} & I1_N   |//      ADD A,N      ; C6 XX

    {I1DCNT {ANDsN        == ir1}} & I1_N   |//      AND N        ; E6 XX

    {I1DCNT {CPsN         == ir1}} & I1_N   |//      CP N         ; FE XX

    {I1DCNT {INsA_6N7     == ir1}} & I1_N   |//      IN A,(N)     ; DB XX

    {I1DCNT {JRs$t2       == ir1}} & I1_N   |//      JR $+2       ; 18 XX

    {I1DCNT {JRsC_$t2     == ir1}} & I1_N   |//      JR C,$+2     ; 38 XX

    {I1DCNT {JRsNC_$t2    == ir1}} & I1_N   |//      JR NC,$+2    ; 30 XX

    {I1DCNT {JRsZ_$t2     == ir1}} & I1_N   |//      JR Z,$+2     ; 28 XX

    {I1DCNT {JRsNZ_$t2    == ir1}} & I1_N   |//      JR NZ,$+2    ; 20 XX

    {I1DCNT {LDs6HL7_N    == ir1}} & I1_N   |//      LD (HL),N    ; 36 XX

    {I1DCNT {LDsA_N       == ir1}} & I1_N   |//      LD A,N       ; 3E XX

    {I1DCNT {LDsB_N       == ir1}} & I1_N   |//      LD B,N       ; 06 XX

    {I1DCNT {LDsC_N       == ir1}} & I1_N   |//      LD C,N       ; 0E XX

    {I1DCNT {LDsD_N       == ir1}} & I1_N   |//      LD D,N       ; 16 XX

    {I1DCNT {LDsE_N       == ir1}} & I1_N   |//      LD E,N       ; 1E XX

    {I1DCNT {LDsH_N       == ir1}} & I1_N   |//      LD H,N       ; 26 XX

    {I1DCNT {LDsL_N       == ir1}} & I1_N   |//      LD L,N       ; 2E XX

    {I1DCNT {ORsN         == ir1}} & I1_N   |//      OR N         ; F6 XX

    {I1DCNT {OUTs6N7_A    == ir1}} & I1_N   |//      OUT (N),A    ; D3 XX

    {I1DCNT {SBCsA_N      == ir1}} & I1_N   |//      SBC A,N      ; DE XX

    {I1DCNT {SUBsN        == ir1}} & I1_N   |//      SUB N        ; D6 XX

    {I1DCNT {XORsN        == ir1}} & I1_N   |//      XOR N        ; EE XX

    {I1DCNT {CALLsC_NN    == ir1}} & I1_NN  |//      CALL C,NN    ; DC XX XX

    {I1DCNT {CALLsNC_NN   == ir1}} & I1_NN  |//      CALL NC,NN   ; D4 XX XX

    {I1DCNT {CALLsNN      == ir1}} & I1_NN  |//      CALL NN      ; CD XX XX

    {I1DCNT {CALLsNZ_NN   == ir1}} & I1_NN  |//      CALL NZ,NN   ; C4 XX XX

    {I1DCNT {CALLsPE_NN   == ir1}} & I1_NN  |//      CALL PE,NN   ; EC XX XX

    {I1DCNT {CALLsPO_NN   == ir1}} & I1_NN  |//      CALL PO,NN   ; E4 XX XX

    {I1DCNT {CALLsP_NN    == ir1}} & I1_NN  |//      CALL P,NN    ; F4 XX XX

    {I1DCNT {CALLsZ_NN    == ir1}} & I1_NN  |//      CALL Z,NN    ; CC XX XX

    {I1DCNT {CALLsM_NN    == ir1}} & I1_NN  |//      CALL M,NN    ; FC XX XX

    {I1DCNT {JP           == ir1}} & I1_NN  |//      JP           ; C3 XX XX

    {I1DCNT {JPsC         == ir1}} & I1_NN  |//      JP C         ; DA XX XX

    {I1DCNT {JPsM         == ir1}} & I1_NN  |//      JP M,        ; FA XX XX

    {I1DCNT {JPsNC        == ir1}} & I1_NN  |//      JP NC,       ; D2 XX XX

    {I1DCNT {JPsNZ        == ir1}} & I1_NN  |//      JP NZ        ; C2 XX XX

    {I1DCNT {JPsP         == ir1}} & I1_NN  |//      JP P         ; F2 XX XX

    {I1DCNT {JPsPE        == ir1}} & I1_NN  |//      JP PE,       ; EA XX XX

    {I1DCNT {JPsPO        == ir1}} & I1_NN  |//      JP PO        ; E2 XX XX

    {I1DCNT {JPsZ         == ir1}} & I1_NN  |//      JP Z         ; CA XX XX

    {I1DCNT {LDs6NN7_A    == ir1}} & I1_NN  |//      LD (NN),A    ; 32 XX XX

    {I1DCNT {LDs6NN7_HL   == ir1}} & I1_NN  |//      LD (NN),HL   ; 22 XX XX

    {I1DCNT {LDsA_6NN7    == ir1}} & I1_NN  |//      LD A,(NN)    ; 3A XX XX

    {I1DCNT {LDsBC_NN     == ir1}} & I1_NN  |//      LD BC,NN     ; 01 XX XX

    {I1DCNT {LDsDE_NN     == ir1}} & I1_NN  |//      LD DE,NN     ; 11 XX XX

    {I1DCNT {LDsHL_6NN7   == ir1}} & I1_NN  |//      LD HL,(NN)   ; 2A XX XX

    {I1DCNT {LDsHL_NN     == ir1}} & I1_NN  |//      LD HL,NN     ; 21 XX XX

    {I1DCNT {LDsSP_NN     == ir1}} & I1_NN  |//      LD SP,NN     ; 31 XX XX

    {I1DCNT {ADCsA_6HL7   == ir1}} & I1_OF  |//      ADC A,(HL)   ; 8E

    {I1DCNT {ADDsA_6HL7   == ir1}} & I1_OF  |//      ADD A,(HL)   ; 86

    {I1DCNT {ANDs6HL7     == ir1}} & I1_OF  |//      AND (HL)     ; A6

    {I1DCNT {CPs6HL7      == ir1}} & I1_OF  |//      CP (HL)      ; BE

    {I1DCNT {LDsA_6BC7    == ir1}} & I1_OF  |//      LD A,(BC)    ; 0A

    {I1DCNT {LDsA_6DE7    == ir1}} & I1_OF  |//      LD A,(DE)    ; 1A

    {I1DCNT {LDsA_6HL7    == ir1}} & I1_OF  |//      LD A,(HL)    ; 7E

    {I1DCNT {LDsB_6HL7    == ir1}} & I1_OF  |//      LD B,(HL)    ; 46

    {I1DCNT {LDsC_6HL7    == ir1}} & I1_OF  |//      LD C,(HL)    ; 4E

    {I1DCNT {LDsD_6HL7    == ir1}} & I1_OF  |//      LD D,(HL)    ; 56

    {I1DCNT {LDsE_6HL7    == ir1}} & I1_OF  |//      LD E,(HL)    ; 5E

    {I1DCNT {LDsH_6HL7    == ir1}} & I1_OF  |//      LD H,(HL)    ; 66

    {I1DCNT {LDsL_6HL7    == ir1}} & I1_OF  |//      LD L,(HL)    ; 6E

    {I1DCNT {ORs6HL7      == ir1}} & I1_OF  |//      OR (HL)      ; B6

    {I1DCNT {SBCs6HL7     == ir1}} & I1_OF  |//      SBC (HL)     ; 9E

    {I1DCNT {SUBs6HL7     == ir1}} & I1_OF  |//      SUB (HL)     ; 96

    {I1DCNT {XORs6HL7     == ir1}} & I1_OF  |//      XOR (HL)     ; AE

    {I1DCNT {LDs6BC7_A    == ir1}} & I1_OS  |//      LD (BC),A    ; 02 

    {I1DCNT {LDs6DE7_A    == ir1}} & I1_OS  |//      LD (DE),A    ; 12

    {I1DCNT {LDs6HL7_A    == ir1}} & I1_OS  |//      LD (HL),A    ; 77

    {I1DCNT {LDs6HL7_B    == ir1}} & I1_OS  |//      LD (HL),B    ; 70

    {I1DCNT {LDs6HL7_C    == ir1}} & I1_OS  |//      LD (HL),C    ; 71

    {I1DCNT {LDs6HL7_D    == ir1}} & I1_OS  |//      LD (HL),D    ; 72

    {I1DCNT {LDs6HL7_E    == ir1}} & I1_OS  |//      LD (HL),E    ; 73

    {I1DCNT {LDs6HL7_H    == ir1}} & I1_OS  |//      LD (HL),H    ; 74

    {I1DCNT {LDs6HL7_L    == ir1}} & I1_OS  |//      LD (HL),L    ; 75

    {I1DCNT {POPsAF       == ir1}} & I1_POP |//      POP AF       ; F1

    {I1DCNT {POPsBC       == ir1}} & I1_POP |//      POP BC       ; C1

    {I1DCNT {POPsDE       == ir1}} & I1_POP |//      POP DE       ; D1

    {I1DCNT {POPsHL       == ir1}} & I1_POP |//      POP HL       ; E1

    {I1DCNT {PUSHsAF      == ir1}} & I1_PUSH|//      PUSH AF      ; F5

    {I1DCNT {PUSHsBC      == ir1}} & I1_PUSH|//      PUSH BC      ; C5

    {I1DCNT {PUSHsDE      == ir1}} & I1_PUSH|//      PUSH DE      ; D5

    {I1DCNT {PUSHsHL      == ir1}} & I1_PUSH|//      PUSH HL      ; E5

    {I1DCNT {ADCsA_A      == ir1}} & I1_R2R |//      ADC A,A      ; 8F

    {I1DCNT {ADCsA_B      == ir1}} & I1_R2R |//      ADC A,B      ; 88

    {I1DCNT {ADCsA_C      == ir1}} & I1_R2R |//      ADC A,C      ; 89

    {I1DCNT {ADCsA_D      == ir1}} & I1_R2R |//      ADC A,D      ; 8A

    {I1DCNT {ADCsA_E      == ir1}} & I1_R2R |//      ADC A,E      ; 8B

    {I1DCNT {ADCsA_H      == ir1}} & I1_R2R |//      ADC A,H      ; 8C

    {I1DCNT {ADCsA_L      == ir1}} & I1_R2R |//      ADC A,L      ; 8D

    {I1DCNT {ADDsA_A      == ir1}} & I1_R2R |//      ADD A,A      ; 87

    {I1DCNT {ADDsA_B      == ir1}} & I1_R2R |//      ADD A,B      ; 80

    {I1DCNT {ADDsA_C      == ir1}} & I1_R2R |//      ADD A,C      ; 81

    {I1DCNT {ADDsA_D      == ir1}} & I1_R2R |//      ADD A,D      ; 82

    {I1DCNT {ADDsA_E      == ir1}} & I1_R2R |//      ADD A,E      ; 83

    {I1DCNT {ADDsA_H      == ir1}} & I1_R2R |//      ADD A,H      ; 84

    {I1DCNT {ADDsA_L      == ir1}} & I1_R2R |//      ADD A,L      ; 85

    {I1DCNT {ADDsHL_BC    == ir1}} & I1_R2R |//      ADD HL,BC    ; 09

    {I1DCNT {ADDsHL_DE    == ir1}} & I1_R2R |//      ADD HL,DE    ; 19

    {I1DCNT {ADDsHL_HL    == ir1}} & I1_R2R |//      ADD HL,HL    ; 29

    {I1DCNT {ADDsHL_SP    == ir1}} & I1_R2R |//      ADD HL,SP    ; 39

    {I1DCNT {ANDsA        == ir1}} & I1_R2R |//      AND A        ; A7

    {I1DCNT {ANDsB        == ir1}} & I1_R2R |//      AND B        ; A0

    {I1DCNT {ANDsC        == ir1}} & I1_R2R |//      AND C        ; A1

    {I1DCNT {ANDsD        == ir1}} & I1_R2R |//      AND D        ; A2

    {I1DCNT {ANDsE        == ir1}} & I1_R2R |//      AND E        ; A3

    {I1DCNT {ANDsH        == ir1}} & I1_R2R |//      AND H        ; A4

    {I1DCNT {ANDsL        == ir1}} & I1_R2R |//      AND L        ; A5

    {I1DCNT {CCF          == ir1}} & I1_R2R |//      CCF          ; 3F

    {I1DCNT {CPL          == ir1}} & I1_R2R |//      CPL          ; 2F

    {I1DCNT {CPsA         == ir1}} & I1_R2R |//      CP A         ; BF

    {I1DCNT {CPsB         == ir1}} & I1_R2R |//      CP B         ; B8

    {I1DCNT {CPsC         == ir1}} & I1_R2R |//      CP C         ; B9

    {I1DCNT {CPsD         == ir1}} & I1_R2R |//      CP D         ; BA

    {I1DCNT {CPsE         == ir1}} & I1_R2R |//      CP E         ; BB

    {I1DCNT {CPsH         == ir1}} & I1_R2R |//      CP H         ; BC

    {I1DCNT {CPsL         == ir1}} & I1_R2R |//      CP L         ; BD

    {I1DCNT {DAA          == ir1}} & I1_R2R |//      DAA          ; 27

    {I1DCNT {DECsA        == ir1}} & I1_R2R |//      DEC A        ; 3D

    {I1DCNT {DECsB        == ir1}} & I1_R2R |//      DEC B        ; 05

    {I1DCNT {DECsBC       == ir1}} & I1_R2R |//      DEC BC       ; 0B

    {I1DCNT {DECsC        == ir1}} & I1_R2R |//      DEC C        ; 0D

    {I1DCNT {DECsD        == ir1}} & I1_R2R |//      DEC D        ; 15

    {I1DCNT {DECsDE       == ir1}} & I1_R2R |//      DEC DE       ; 1B

    {I1DCNT {DECsE        == ir1}} & I1_R2R |//      DEC E        ; 1D

    {I1DCNT {DECsH        == ir1}} & I1_R2R |//      DEC H        ; 25

    {I1DCNT {DECsHL       == ir1}} & I1_R2R |//      DEC HL       ; 2B

    {I1DCNT {DECsL        == ir1}} & I1_R2R |//      DEC L        ; 2D

    {I1DCNT {DECsSP       == ir1}} & I1_R2R |//      DEC SP       ; 3B

    {I1DCNT {DI           == ir1}} & I1_R2R |//      DI           ; F3

    {I1DCNT {DJNZs$t2     == ir1}} & I1_R2R |//      DJNZ $+2     ; 10 XX

    {I1DCNT {EI           == ir1}} & I1_R2R |//      EI           ; FB

    {I1DCNT {EXX          == ir1}} & I1_R2R |//      EXX          ; D9

    {I1DCNT {EXsAF_AFp    == ir1}} & I1_R2R |//      EX AF,AF'    ; 08

    {I1DCNT {EXsDE_HL     == ir1}} & I1_R2R |//      EX DE,HL     ; EB

    {I1DCNT {HALT         == ir1}} & I1_R2R |//      HALT         ; 76

    {I1DCNT {INCsA        == ir1}} & I1_R2R |//      INC A        ; 3C

    {I1DCNT {INCsB        == ir1}} & I1_R2R |//      INC B       ; 04

    {I1DCNT {INCsBC       == ir1}} & I1_R2R |//      INC BC      ; 03

    {I1DCNT {INCsC        == ir1}} & I1_R2R |//      INC C       ; 0C

    {I1DCNT {INCsD        == ir1}} & I1_R2R |//      INC D        ; 14

    {I1DCNT {INCsDE       == ir1}} & I1_R2R |//      INC DE       ; 13

    {I1DCNT {INCsE        == ir1}} & I1_R2R |//      INC E        ; 1C

    {I1DCNT {INCsH        == ir1}} & I1_R2R |//      INC H        ; 24

    {I1DCNT {INCsHL       == ir1}} & I1_R2R |//      INC HL       ; 23

    {I1DCNT {INCsL        == ir1}} & I1_R2R |//      INC L        ; 2C

    {I1DCNT {INCsSP       == ir1}} & I1_R2R |//      INC SP       ; 33

    {I1DCNT {LDsA_A       == ir1}} & I1_R2R |//      LD A,A       ; 7F

    {I1DCNT {LDsA_B       == ir1}} & I1_R2R |//      LD A,B       ; 78

    {I1DCNT {LDsA_C       == ir1}} & I1_R2R |//      LD A,C       ; 79

    {I1DCNT {LDsA_D       == ir1}} & I1_R2R |//      LD A,D       ; 7A

    {I1DCNT {LDsA_E       == ir1}} & I1_R2R |//      LD A,E       ; 7B

    {I1DCNT {LDsA_H       == ir1}} & I1_R2R |//      LD A,H       ; 7C

    {I1DCNT {LDsA_L       == ir1}} & I1_R2R |//      LD A,L       ; 7D

    {I1DCNT {LDsB_A       == ir1}} & I1_R2R |//      LD B,A       ; 47

    {I1DCNT {LDsB_B       == ir1}} & I1_R2R |//      LD B,B       ; 40

    {I1DCNT {LDsB_C       == ir1}} & I1_R2R |//      LD B,C       ; 41

    {I1DCNT {LDsB_D       == ir1}} & I1_R2R |//      LD B,D       ; 42

    {I1DCNT {LDsB_E       == ir1}} & I1_R2R |//      LD B,E       ; 43

    {I1DCNT {LDsB_H       == ir1}} & I1_R2R |//      LD B,H       ; 44

    {I1DCNT {LDsB_L       == ir1}} & I1_R2R |//      LD B,L       ; 45