OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [DataPath.vhd] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 17 leonardoar
--! @file
2
--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
3
 
4
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
5
library IEEE;
6
use ieee.std_logic_1164.all;
7
use ieee.std_logic_unsigned.all;
8
use ieee.std_logic_arith.all;
9
 
10
--! Use CPU Definitions package
11
use work.pkgOpenCPU32.all;
12
 
13
--! A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations.\n
14
--! Most central processing units consist of a datapath and a control unit, with a large part of the control unit dedicated to 
15
--! regulating the interaction between the datapath and main memory.
16
 
17
--! The purpose of datapaths is to provide routes for data to travel between functional units.
18
entity DataPath is
19
    generic (n : integer := nBits - 1);                                                                 --! Generic value (Used to easily change the size of the Alu on the package)
20
         Port ( inputMm : in  STD_LOGIC_VECTOR (n downto 0);                     --! Input of Datapath from main memory       
21
                          inputImm : in  STD_LOGIC_VECTOR (n downto 0);                  --! Input of Datapath from imediate value (instructions...)
22
                          clk : in  STD_LOGIC;                                                                                          --! Clock signal
23
           outEn : in  typeEnDis;                                                                                       --! Enable/Disable datapath output
24
           aluOp : in  aluOps;                                                                                          --! Alu operations
25
           muxSel : in  STD_LOGIC_VECTOR (2 downto 0);                           --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
26 27 leonardoar
                          muxRegFile : in STD_LOGIC_VECTOR(1 downto 0);                          --! Select Alu InputA (Memory,Imediate,RegFileA)
27 17 leonardoar
           regFileWriteAddr : in  generalRegisters;                                     --! General register write address
28
           regFileWriteEn : in  STD_LOGIC;                                                              --! RegisterFile write enable signal
29
           regFileReadAddrA : in  generalRegisters;                                     --! General register read address (PortA)
30
           regFileReadAddrB : in  generalRegisters;                                     --! General register read address (PortB)
31
           regFileEnA : in  STD_LOGIC;                                                                          --! Enable RegisterFile PortA
32
           regFileEnB : in  STD_LOGIC;                                                                          --! Enable RegisterFile PortB
33
                          outputDp : out  STD_LOGIC_VECTOR (n downto 0);                 --! DataPath Output
34 29 leonardoar
           dpFlags : out  STD_LOGIC_VECTOR (2 downto 0));                        --! Alu Flags
35 17 leonardoar
end DataPath;
36
 
37
--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
38
--! @details This description will also show how to instantiate components(Alu, RegisterFile, Multiplexer) on your design
39
architecture Behavioral of DataPath is
40
 
41 19 leonardoar
--! Component declaration to instantiate the Multiplexer circuit
42
COMPONENT Multiplexer4_1
43
        generic (n : integer := nBits - 1);                                     --! Generic value (Used to easily change the size of the Alu on the package)
44
        Port ( A   : in  STD_LOGIC_VECTOR (n downto 0);  --! First Input
45
                  B   : in  STD_LOGIC_VECTOR (n downto 0);       --! Second Input
46
                  C   : in  STD_LOGIC_VECTOR (n downto 0);       --! Third Input
47
                  D   : in  STD_LOGIC_VECTOR (n downto 0);       --! Forth Input
48
                  E   : in  STD_LOGIC_VECTOR (n downto 0);       --! Fifth Input
49
        sel : in  STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
50
                  S   : out  STD_LOGIC_VECTOR (n downto 0));     --! Mux Output
51
END COMPONENT;
52
 
53 27 leonardoar
--! Component declaration to instantiate the Multiplexer3_1 circuit
54
COMPONENT Multiplexer3_1 is
55
    generic (n : integer := nBits - 1);                                 --! Generic value (Used to easily change the size of the Alu on the package)
56
         Port ( A : in  STD_LOGIC_VECTOR (n downto 0);           --! First Input
57
           B : in  STD_LOGIC_VECTOR (n downto 0);                --! Second Input
58
           C : in  STD_LOGIC_VECTOR (n downto 0);                --! Third Input
59
           sel : in  STD_LOGIC_VECTOR(1 downto 0);               --! Select inputs (1, 2, 3)
60
           S : out  STD_LOGIC_VECTOR (n downto 0));      --! Mux Output
61
end COMPONENT;
62
 
63 19 leonardoar
--! Component declaration to instantiate the Alu circuit
64
COMPONENT Alu
65 29 leonardoar
        generic (n : integer := nBits - 1);                                             --! Generic value (Used to easily change the size of the Alu on the package)
66 19 leonardoar
        Port ( A : in  STD_LOGIC_VECTOR (n downto 0);            --! Alu Operand 1
67 29 leonardoar
                  B : in  STD_LOGIC_VECTOR (n downto 0);                 --! Alu Operand 2
68
                  S : out  STD_LOGIC_VECTOR (n downto 0);                        --! Alu Output
69
                  flagsOut : out STD_LOGIC_VECTOR(2 downto 0);   --! Flags from current operation
70
                  sel : in  aluOps);                                                                            --! Select operation
71 19 leonardoar
END COMPONENT;
72
 
73
--! Component declaration to instantiate the testRegisterFile circuit
74
COMPONENT RegisterFile
75
        generic (n : integer := nBits - 1);                                             --! Generic value (Used to easily change the size of the registers)
76
        Port ( clk : in  STD_LOGIC;                                                             --! Clock signal
77
                  writeEn : in  STD_LOGIC;                                                              --! Write enable
78
                  writeAddr : in  generalRegisters;                                     --! Write Adress
79
                  input : in  STD_LOGIC_VECTOR (n downto 0);             --! Input 
80
                  Read_A_En : in  STD_LOGIC;                                                    --! Enable read A
81
                  Read_A_Addr : in  generalRegisters;                           --! Read A adress
82
                  Read_B_En : in  STD_LOGIC;                                                    --! Enable read A
83
                  Read_B_Addr : in  generalRegisters;                   --! Read B adress
84
                  A_Out : out  STD_LOGIC_VECTOR (n downto 0);    --! Output A
85
                  B_Out : out  STD_LOGIC_VECTOR (n downto 0));   --! Output B
86
END COMPONENT;
87
 
88
COMPONENT TriStateBuffer
89
        generic (n : integer := nBits - 1);                             --! Generic value (Used to easily change the size of the Alu on the package)
90
        PORT(
91
                A : IN  std_logic_vector(n downto 0);            --! Buffer Input
92
                sel : IN  typeEnDis;                                                            --! Enable or Disable the output
93
                S : OUT  std_logic_vector(n downto 0)            --! Enable or Disable the output
94
          );
95
END COMPONENT;
96
 
97
-- Signals that will connect the various components from the DataPath
98
signal regFilePortA : STD_LOGIC_VECTOR (n downto 0);
99
signal regFilePortB : STD_LOGIC_VECTOR (n downto 0);
100
signal aluOut             : STD_LOGIC_VECTOR (n downto 0);
101
signal muxOut             : STD_LOGIC_VECTOR (n downto 0);
102 27 leonardoar
signal muxOutReg          : STD_LOGIC_VECTOR (n downto 0);
103 17 leonardoar
begin
104 27 leonardoar
        --! Instantiate Multiplexer 5:1
105 19 leonardoar
   uMux: Multiplexer4_1 PORT MAP (
106
          A => inputMm,
107
          B => inputImm,
108
                         C => regFilePortA,
109
                         D => regFilePortB,
110
                         E => aluOut,
111
          sel => muxSel,
112
          S => muxOut
113
        );
114
 
115 27 leonardoar
        --! Instantiate Multiplexer 5:1
116
   uMux2: Multiplexer3_1 PORT MAP (
117
          A => inputMm,
118
          B => inputImm,
119
                         C => regFilePortA,
120
          sel => muxRegFile,
121
          S => muxOutReg
122
        );
123
 
124 19 leonardoar
        --! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
125
   uAlu: Alu PORT MAP (
126 27 leonardoar
          A => muxOutReg,
127 20 leonardoar
          B => regFilePortB,
128 19 leonardoar
          S => aluOut,
129 29 leonardoar
                         flagsOut => dpFlags,
130 19 leonardoar
          sel => aluOp
131
        );
132
 
133
        --! Instantiate the Unit Under Test (RegisterFile) (Doxygen bug if it's not commented!)
134
   uRegisterFile: RegisterFile PORT MAP (
135
          clk => clk,
136
          writeEn => regFileWriteEn,
137
          writeAddr => regFileWriteAddr,
138
          input => muxOut,
139
          Read_A_En => regFileEnA,
140
          Read_A_Addr => regFileReadAddrA,
141
          Read_B_En => regFileEnB,
142
          Read_B_Addr => regFileReadAddrB,
143
          A_Out => regFilePortA,
144
          B_Out => regFilePortB
145
        );
146
 
147
        --!Instantiate the Unit Under Test (Multiplexer2_1) (Doxygen bug if it's not commented!)
148
   uTriState: TriStateBuffer PORT MAP (
149
          A => muxOut,
150
          sel => outEn,
151
          S => outputDp
152
        );
153 17 leonardoar
 
154
end Behavioral;
155
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.