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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [Multiplexer4_1.vhd] - Blame information for rev 42

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--! @file
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--! @brief 4:1 Mux using with-select
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--! Use standard library
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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--! Mux 5->1 circuit can select one of the 2 inputs into one output with some selection signal
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--! Detailed description of this 
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--! mux design element.
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entity Multiplexer4_1 is
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    generic (n : integer := nBits - 1);                                 --! Generic value (Used to easily change the size of the Alu on the package)
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         Port ( A   : in  STD_LOGIC_VECTOR (n downto 0); --! First Input
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           B   : in  STD_LOGIC_VECTOR (n downto 0);      --! Second Input
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                          C   : in  STD_LOGIC_VECTOR (n downto 0);       --! Third Input
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                          D   : in  STD_LOGIC_VECTOR (n downto 0);       --! Forth Input
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                          E   : in  STD_LOGIC_VECTOR (n downto 0);       --! Fifth Input
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           sel : in  dpMuxInputs;                                                       --! Select inputs (1, 2, 3, 4, 5)
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           S   : out  STD_LOGIC_VECTOR (n downto 0));    --! Mux Output
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end Multiplexer4_1;
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--! @brief Architure definition of the MUX
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--! @details On this case we're going to use VHDL combinational description
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architecture Behavioral of Multiplexer4_1 is
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begin
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        with sel select
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                S <= A when fromMemory,
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                          B when fromImediate,
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                          C when fromRegFileA,
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                          D when fromRegFileB,
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                          E when fromAlu,
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                          (others => 'Z') when others;
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end Behavioral;
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