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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [TriStateBuffer.vhd] - Blame information for rev 16
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--! @file
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--! @brief Tri-State buffer http://en.wikipedia.org/wiki/Three-state_logic
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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--! In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a \n
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--! high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit.
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--! In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a \n
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--! high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit.
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--! This allows multiple circuits to share the same output line or lines (such as a bus).
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entity TriStateBuffer is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Buffer Input
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sel : in typeEnDis; --! Enable or Disable the output
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S : out STD_LOGIC_VECTOR (n downto 0)); --! TriState buffer output
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end TriStateBuffer;
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--! @brief Architure definition of the TriStateBuffer
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--! @details On this case we're going to use VHDL combinational description (Simple combination circuit)
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architecture Behavioral of TriStateBuffer is
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begin
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with sel select
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S <= A when enable,
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(others => 'Z') when disable;
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end Behavioral;
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