URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testControlUnit.vhd] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log


--! @file
--! @brief Testbench for ControlUnit
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
ENTITY testControlUnit IS
generic (n : integer := nBits - 1);                                                                     --! Generic value (Used to easily change the size of the Alu on the package)
END testControlUnit;
 
--! @brief ControlUnit Testbench file
--! @details Exercise the control unit with a assembly program sample
--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
ARCHITECTURE behavior OF testControlUnit IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ControlUnit
    generic (n : integer := nBits - 1);                                                                 --! Generic value (Used to easily change the size of the Alu on the package)
         Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;                                                                                         --! Main system clock
           FlagsDp : in  STD_LOGIC_VECTOR (2 downto 0);                          --! Flags comming from the Datapath
           DataDp : in  STD_LOGIC_VECTOR (n downto 0);                           --! Data comming from the Datapath
                          outEnDp : out  typeEnDis;                                                                             --! Enable/Disable datapath output
           MuxDp : out  STD_LOGIC_VECTOR (2 downto 0);                           --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
                          MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0);                           --! Select Alu InputA (Memory,Imediate,RegFileA)
           ImmDp : out  STD_LOGIC_VECTOR (n downto 0);                           --! Imediate value passed to the Datapath
           DpAluOp : out  aluOps;                                                                                       --! Alu operations
                          DpRegFileWriteAddr : out  generalRegisters;                           --! General register address to write
           DpRegFileWriteEn : out  STD_LOGIC;                                                   --! Enable register write
           DpRegFileReadAddrA : out  generalRegisters;                          --! General register address to read
           DpRegFileReadAddrB : out  generalRegisters;                          --! General register address to read
           DpRegFileReadEnA : out  STD_LOGIC;                                                   --! Enable register read (PortA)
           DpRegFileReadEnB : out  STD_LOGIC;                                                   --! Enable register read (PortB)
           MemoryDataReadEn : out std_logic;                                                            --! Enable Main memory read
                          MemoryDataWriteEn: out std_logic;                                                             --! Enable Main memory write
                          MemoryDataInput : in  STD_LOGIC_VECTOR (n downto 0);   --! Incoming data from main memory
           MemoryDataRdAddr : out  STD_LOGIC_VECTOR (n downto 0);        --! Main memory Read address
                          MemoryDataWrAddr : out  STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
           MemoryDataOut : out  STD_LOGIC_VECTOR (n downto 0));  --! Data to write on main memory
    END COMPONENT;
 
 
   --Inputs
   signal reset : std_logic := '0';                                                                                                                      --! Wire to connect Test signal to component
   signal clk : std_logic := '0';                                                                                                                        --! Wire to connect Test signal to component
   signal FlagsDp : std_logic_vector(2 downto 0) := (others => '0');                              --! Wire to connect Test signal to component
   signal DataDp : std_logic_vector(n downto 0) := (others => '0');                               --! Wire to connect Test signal to component
   signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0');      --! Wire to connect Test signal to component
 
        --Outputs
   signal outEnDp : typeEnDis;                                                                                                                          --! Wire to connect Test signal to component
        signal MuxDp : std_logic_vector(2 downto 0);                                                                                     --! Wire to connect Test signal to component
        signal MuxRegDp : std_logic_vector(1 downto 0);                                                                          --! Wire to connect Test signal to component
   signal ImmDp : std_logic_vector(n downto 0);                                                                                  --! Wire to connect Test signal to component
        signal DpAluOp : aluOps;                                                                                                                                        --! Wire to connect Test signal to component
   signal DpRegFileWriteAddr : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileWriteEn : std_logic;                                                                                                 --! Wire to connect Test signal to component
   signal DpRegFileReadAddrA : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileReadAddrB : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileReadEnA : std_logic;                                                                                                 --! Wire to connect Test signal to component
   signal DpRegFileReadEnB : std_logic;                                                                                                 --! Wire to connect Test signal to component
        signal MemoryDataReadEn : std_logic;                                                                                                    --! Wire to connect Test signal to component
        signal MemoryDataWriteEn : std_logic;                                                                                                   --! Wire to connect Test signal to component
        signal MemoryDataRdAddr : std_logic_vector(n downto 0);                                                  --! Wire to connect Test signal to component
   signal MemoryDataWrAddr : std_logic_vector(n downto 0);                                                       --! Wire to connect Test signal to component
   signal MemoryDataOut : std_logic_vector(n downto 0);                                                          --! Wire to connect Test signal to component
 
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
        --! Instantiate the Unit Under Test (ControlUnit)
   uut: ControlUnit PORT MAP (
                        reset => reset,
                        clk => clk,
                        FlagsDp => FlagsDp,
                        DataDp => DataDp,
                        outEnDp => outEnDp,
                        MuxDp => MuxDp,
                        MuxRegDp => MuxRegDp,
                        ImmDp => ImmDp,
                        DpAluOp => DpAluOp,
                        DpRegFileWriteAddr => DpRegFileWriteAddr,
                        DpRegFileWriteEn => DpRegFileWriteEn,
                        DpRegFileReadAddrA => DpRegFileReadAddrA,
                        DpRegFileReadAddrB => DpRegFileReadAddrB,
                        DpRegFileReadEnA => DpRegFileReadEnA,
                        DpRegFileReadEnB => DpRegFileReadEnB,
                        MemoryDataReadEn => MemoryDataReadEn,
                        MemoryDataWriteEn => MemoryDataWriteEn,
                        MemoryDataInput => MemoryDataInput,
                        MemoryDataRdAddr => MemoryDataRdAddr,
                        MemoryDataWrAddr => MemoryDataWrAddr,
                        MemoryDataOut => MemoryDataOut
        );
 
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
   begin
                -- Reset operation
                REPORT "RESET" SEVERITY NOTE;
                reset <= '1';
      wait for 2 ns;
                reset <= '0';
                wait for 2 ns;
 
      -- MOV r0,10d (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r0,10" SEVERITY NOTE;
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
                wait for CLK_period;    -- Executing ... 1
                wait for CLK_period;    -- Executing ... 2
 
                -- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r1,20" SEVERITY NOTE;
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
                wait for CLK_period;    -- Executing ... 1
                wait for CLK_period;    -- Executing ... 2
 
      wait;
   end process;
 
END;

Line No.	Rev	Author	Line
1	22	leonardoar	`--! @file`
2			`--! @brief Testbench for ControlUnit`
3
4			`--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)`
5			`library IEEE;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.std_logic_unsigned.all;`
8			`use ieee.std_logic_arith.all;`
9
10			`--! Use CPU Definitions package`
11			`use work.pkgOpenCPU32.all;`
12
13			`ENTITY testControlUnit IS`
14	32	leonardoar	`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
15	22	leonardoar	`END testControlUnit;`
16
17			`--! @brief ControlUnit Testbench file`
18			`--! @details Exercise the control unit with a assembly program sample`
19			`--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html`
20			`ARCHITECTURE behavior OF testControlUnit IS`
21
22			`-- Component Declaration for the Unit Under Test (UUT)`
23
24			`COMPONENT ControlUnit`
25	32	leonardoar	`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
26			`Port ( reset : in STD_LOGIC;`
27			`clk : in STD_LOGIC; --! Main system clock`
28			`FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath`
29			`DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath`
30			`outEnDp : out typeEnDis; --! Enable/Disable datapath output`
31			`MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)`
32			`MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)`
33			`ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath`
34			`DpAluOp : out aluOps; --! Alu operations`
35			`DpRegFileWriteAddr : out generalRegisters; --! General register address to write`
36			`DpRegFileWriteEn : out STD_LOGIC; --! Enable register write`
37			`DpRegFileReadAddrA : out generalRegisters; --! General register address to read`
38			`DpRegFileReadAddrB : out generalRegisters; --! General register address to read`
39			`DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)`
40			`DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)`
41			`MemoryDataReadEn : out std_logic; --! Enable Main memory read`
42			`MemoryDataWriteEn: out std_logic; --! Enable Main memory write`
43			`MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory`
44			`MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address`
45			`MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address`
46			`MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory`
47	22	leonardoar	`END COMPONENT;`
48
49
50			`--Inputs`
51			`signal reset : std_logic := '0'; --! Wire to connect Test signal to component`
52			`signal clk : std_logic := '0'; --! Wire to connect Test signal to component`
53	32	leonardoar	`signal FlagsDp : std_logic_vector(2 downto 0) := (others => '0'); --! Wire to connect Test signal to component`
54			`signal DataDp : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component`
55			`signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component`
56	22	leonardoar
57			`--Outputs`
58	32	leonardoar	`signal outEnDp : typeEnDis; --! Wire to connect Test signal to component`
59			`signal MuxDp : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component`
60			`signal MuxRegDp : std_logic_vector(1 downto 0); --! Wire to connect Test signal to component`
61			`signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
62			`signal DpAluOp : aluOps; --! Wire to connect Test signal to component`
63			`signal DpRegFileWriteAddr : generalRegisters; --! Wire to connect Test signal to component`
64	22	leonardoar	`signal DpRegFileWriteEn : std_logic; --! Wire to connect Test signal to component`
65	32	leonardoar	`signal DpRegFileReadAddrA : generalRegisters; --! Wire to connect Test signal to component`
66			`signal DpRegFileReadAddrB : generalRegisters; --! Wire to connect Test signal to component`
67	22	leonardoar	`signal DpRegFileReadEnA : std_logic; --! Wire to connect Test signal to component`
68			`signal DpRegFileReadEnB : std_logic; --! Wire to connect Test signal to component`
69	32	leonardoar	`signal MemoryDataReadEn : std_logic; --! Wire to connect Test signal to component`
70			`signal MemoryDataWriteEn : std_logic; --! Wire to connect Test signal to component`
71			`signal MemoryDataRdAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
72			`signal MemoryDataWrAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
73			`signal MemoryDataOut : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
74	22	leonardoar
75			`-- Clock period definitions`
76			`constant clk_period : time := 10 ns;`
77
78			`BEGIN`
79
80			`--! Instantiate the Unit Under Test (ControlUnit)`
81	32	leonardoar	`uut: ControlUnit PORT MAP (`
82			`reset => reset,`
83			`clk => clk,`
84			`FlagsDp => FlagsDp,`
85			`DataDp => DataDp,`
86			`outEnDp => outEnDp,`
87			`MuxDp => MuxDp,`
88			`MuxRegDp => MuxRegDp,`
89			`ImmDp => ImmDp,`
90			`DpAluOp => DpAluOp,`
91			`DpRegFileWriteAddr => DpRegFileWriteAddr,`
92			`DpRegFileWriteEn => DpRegFileWriteEn,`
93			`DpRegFileReadAddrA => DpRegFileReadAddrA,`
94			`DpRegFileReadAddrB => DpRegFileReadAddrB,`
95			`DpRegFileReadEnA => DpRegFileReadEnA,`
96			`DpRegFileReadEnB => DpRegFileReadEnB,`
97			`MemoryDataReadEn => MemoryDataReadEn,`
98			`MemoryDataWriteEn => MemoryDataWriteEn,`
99			`MemoryDataInput => MemoryDataInput,`
100			`MemoryDataRdAddr => MemoryDataRdAddr,`
101			`MemoryDataWrAddr => MemoryDataWrAddr,`
102			`MemoryDataOut => MemoryDataOut`
103	22	leonardoar	`);`
104
105			`-- Clock process definitions`
106			`clk_process :process`
107			`begin`
108			`clk <= '0';`
109			`wait for clk_period/2;`
110			`clk <= '1';`
111			`wait for clk_period/2;`
112			`end process;`
113
114
115			`-- Stimulus process`
116			`stim_proc: process`
117	32	leonardoar	`begin`
118			`-- Reset operation`
119			`REPORT "RESET" SEVERITY NOTE;`
120			`reset <= '1';`
121			`wait for 2 ns;`
122			`reset <= '0';`
123			`wait for 2 ns;`
124	22	leonardoar
125	33	leonardoar	`-- MOV r0,10d (Compare control unit outputs with Datapath)--------------------------------------`
126	32	leonardoar	`REPORT "MOV r0,10" SEVERITY NOTE;`
127	33	leonardoar	`MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);`
128			`wait for CLK_period; -- Fetch`
129			`wait for CLK_period; -- Decode`
130			`wait for CLK_period; -- Execute`
131			`wait for CLK_period; -- Executing ... 1`
132			`wait for CLK_period; -- Executing ... 2`
133
134			`-- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------`
135			`REPORT "MOV r1,20" SEVERITY NOTE;`
136			`MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);`
137			`wait for CLK_period; -- Fetch`
138			`wait for CLK_period; -- Decode`
139			`wait for CLK_period; -- Execute`
140			`wait for CLK_period; -- Executing ... 1`
141			`wait for CLK_period; -- Executing ... 2`
142	22	leonardoar
143			`wait;`
144			`end process;`
145
146			`END;`

Browse

Tools

Subversion Repositories opencpu32

[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testControlUnit.vhd] - Blame information for rev 33