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--! @file
--! @brief Testbench for ControlUnit
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! Adding library for File I/O 
-- More information on this site:
-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
use std.textio.ALL;
use ieee.std_logic_textio.all;
 
ENTITY testControlUnit IS
generic (n : integer := nBits - 1);                                                                     --! Generic value (Used to easily change the size of the Alu on the package)
END testControlUnit;
 
--! @brief ControlUnit Testbench file
--! @details Exercise the control unit with a assembly program sample
--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
ARCHITECTURE behavior OF testControlUnit IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ControlUnit
    generic (n : integer := nBits - 1);                                                                 --! Generic value (Used to easily change the size of the Alu on the package)
         Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;                                                                                         --! Main system clock
           FlagsDp : in  STD_LOGIC_VECTOR (2 downto 0);                          --! Flags comming from the Datapath
           DataDp : in  STD_LOGIC_VECTOR (n downto 0);                           --! Data comming from the Datapath
                          outEnDp : out  typeEnDis;                                                                             --! Enable/Disable datapath output
           MuxDp : out  STD_LOGIC_VECTOR (2 downto 0);                           --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
                          MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0);                           --! Select Alu InputA (Memory,Imediate,RegFileA)
           ImmDp : out  STD_LOGIC_VECTOR (n downto 0);                           --! Imediate value passed to the Datapath
           DpAluOp : out  aluOps;                                                                                       --! Alu operations
                          DpRegFileWriteAddr : out  generalRegisters;                           --! General register address to write
           DpRegFileWriteEn : out  STD_LOGIC;                                                   --! Enable register write
           DpRegFileReadAddrA : out  generalRegisters;                          --! General register address to read
           DpRegFileReadAddrB : out  generalRegisters;                          --! General register address to read
           DpRegFileReadEnA : out  STD_LOGIC;                                                   --! Enable register read (PortA)
           DpRegFileReadEnB : out  STD_LOGIC;                                                   --! Enable register read (PortB)
           MemoryDataReadEn : out std_logic;                                                            --! Enable Main memory read
                          MemoryDataWriteEn: out std_logic;                                                             --! Enable Main memory write
                          MemoryDataInput : in  STD_LOGIC_VECTOR (n downto 0);   --! Incoming data from main memory
           MemoryDataRdAddr : out  STD_LOGIC_VECTOR (n downto 0);        --! Main memory Read address
                          MemoryDataWrAddr : out  STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
           MemoryDataOut : out  STD_LOGIC_VECTOR (n downto 0));  --! Data to write on main memory
    END COMPONENT;
 
 
   --Inputs
   signal reset : std_logic := '0';                                                                                                                      --! Wire to connect Test signal to component
   signal clk : std_logic := '0';                                                                                                                        --! Wire to connect Test signal to component
   signal FlagsDp : std_logic_vector(2 downto 0) := (others => '0');                              --! Wire to connect Test signal to component
   signal DataDp : std_logic_vector(n downto 0) := (others => '0');                               --! Wire to connect Test signal to component
   signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0');      --! Wire to connect Test signal to component
 
        --Outputs
   signal outEnDp : typeEnDis;                                                                                                                          --! Wire to connect Test signal to component
        signal MuxDp : std_logic_vector(2 downto 0);                                                                                     --! Wire to connect Test signal to component
        signal MuxRegDp : std_logic_vector(1 downto 0);                                                                          --! Wire to connect Test signal to component
   signal ImmDp : std_logic_vector(n downto 0);                                                                                  --! Wire to connect Test signal to component
        signal DpAluOp : aluOps;                                                                                                                                        --! Wire to connect Test signal to component
   signal DpRegFileWriteAddr : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileWriteEn : std_logic;                                                                                                 --! Wire to connect Test signal to component
   signal DpRegFileReadAddrA : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileReadAddrB : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileReadEnA : std_logic;                                                                                                 --! Wire to connect Test signal to component
   signal DpRegFileReadEnB : std_logic;                                                                                                 --! Wire to connect Test signal to component
        signal MemoryDataReadEn : std_logic;                                                                                                    --! Wire to connect Test signal to component
        signal MemoryDataWriteEn : std_logic;                                                                                                   --! Wire to connect Test signal to component
        signal MemoryDataRdAddr : std_logic_vector(n downto 0);                                                  --! Wire to connect Test signal to component
   signal MemoryDataWrAddr : std_logic_vector(n downto 0);                                                       --! Wire to connect Test signal to component
   signal MemoryDataOut : std_logic_vector(n downto 0);                                                          --! Wire to connect Test signal to component
 
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
        --! Instantiate the Unit Under Test (ControlUnit)
   uut: ControlUnit PORT MAP (
                        reset => reset,
                        clk => clk,
                        FlagsDp => FlagsDp,
                        DataDp => DataDp,
                        outEnDp => outEnDp,
                        MuxDp => MuxDp,
                        MuxRegDp => MuxRegDp,
                        ImmDp => ImmDp,
                        DpAluOp => DpAluOp,
                        DpRegFileWriteAddr => DpRegFileWriteAddr,
                        DpRegFileWriteEn => DpRegFileWriteEn,
                        DpRegFileReadAddrA => DpRegFileReadAddrA,
                        DpRegFileReadAddrB => DpRegFileReadAddrB,
                        DpRegFileReadEnA => DpRegFileReadEnA,
                        DpRegFileReadEnB => DpRegFileReadEnB,
                        MemoryDataReadEn => MemoryDataReadEn,
                        MemoryDataWriteEn => MemoryDataWriteEn,
                        MemoryDataInput => MemoryDataInput,
                        MemoryDataRdAddr => MemoryDataRdAddr,
                        MemoryDataWrAddr => MemoryDataWrAddr,
                        MemoryDataOut => MemoryDataOut
        );
 
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
        variable line_out: Line; -- Line that will be written to a file
        file cmdfile: TEXT;      -- Define the file 'handle'
   begin
                -- Reset operation
                REPORT "RESET" SEVERITY NOTE;
                -- Open source file for write...
                FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",WRITE_MODE);
                reset <= '1';
      wait for 2 ns;
                reset <= '0';
                wait for 2 ns;
 
      -- MOV r0,10d (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r0,10" SEVERITY NOTE;
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid
                assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r1,20" SEVERITY NOTE;
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid
                assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- MOV r2,r1 (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r2,r1" SEVERITY NOTE;
                MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid         
                assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- ADD r2,r0 (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "ADD r2,r0" SEVERITY NOTE;
                MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid         
                assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
                assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
                assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;
                assert MuxRegDp = muxRegPos(fromRegFileA) report "Invalid value" severity FAILURE;
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- ADD r2,2 (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "ADD r2,2" SEVERITY NOTE;
                MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid         
                assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
      assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
                assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;
                assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
      -- Close file
                file_close(cmdfile);
                -- Finish simulation
                assert false report "NONE. End of simulation." severity failure;
                wait;
   end process;
 
END;

Line No.	Rev	Author	Line
1	22	leonardoar	`--! @file`
2			`--! @brief Testbench for ControlUnit`
3
4			`--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)`
5			`library IEEE;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.std_logic_unsigned.all;`
8			`use ieee.std_logic_arith.all;`
9
10			`--! Use CPU Definitions package`
11			`use work.pkgOpenCPU32.all;`
12	40	leonardoar
13			`--! Adding library for File I/O`
14			`-- More information on this site:`
15			`-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm`
16			`use std.textio.ALL;`
17			`use ieee.std_logic_textio.all;`
18	22	leonardoar
19			`ENTITY testControlUnit IS`
20	32	leonardoar	`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
21	22	leonardoar	`END testControlUnit;`
22
23			`--! @brief ControlUnit Testbench file`
24			`--! @details Exercise the control unit with a assembly program sample`
25			`--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html`
26			`ARCHITECTURE behavior OF testControlUnit IS`
27
28			`-- Component Declaration for the Unit Under Test (UUT)`
29
30			`COMPONENT ControlUnit`
31	32	leonardoar	`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
32			`Port ( reset : in STD_LOGIC;`
33			`clk : in STD_LOGIC; --! Main system clock`
34			`FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath`
35			`DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath`
36			`outEnDp : out typeEnDis; --! Enable/Disable datapath output`
37			`MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)`
38			`MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)`
39			`ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath`
40			`DpAluOp : out aluOps; --! Alu operations`
41			`DpRegFileWriteAddr : out generalRegisters; --! General register address to write`
42			`DpRegFileWriteEn : out STD_LOGIC; --! Enable register write`
43			`DpRegFileReadAddrA : out generalRegisters; --! General register address to read`
44			`DpRegFileReadAddrB : out generalRegisters; --! General register address to read`
45			`DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)`
46			`DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)`
47			`MemoryDataReadEn : out std_logic; --! Enable Main memory read`
48			`MemoryDataWriteEn: out std_logic; --! Enable Main memory write`
49			`MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory`
50			`MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address`
51			`MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address`
52			`MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory`
53	22	leonardoar	`END COMPONENT;`
54
55
56			`--Inputs`
57			`signal reset : std_logic := '0'; --! Wire to connect Test signal to component`
58			`signal clk : std_logic := '0'; --! Wire to connect Test signal to component`
59	32	leonardoar	`signal FlagsDp : std_logic_vector(2 downto 0) := (others => '0'); --! Wire to connect Test signal to component`
60			`signal DataDp : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component`
61			`signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component`
62	22	leonardoar
63			`--Outputs`
64	32	leonardoar	`signal outEnDp : typeEnDis; --! Wire to connect Test signal to component`
65			`signal MuxDp : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component`
66			`signal MuxRegDp : std_logic_vector(1 downto 0); --! Wire to connect Test signal to component`
67			`signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
68			`signal DpAluOp : aluOps; --! Wire to connect Test signal to component`
69			`signal DpRegFileWriteAddr : generalRegisters; --! Wire to connect Test signal to component`
70	22	leonardoar	`signal DpRegFileWriteEn : std_logic; --! Wire to connect Test signal to component`
71	32	leonardoar	`signal DpRegFileReadAddrA : generalRegisters; --! Wire to connect Test signal to component`
72			`signal DpRegFileReadAddrB : generalRegisters; --! Wire to connect Test signal to component`
73	22	leonardoar	`signal DpRegFileReadEnA : std_logic; --! Wire to connect Test signal to component`
74			`signal DpRegFileReadEnB : std_logic; --! Wire to connect Test signal to component`
75	32	leonardoar	`signal MemoryDataReadEn : std_logic; --! Wire to connect Test signal to component`
76			`signal MemoryDataWriteEn : std_logic; --! Wire to connect Test signal to component`
77			`signal MemoryDataRdAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
78			`signal MemoryDataWrAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
79			`signal MemoryDataOut : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
80	22	leonardoar
81			`-- Clock period definitions`
82			`constant clk_period : time := 10 ns;`
83
84			`BEGIN`
85
86			`--! Instantiate the Unit Under Test (ControlUnit)`
87	32	leonardoar	`uut: ControlUnit PORT MAP (`
88			`reset => reset,`
89			`clk => clk,`
90			`FlagsDp => FlagsDp,`
91			`DataDp => DataDp,`
92			`outEnDp => outEnDp,`
93			`MuxDp => MuxDp,`
94			`MuxRegDp => MuxRegDp,`
95			`ImmDp => ImmDp,`
96			`DpAluOp => DpAluOp,`
97			`DpRegFileWriteAddr => DpRegFileWriteAddr,`
98			`DpRegFileWriteEn => DpRegFileWriteEn,`
99			`DpRegFileReadAddrA => DpRegFileReadAddrA,`
100			`DpRegFileReadAddrB => DpRegFileReadAddrB,`
101			`DpRegFileReadEnA => DpRegFileReadEnA,`
102			`DpRegFileReadEnB => DpRegFileReadEnB,`
103			`MemoryDataReadEn => MemoryDataReadEn,`
104			`MemoryDataWriteEn => MemoryDataWriteEn,`
105			`MemoryDataInput => MemoryDataInput,`
106			`MemoryDataRdAddr => MemoryDataRdAddr,`
107			`MemoryDataWrAddr => MemoryDataWrAddr,`
108			`MemoryDataOut => MemoryDataOut`
109	22	leonardoar	`);`
110
111			`-- Clock process definitions`
112			`clk_process :process`
113			`begin`
114			`clk <= '0';`
115			`wait for clk_period/2;`
116			`clk <= '1';`
117			`wait for clk_period/2;`
118			`end process;`
119
120
121			`-- Stimulus process`
122			`stim_proc: process`
123	40	leonardoar	`variable line_out: Line; -- Line that will be written to a file`
124			`file cmdfile: TEXT; -- Define the file 'handle'`
125	32	leonardoar	`begin`
126			`-- Reset operation`
127			`REPORT "RESET" SEVERITY NOTE;`
128	40	leonardoar	`-- Open source file for write...`
129			`FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",WRITE_MODE);`
130	32	leonardoar	`reset <= '1';`
131			`wait for 2 ns;`
132			`reset <= '0';`
133			`wait for 2 ns;`
134	22	leonardoar
135	33	leonardoar	`-- MOV r0,10d (Compare control unit outputs with Datapath)--------------------------------------`
136	32	leonardoar	`REPORT "MOV r0,10" SEVERITY NOTE;`
137	40	leonardoar	`MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);`
138	33	leonardoar	`wait for CLK_period; -- Fetch`
139			`wait for CLK_period; -- Decode`
140			`wait for CLK_period; -- Execute`
141	34	leonardoar
142	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
143			`WRITE (line_out, MemoryDataInput);`
144			`WRITELINE (cmdfile, line_out);`
145
146	34	leonardoar	`-- Verify if signals for the datapath are valid`
147			`assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;`
148			`assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;`
149			`assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;`
150			`assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;`
151
152	33	leonardoar	`wait for CLK_period; -- Executing ... 1`
153
154	34	leonardoar	`-- State writing on the registers`
155			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
156
157			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
158
159			`-- Verify if all lines are unasserted`
160			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
161			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
162			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
163			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
164			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
165			`-------------------------------------------------------------------------------------------------`
166
167	33	leonardoar	`-- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------`
168			`REPORT "MOV r1,20" SEVERITY NOTE;`
169			`MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);`
170			`wait for CLK_period; -- Fetch`
171			`wait for CLK_period; -- Decode`
172			`wait for CLK_period; -- Execute`
173	34	leonardoar
174	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
175			`WRITE (line_out, MemoryDataInput);`
176			`WRITELINE (cmdfile, line_out);`
177
178	34	leonardoar	`-- Verify if signals for the datapath are valid`
179			`assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;`
180			`assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;`
181			`assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;`
182			`assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;`
183
184	33	leonardoar	`wait for CLK_period; -- Executing ... 1`
185	34	leonardoar
186			`-- State writing on the registers`
187			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
188
189			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
190
191			`-- Verify if all lines are unasserted`
192			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
193			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
194			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
195			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
196			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
197			`-------------------------------------------------------------------------------------------------`
198
199			`-- MOV r2,r1 (Compare control unit outputs with Datapath)--------------------------------------`
200			`REPORT "MOV r2,r1" SEVERITY NOTE;`
201			`MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";`
202			`wait for CLK_period; -- Fetch`
203			`wait for CLK_period; -- Decode`
204			`wait for CLK_period; -- Execute`
205
206	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
207			`WRITE (line_out, MemoryDataInput);`
208			`WRITELINE (cmdfile, line_out);`
209
210	34	leonardoar	`-- Verify if signals for the datapath are valid`
211			`assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;`
212			`assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;`
213			`assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;`
214			`assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;`
215			`wait for CLK_period; -- Executing ... 1`
216
217			`-- State writing on the registers`
218			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
219
220			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
221
222			`-- Verify if all lines are unasserted`
223			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
224			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
225			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
226			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
227			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
228			`-------------------------------------------------------------------------------------------------`
229
230			`-- ADD r2,r0 (Compare control unit outputs with Datapath)--------------------------------------`
231			`REPORT "ADD r2,r0" SEVERITY NOTE;`
232			`MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";`
233			`wait for CLK_period; -- Fetch`
234			`wait for CLK_period; -- Decode`
235			`wait for CLK_period; -- Execute`
236
237	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
238			`WRITE (line_out, MemoryDataInput);`
239			`WRITELINE (cmdfile, line_out);`
240
241	34	leonardoar	`-- Verify if signals for the datapath are valid`
242			`assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;`
243			`assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;`
244			`assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;`
245			`assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;`
246			`assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;`
247			`assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;`
248			`assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;`
249			`assert MuxRegDp = muxRegPos(fromRegFileA) report "Invalid value" severity FAILURE;`
250			`wait for CLK_period; -- Executing ... 1`
251
252			`-- State writing on the registers`
253			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
254
255			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
256
257			`-- Verify if all lines are unasserted`
258			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
259			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
260			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
261			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
262			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
263			`-------------------------------------------------------------------------------------------------`
264	35	leonardoar
265			`-- ADD r2,2 (Compare control unit outputs with Datapath)--------------------------------------`
266			`REPORT "ADD r2,2" SEVERITY NOTE;`
267			`MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);`
268			`wait for CLK_period; -- Fetch`
269			`wait for CLK_period; -- Decode`
270			`wait for CLK_period; -- Execute`
271
272	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
273			`WRITE (line_out, MemoryDataInput);`
274			`WRITELINE (cmdfile, line_out);`
275
276	35	leonardoar	`-- Verify if signals for the datapath are valid`
277			`assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;`
278			`assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;`
279			`assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;`
280			`assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;`
281			`assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;`
282			`assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;`
283			`assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;`
284
285			`wait for CLK_period; -- Executing ... 1`
286
287			`-- State writing on the registers`
288			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
289
290			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
291
292			`-- Verify if all lines are unasserted`
293			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
294			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
295			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
296			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
297			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
298			`-------------------------------------------------------------------------------------------------`
299	22	leonardoar
300	40	leonardoar	`-- Close file`
301			`file_close(cmdfile);`
302			`-- Finish simulation`
303	34	leonardoar	`assert false report "NONE. End of simulation." severity failure;`
304			`wait;`
305	22	leonardoar	`end process;`
306
307			`END;`

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