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--! @file
--! @brief Testbench for ControlUnit
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! Adding library for File I/O 
-- More information on this site:
-- http://people.sabanciuniv.edu/erkays/el310/io_10.pdf
-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
use std.textio.ALL;
use ieee.std_logic_textio.all;
 
ENTITY testControlUnit IS
generic (n : integer := nBits - 1);                                                                     --! Generic value (Used to easily change the size of the Alu on the package)
END testControlUnit;
 
--! @brief ControlUnit Testbench file
--! @details Exercise the control unit with a assembly program sample
--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
ARCHITECTURE behavior OF testControlUnit IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ControlUnit
    generic (n : integer := nBits - 1);                                                                 --! Generic value (Used to easily change the size of the Alu on the package)
         Port ( reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;                                                                                         --! Main system clock
           FlagsDp : in  STD_LOGIC_VECTOR (2 downto 0);                          --! Flags comming from the Datapath
           DataDp : in  STD_LOGIC_VECTOR (n downto 0);                           --! Data comming from the Datapath
                          outEnDp : out  typeEnDis;                                                                             --! Enable/Disable datapath output
           MuxDp : out  STD_LOGIC_VECTOR (2 downto 0);                           --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
                          MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0);                           --! Select Alu InputA (Memory,Imediate,RegFileA)
           ImmDp : out  STD_LOGIC_VECTOR (n downto 0);                           --! Imediate value passed to the Datapath
           DpAluOp : out  aluOps;                                                                                       --! Alu operations
                          DpRegFileWriteAddr : out  generalRegisters;                           --! General register address to write
           DpRegFileWriteEn : out  STD_LOGIC;                                                   --! Enable register write
           DpRegFileReadAddrA : out  generalRegisters;                          --! General register address to read
           DpRegFileReadAddrB : out  generalRegisters;                          --! General register address to read
           DpRegFileReadEnA : out  STD_LOGIC;                                                   --! Enable register read (PortA)
           DpRegFileReadEnB : out  STD_LOGIC;                                                   --! Enable register read (PortB)
           MemoryDataReadEn : out std_logic;                                                            --! Enable Main memory read
                          MemoryDataWriteEn: out std_logic;                                                             --! Enable Main memory write
                          MemoryDataInput : in  STD_LOGIC_VECTOR (n downto 0);   --! Incoming data from main memory
           MemoryDataRdAddr : out  STD_LOGIC_VECTOR (n downto 0);        --! Main memory Read address
                          MemoryDataWrAddr : out  STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
           MemoryDataOut : out  STD_LOGIC_VECTOR (n downto 0));  --! Data to write on main memory
    END COMPONENT;
 
 
   --Inputs
   signal reset : std_logic := '0';                                                                                                                      --! Wire to connect Test signal to component
   signal clk : std_logic := '0';                                                                                                                        --! Wire to connect Test signal to component
   signal FlagsDp : std_logic_vector(2 downto 0) := (others => '0');                              --! Wire to connect Test signal to component
   signal DataDp : std_logic_vector(n downto 0) := (others => '0');                               --! Wire to connect Test signal to component
   signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0');      --! Wire to connect Test signal to component
 
        --Outputs
   signal outEnDp : typeEnDis;                                                                                                                          --! Wire to connect Test signal to component
        signal MuxDp : std_logic_vector(2 downto 0);                                                                                     --! Wire to connect Test signal to component
        signal MuxRegDp : std_logic_vector(1 downto 0);                                                                          --! Wire to connect Test signal to component
   signal ImmDp : std_logic_vector(n downto 0);                                                                                  --! Wire to connect Test signal to component
        signal DpAluOp : aluOps;                                                                                                                                        --! Wire to connect Test signal to component
   signal DpRegFileWriteAddr : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileWriteEn : std_logic;                                                                                                 --! Wire to connect Test signal to component
   signal DpRegFileReadAddrA : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileReadAddrB : generalRegisters;                                                                                --! Wire to connect Test signal to component
   signal DpRegFileReadEnA : std_logic;                                                                                                 --! Wire to connect Test signal to component
   signal DpRegFileReadEnB : std_logic;                                                                                                 --! Wire to connect Test signal to component
        signal MemoryDataReadEn : std_logic;                                                                                                    --! Wire to connect Test signal to component
        signal MemoryDataWriteEn : std_logic;                                                                                                   --! Wire to connect Test signal to component
        signal MemoryDataRdAddr : std_logic_vector(n downto 0);                                                  --! Wire to connect Test signal to component
   signal MemoryDataWrAddr : std_logic_vector(n downto 0);                                                       --! Wire to connect Test signal to component
   signal MemoryDataOut : std_logic_vector(n downto 0);                                                          --! Wire to connect Test signal to component
 
   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
        --! Instantiate the Unit Under Test (ControlUnit)
   uut: ControlUnit PORT MAP (
                        reset => reset,
                        clk => clk,
                        FlagsDp => FlagsDp,
                        DataDp => DataDp,
                        outEnDp => outEnDp,
                        MuxDp => MuxDp,
                        MuxRegDp => MuxRegDp,
                        ImmDp => ImmDp,
                        DpAluOp => DpAluOp,
                        DpRegFileWriteAddr => DpRegFileWriteAddr,
                        DpRegFileWriteEn => DpRegFileWriteEn,
                        DpRegFileReadAddrA => DpRegFileReadAddrA,
                        DpRegFileReadAddrB => DpRegFileReadAddrB,
                        DpRegFileReadEnA => DpRegFileReadEnA,
                        DpRegFileReadEnB => DpRegFileReadEnB,
                        MemoryDataReadEn => MemoryDataReadEn,
                        MemoryDataWriteEn => MemoryDataWriteEn,
                        MemoryDataInput => MemoryDataInput,
                        MemoryDataRdAddr => MemoryDataRdAddr,
                        MemoryDataWrAddr => MemoryDataWrAddr,
                        MemoryDataOut => MemoryDataOut
        );
 
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
        variable line_out: Line; -- Line that will be written to a file
        file cmdfile: TEXT;      -- Define the file 'handle'
   begin
                -- Reset operation
                REPORT "RESET" SEVERITY NOTE;
                -- Open source file for write...
                FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",WRITE_MODE);
                reset <= '1';
      wait for 2 ns;
                reset <= '0';
                wait for 2 ns;
 
      -- MOV r0,10d (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r0,10" SEVERITY NOTE;
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid
                assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r1,20" SEVERITY NOTE;
                MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid
                assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
      assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- MOV r2,r1 (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "MOV r2,r1" SEVERITY NOTE;
                MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid         
                assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- ADD r2,r0 (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "ADD r2,r0" SEVERITY NOTE;
                MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid         
                assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
                assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
                assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;
                assert MuxRegDp = muxRegPos(fromRegFileA) report "Invalid value" severity FAILURE;
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
                -- ADD r2,2 (Compare control unit outputs with Datapath)--------------------------------------
                REPORT "ADD r2,2" SEVERITY NOTE;
                MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);
                wait for CLK_period;    -- Fetch
                wait for CLK_period;    -- Decode
                wait for CLK_period;    -- Execute
 
                -- Write the command to a file (This will be usefull for the top Testing later)
                WRITE (line_out, MemoryDataInput);
                WRITELINE (cmdfile, line_out);
 
                -- Verify if signals for the datapath are valid         
                assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
      assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
                assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;
                assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ... 1
 
                -- State writing on the registers
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
                -- Verify if all lines are unasserted
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
 
      -- Close file
                file_close(cmdfile);
                -- Finish simulation
                assert false report "NONE. End of simulation." severity failure;
                wait;
   end process;
 
END;

Line No.	Rev	Author	Line
1	22	leonardoar	`--! @file`
2			`--! @brief Testbench for ControlUnit`
3
4			`--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)`
5			`library IEEE;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.std_logic_unsigned.all;`
8			`use ieee.std_logic_arith.all;`
9
10			`--! Use CPU Definitions package`
11			`use work.pkgOpenCPU32.all;`
12	40	leonardoar
13			`--! Adding library for File I/O`
14			`-- More information on this site:`
15	41	leonardoar	`-- http://people.sabanciuniv.edu/erkays/el310/io_10.pdf`
16	40	leonardoar	`-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm`
17			`use std.textio.ALL;`
18			`use ieee.std_logic_textio.all;`
19	22	leonardoar
20			`ENTITY testControlUnit IS`
21	32	leonardoar	`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
22	22	leonardoar	`END testControlUnit;`
23
24			`--! @brief ControlUnit Testbench file`
25			`--! @details Exercise the control unit with a assembly program sample`
26			`--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html`
27			`ARCHITECTURE behavior OF testControlUnit IS`
28
29			`-- Component Declaration for the Unit Under Test (UUT)`
30
31			`COMPONENT ControlUnit`
32	32	leonardoar	`generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)`
33			`Port ( reset : in STD_LOGIC;`
34			`clk : in STD_LOGIC; --! Main system clock`
35			`FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath`
36			`DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath`
37			`outEnDp : out typeEnDis; --! Enable/Disable datapath output`
38			`MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)`
39			`MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)`
40			`ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath`
41			`DpAluOp : out aluOps; --! Alu operations`
42			`DpRegFileWriteAddr : out generalRegisters; --! General register address to write`
43			`DpRegFileWriteEn : out STD_LOGIC; --! Enable register write`
44			`DpRegFileReadAddrA : out generalRegisters; --! General register address to read`
45			`DpRegFileReadAddrB : out generalRegisters; --! General register address to read`
46			`DpRegFileReadEnA : out STD_LOGIC; --! Enable register read (PortA)`
47			`DpRegFileReadEnB : out STD_LOGIC; --! Enable register read (PortB)`
48			`MemoryDataReadEn : out std_logic; --! Enable Main memory read`
49			`MemoryDataWriteEn: out std_logic; --! Enable Main memory write`
50			`MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0); --! Incoming data from main memory`
51			`MemoryDataRdAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address`
52			`MemoryDataWrAddr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address`
53			`MemoryDataOut : out STD_LOGIC_VECTOR (n downto 0)); --! Data to write on main memory`
54	22	leonardoar	`END COMPONENT;`
55
56
57			`--Inputs`
58			`signal reset : std_logic := '0'; --! Wire to connect Test signal to component`
59			`signal clk : std_logic := '0'; --! Wire to connect Test signal to component`
60	32	leonardoar	`signal FlagsDp : std_logic_vector(2 downto 0) := (others => '0'); --! Wire to connect Test signal to component`
61			`signal DataDp : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component`
62			`signal MemoryDataInput : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component`
63	22	leonardoar
64			`--Outputs`
65	32	leonardoar	`signal outEnDp : typeEnDis; --! Wire to connect Test signal to component`
66			`signal MuxDp : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component`
67			`signal MuxRegDp : std_logic_vector(1 downto 0); --! Wire to connect Test signal to component`
68			`signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
69			`signal DpAluOp : aluOps; --! Wire to connect Test signal to component`
70			`signal DpRegFileWriteAddr : generalRegisters; --! Wire to connect Test signal to component`
71	22	leonardoar	`signal DpRegFileWriteEn : std_logic; --! Wire to connect Test signal to component`
72	32	leonardoar	`signal DpRegFileReadAddrA : generalRegisters; --! Wire to connect Test signal to component`
73			`signal DpRegFileReadAddrB : generalRegisters; --! Wire to connect Test signal to component`
74	22	leonardoar	`signal DpRegFileReadEnA : std_logic; --! Wire to connect Test signal to component`
75			`signal DpRegFileReadEnB : std_logic; --! Wire to connect Test signal to component`
76	32	leonardoar	`signal MemoryDataReadEn : std_logic; --! Wire to connect Test signal to component`
77			`signal MemoryDataWriteEn : std_logic; --! Wire to connect Test signal to component`
78			`signal MemoryDataRdAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
79			`signal MemoryDataWrAddr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
80			`signal MemoryDataOut : std_logic_vector(n downto 0); --! Wire to connect Test signal to component`
81	22	leonardoar
82			`-- Clock period definitions`
83			`constant clk_period : time := 10 ns;`
84
85			`BEGIN`
86
87			`--! Instantiate the Unit Under Test (ControlUnit)`
88	32	leonardoar	`uut: ControlUnit PORT MAP (`
89			`reset => reset,`
90			`clk => clk,`
91			`FlagsDp => FlagsDp,`
92			`DataDp => DataDp,`
93			`outEnDp => outEnDp,`
94			`MuxDp => MuxDp,`
95			`MuxRegDp => MuxRegDp,`
96			`ImmDp => ImmDp,`
97			`DpAluOp => DpAluOp,`
98			`DpRegFileWriteAddr => DpRegFileWriteAddr,`
99			`DpRegFileWriteEn => DpRegFileWriteEn,`
100			`DpRegFileReadAddrA => DpRegFileReadAddrA,`
101			`DpRegFileReadAddrB => DpRegFileReadAddrB,`
102			`DpRegFileReadEnA => DpRegFileReadEnA,`
103			`DpRegFileReadEnB => DpRegFileReadEnB,`
104			`MemoryDataReadEn => MemoryDataReadEn,`
105			`MemoryDataWriteEn => MemoryDataWriteEn,`
106			`MemoryDataInput => MemoryDataInput,`
107			`MemoryDataRdAddr => MemoryDataRdAddr,`
108			`MemoryDataWrAddr => MemoryDataWrAddr,`
109			`MemoryDataOut => MemoryDataOut`
110	22	leonardoar	`);`
111
112			`-- Clock process definitions`
113			`clk_process :process`
114			`begin`
115			`clk <= '0';`
116			`wait for clk_period/2;`
117			`clk <= '1';`
118			`wait for clk_period/2;`
119			`end process;`
120
121
122			`-- Stimulus process`
123			`stim_proc: process`
124	40	leonardoar	`variable line_out: Line; -- Line that will be written to a file`
125			`file cmdfile: TEXT; -- Define the file 'handle'`
126	32	leonardoar	`begin`
127			`-- Reset operation`
128			`REPORT "RESET" SEVERITY NOTE;`
129	40	leonardoar	`-- Open source file for write...`
130			`FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",WRITE_MODE);`
131	32	leonardoar	`reset <= '1';`
132			`wait for 2 ns;`
133			`reset <= '0';`
134			`wait for 2 ns;`
135	22	leonardoar
136	33	leonardoar	`-- MOV r0,10d (Compare control unit outputs with Datapath)--------------------------------------`
137	32	leonardoar	`REPORT "MOV r0,10" SEVERITY NOTE;`
138	40	leonardoar	`MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);`
139	33	leonardoar	`wait for CLK_period; -- Fetch`
140			`wait for CLK_period; -- Decode`
141			`wait for CLK_period; -- Execute`
142	34	leonardoar
143	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
144			`WRITE (line_out, MemoryDataInput);`
145			`WRITELINE (cmdfile, line_out);`
146
147	34	leonardoar	`-- Verify if signals for the datapath are valid`
148			`assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;`
149			`assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;`
150			`assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;`
151			`assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;`
152
153	33	leonardoar	`wait for CLK_period; -- Executing ... 1`
154
155	34	leonardoar	`-- State writing on the registers`
156			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
157
158			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
159
160			`-- Verify if all lines are unasserted`
161			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
162			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
163			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
164			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
165			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
166			`-------------------------------------------------------------------------------------------------`
167
168	33	leonardoar	`-- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------`
169			`REPORT "MOV r1,20" SEVERITY NOTE;`
170			`MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);`
171			`wait for CLK_period; -- Fetch`
172			`wait for CLK_period; -- Decode`
173			`wait for CLK_period; -- Execute`
174	34	leonardoar
175	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
176			`WRITE (line_out, MemoryDataInput);`
177			`WRITELINE (cmdfile, line_out);`
178
179	34	leonardoar	`-- Verify if signals for the datapath are valid`
180			`assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;`
181			`assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;`
182			`assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;`
183			`assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;`
184
185	33	leonardoar	`wait for CLK_period; -- Executing ... 1`
186	34	leonardoar
187			`-- State writing on the registers`
188			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
189
190			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
191
192			`-- Verify if all lines are unasserted`
193			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
194			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
195			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
196			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
197			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
198			`-------------------------------------------------------------------------------------------------`
199
200			`-- MOV r2,r1 (Compare control unit outputs with Datapath)--------------------------------------`
201			`REPORT "MOV r2,r1" SEVERITY NOTE;`
202			`MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";`
203			`wait for CLK_period; -- Fetch`
204			`wait for CLK_period; -- Decode`
205			`wait for CLK_period; -- Execute`
206
207	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
208			`WRITE (line_out, MemoryDataInput);`
209			`WRITELINE (cmdfile, line_out);`
210
211	34	leonardoar	`-- Verify if signals for the datapath are valid`
212			`assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;`
213			`assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;`
214			`assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;`
215			`assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;`
216			`wait for CLK_period; -- Executing ... 1`
217
218			`-- State writing on the registers`
219			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
220
221			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
222
223			`-- Verify if all lines are unasserted`
224			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
225			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
226			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
227			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
228			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
229			`-------------------------------------------------------------------------------------------------`
230
231			`-- ADD r2,r0 (Compare control unit outputs with Datapath)--------------------------------------`
232			`REPORT "ADD r2,r0" SEVERITY NOTE;`
233			`MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";`
234			`wait for CLK_period; -- Fetch`
235			`wait for CLK_period; -- Decode`
236			`wait for CLK_period; -- Execute`
237
238	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
239			`WRITE (line_out, MemoryDataInput);`
240			`WRITELINE (cmdfile, line_out);`
241
242	34	leonardoar	`-- Verify if signals for the datapath are valid`
243			`assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;`
244			`assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;`
245			`assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;`
246			`assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;`
247			`assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;`
248			`assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;`
249			`assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;`
250			`assert MuxRegDp = muxRegPos(fromRegFileA) report "Invalid value" severity FAILURE;`
251			`wait for CLK_period; -- Executing ... 1`
252
253			`-- State writing on the registers`
254			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
255
256			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
257
258			`-- Verify if all lines are unasserted`
259			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
260			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
261			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
262			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
263			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
264			`-------------------------------------------------------------------------------------------------`
265	35	leonardoar
266			`-- ADD r2,2 (Compare control unit outputs with Datapath)--------------------------------------`
267			`REPORT "ADD r2,2" SEVERITY NOTE;`
268			`MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);`
269			`wait for CLK_period; -- Fetch`
270			`wait for CLK_period; -- Decode`
271			`wait for CLK_period; -- Execute`
272
273	40	leonardoar	`-- Write the command to a file (This will be usefull for the top Testing later)`
274			`WRITE (line_out, MemoryDataInput);`
275			`WRITELINE (cmdfile, line_out);`
276
277	35	leonardoar	`-- Verify if signals for the datapath are valid`
278			`assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;`
279			`assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;`
280			`assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;`
281			`assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;`
282			`assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;`
283			`assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;`
284			`assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;`
285
286			`wait for CLK_period; -- Executing ... 1`
287
288			`-- State writing on the registers`
289			`assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;`
290
291			`wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)`
292
293			`-- Verify if all lines are unasserted`
294			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
295			`assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;`
296			`assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;`
297			`assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;`
298			`assert outEnDp = disable report "Invalid value" severity FAILURE;`
299			`-------------------------------------------------------------------------------------------------`
300	22	leonardoar
301	40	leonardoar	`-- Close file`
302			`file_close(cmdfile);`
303			`-- Finish simulation`
304	34	leonardoar	`assert false report "NONE. End of simulation." severity failure;`
305			`wait;`
306	22	leonardoar	`end process;`
307
308			`END;`

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