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[/] [openfire2/] [trunk/] [docs/] [memory-map.txt] - Blame information for rev 8

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Line No. Rev Author Line
1 2 toni32
Hint:
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Address from the code side (if you want to know physical address >> 2)
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Bit ordering:  0=MSB --> 31=LSB
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I/O PORTS
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-------------------------------------------------------------------------------------
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ADDRESS                 READ                            WRITE
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-------------------------------------------------------------------------------------
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SP3SK GPIO: **ATTENTION** USE ALWAYS WORD (32BIT) WRITE DUE TO NOT BYTE SELECT LOGIC
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0x0800_0000             31..24=segments_n               31..24=segments_n
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0x0800_0001(r)          23..20=drivers_n                23..20=drivers_n
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0x0800_0002(r)          19..16=pushbuttons
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0x0800_0003(r)          15.. 8=leds                     15..8 =leds
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                         7.. 0=switches
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UARTS STATUS REGISTER:
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0x0800_0004             24=rx1_data_present
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                        25=rx1_half_full
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                        26=rx1_full
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                        27=tx1_half_full
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                        28=tx1_full
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0x0800_0006              8=rx2_data_present
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                         9=rx2_half_full
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                        10=rx2_full
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                        11=tx2_half_full
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                        12=tx2_full
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UART1_TXRX_DATA:
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0x0800_0008             31..24=read byte                31..24=send byte
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UART2_TXRX_DATA:
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0x0800_000C             31..24=read byte                31..24=send byte
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PROM_READER:
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0x0800_0010             31..24=read current byte
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0x0800_0011             23=requested sync               23=request next sync
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                        22=requested data               22=request next byte
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                        21=prom synced
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                        20=data ready
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TIMER1:
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0x0800_0014             31=running/stopped              31=start/stop
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                        30..0=current value             30..0=max. timer value
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INTERRUPT_ENABLE:
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0x0800_0018                                             31=enable timer1 interrupt
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                                                        30=enable uart1 receive byte interrupt
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                                                        29=enable uart2 receive byte interrupt
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-------------------------------------------------
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MEMORY MAP
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-------------------------------------------------
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0x0000_0000     block ram start (inside fpga)
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0x0000_1fff     block ram end
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0x0000_0000     reset vector
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0x0000_0008     software exception vector (break)
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0x0000_0010     interrupt vector
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0x0000_0018     reserved (breakpoint vector)
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0x0000_0020     hardware exception vector
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0x0400_0000     external sram start
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0x040f_ffff     external sram end
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0x040e_2000     video ram start (inside external sram)
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0x040f_ffff     video ram end (size = 0x1_e000)
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0x0800_0000     i/o space
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0x0800_xxxx
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