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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.03
//  \   \         Filename: kcuart_tx.v
//  /   /         Date Last Modified:  November 2, 2004
// /___/   /\     Date Created: October 14, 2002
// \   \  /  \
//  \___\/\___\
//
//Device:       Xilinx
//Purpose:      
//      Constant (K) Compact UART Transmitter
//Reference:
//      None
//Revision History:
//    Rev 1.00 - kc - Start of design entry in VHDL,  October 14, 2002
//    Rev 1.01 - sus - Converted to verilog,  August 4, 2004
//    Rev 1.02 - njs - Synplicity attributes added,  September 6, 2004
//    Rev 1.03 - njs - Fixed simulation attributes from string to hex, 
//                              November 2, 2004
////////////////////////////////////////////////////////////////////////////////// 
// Contact: e-mail  picoblaze@xilinx.com
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer: 
// LIMITED WARRANTY AND DISCLAIMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement, or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrant or
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits, cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the 
// essential purpose of any limited remedies herein. 
//////////////////////////////////////////////////////////////////////////////////
 
`timescale 1 ps / 1ps
 
module kcuart_tx
     (data_in,
      send_character,
      en_16_x_baud,
      serial_out,
      Tx_complete,
      clk);
 
input   [7:0]    data_in;
input           send_character;
input           en_16_x_baud;
output          serial_out;
output          Tx_complete;
input           clk;
 
//
////////////////////////////////////////////////////////////////////////////////////
//
// Start of KCUART_TX
//       
//
////////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////////
//
// wires used in KCUART_TX
//
////////////////////////////////////////////////////////////////////////////////////
//
wire            data_01;
wire            data_23;
wire            data_45;
wire            data_67;
wire            data_0123;
wire            data_4567;
wire            data_01234567;
wire    [2:0]    bit_select;
wire    [2:0]    next_count;
wire    [2:0]    mask_count;
wire    [2:0]    mask_count_carry;
wire    [2:0]    count_carry;
wire            ready_to_start;
wire            decode_Tx_start;
wire            Tx_start;
wire            decode_Tx_run;
wire            Tx_run;
wire            decode_hot_state;
wire            hot_state;
wire            hot_delay;
wire            Tx_bit;
wire            decode_Tx_stop;
wire            Tx_stop;
wire            decode_Tx_complete;
 
////////////////////////////////////////////////////////////////////////////////////
//
// Start of KCUART_TX circuit description
//
////////////////////////////////////////////////////////////////////////////////////
//      
 
  // 8 to 1 multiplexer to convert parallel data to serial
 
        LUT4 mux1_lut
          ( .I0(bit_select[0]),
            .I1(data_in[0]),
            .I2(data_in[1]),
            .I3(Tx_run),
            .O(data_01) );
 
        defparam mux1_lut.INIT = 16'hE4FF;
 
 
        LUT4 mux2_lut
        (   .I0(bit_select[0]),
            .I1(data_in[2]),
            .I2(data_in[3]),
            .I3(Tx_run),
            .O(data_23) );
 
        defparam mux2_lut.INIT = 16'hE4FF;
 
 
        LUT4 mux3_lut
           (.I0(bit_select[0]),
            .I1(data_in[4]),
            .I2(data_in[5]),
            .I3(Tx_run),
            .O(data_45) );
 
        defparam mux3_lut.INIT = 16'hE4FF;
 
 
        LUT4 mux4_lut
           (.I0(bit_select[0]),
            .I1(data_in[6]),
            .I2(data_in[7]),
            .I3(Tx_run),
            .O(data_67) );
 
        defparam mux4_lut.INIT = 16'hE4FF;
 
 
        MUXF5 mux5_muxf5
                (               .I1(data_23),
            .I0(data_01),
            .S(bit_select[1]),
            .O(data_0123) );
 
        MUXF5 mux6_muxf5
                (               .I1(data_67),
            .I0(data_45),
            .S(bit_select[1]),
            .O(data_4567) );
 
        MUXF6 mux7_muxf6
                (               .I1(data_4567),
            .I0(data_0123),
            .S(bit_select[2]),
            .O(data_01234567) );
 
  // Register serial output and force start and stop bits
 
        FDRS pipeline_serial
        (   .D(data_01234567),
            .Q(serial_out),
            .R(Tx_start),
            .S(Tx_stop),
            .C(clk) ) ;
 
  // 3-bit counter
  // Counter is clock enabled by en_16_x_baud
  // Counter will be reset when 'Tx_start' is active
  // Counter will increment when Tx_bit is active
  // Tx_run must be active to count
  // count_carry[2] indicates when terminal count [7] is reached and Tx_bit=1 (ie overflow)
 
        FDRE register_bit_0
        (.D(next_count[0]),
         .Q(bit_select[0]),
         .CE(en_16_x_baud),
         .R(Tx_start),
         .C(clk) );
 
        LUT2 count_lut_0
        (.I0(bit_select[0]),
         .I1(Tx_run),
         .O(mask_count[0]) );
 
        defparam count_lut_0.INIT = 4'h8;
 
 
   MULT_AND mask_and_0
        (.I0(bit_select[0]),
         .I1(Tx_run),
         .LO(mask_count_carry[0]) );
 
        MUXCY count_muxcy_0
        ( .DI(mask_count_carry[0]),
         .CI(Tx_bit),
         .S(mask_count[0]),
         .O(count_carry[0]) );
 
        XORCY count_xor_0
        (.LI(mask_count[0]),
         .CI(Tx_bit),
         .O(next_count[0]) );
 
        FDRE register_bit_1
        (.D(next_count[1]),
         .Q(bit_select[1]),
         .CE(en_16_x_baud),
         .R(Tx_start),
         .C(clk) );
 
        LUT2 count_lut_1
        (.I0(bit_select[1]),
         .I1(Tx_run),
         .O(mask_count[1]) );
 
        defparam count_lut_1.INIT = 4'h8;
 
 
   MULT_AND mask_and_1
        (       .I0(bit_select[1]),
         .I1(Tx_run),
         .LO(mask_count_carry[1]) );
 
        MUXCY count_muxcy_1
        (       .DI(mask_count_carry[1]),
         .CI(count_carry[0]),
         .S(mask_count[1]),
         .O(count_carry[1]) );
 
        XORCY count_xor_1
        (       .LI(mask_count[1]),
         .CI(count_carry[0]),
         .O(next_count[1]) );
 
        FDRE register_bit_2
        (       .D(next_count[2]),
         .Q(bit_select[2]),
         .CE(en_16_x_baud),
         .R(Tx_start),
         .C(clk) );
 
        LUT2 count_lut_2
        (       .I0(bit_select[2]),
         .I1(Tx_run),
         .O(mask_count[2]) );
 
        defparam count_lut_2.INIT = 4'h8;
 
 
        MULT_AND mask_and_2
        (       .I0(bit_select[2]),
         .I1(Tx_run),
         .LO(mask_count_carry[2]) );
 
 
        MUXCY count_muxcy_2
        (       .DI(mask_count_carry[2]),
         .CI(count_carry[1]),
         .S(mask_count[2]) ,
         .O(count_carry[2]) );
 
        XORCY count_xor_2
                (       .LI(mask_count[2]),
         .CI(count_carry[1]),
         .O(next_count[2]) );
 
  // Ready to start decode
 
        LUT3 ready_lut
                (       .I0(Tx_run),
         .I1(Tx_start),
         .I2(send_character),
         .O(ready_to_start ) );
 
        defparam ready_lut.INIT = 8'h10;
 
 
  // Start bit enable
 
        LUT4 start_lut
                (       .I0(Tx_bit),
         .I1(Tx_stop),
         .I2(ready_to_start),
         .I3(Tx_start),
         .O(decode_Tx_start ) );
 
        defparam start_lut.INIT = 16'h0190;
 
 
        FDE Tx_start_reg
        (       .D(decode_Tx_start),
      .Q(Tx_start),
      .CE(en_16_x_baud),
      .C(clk) );
 
 
  // Run bit enable
        LUT4 run_lut
        (       .I0(count_carry[2]),
      .I1(Tx_bit),
      .I2(Tx_start),
      .I3(Tx_run),
                .O(decode_Tx_run ) );
 
        defparam run_lut.INIT = 16'h1540;
 
 
        FDE Tx_run_reg
        (       .D(decode_Tx_run),
      .Q(Tx_run),
      .CE(en_16_x_baud),
      .C(clk) );
 
  // Bit rate enable
 
        LUT3 hot_state_lut
        (       .I0(Tx_stop),
      .I1(ready_to_start),
      .I2(Tx_bit),
      .O(decode_hot_state) );
 
        defparam hot_state_lut.INIT = 8'h94;
 
 
        FDE hot_state_reg
        (       .D(decode_hot_state),
      .Q(hot_state),
      .CE(en_16_x_baud),
      .C(clk) );
 
        SRL16E delay14_srl
        (       .D(hot_state),
      .CE(en_16_x_baud),
      .CLK(clk),
      .A0(1'b1),
      .A1(1'b0),
      .A2(1'b1),
      .A3(1'b1),
      .Q(hot_delay) );
 
        defparam delay14_srl.INIT = 16'h0000;
 
 
        FDE Tx_bit_reg
        (       .D(hot_delay),
        .Q(Tx_bit),
      .CE(en_16_x_baud),
      .C(clk) );
 
  // Stop bit enable
        LUT4 stop_lut
        (       .I0(Tx_bit),
      .I1(Tx_run),
      .I2(count_carry[2]),
      .I3(Tx_stop),
      .O(decode_Tx_stop) );
 
        defparam stop_lut.INIT = 16'h0180;
 
 
  FDE Tx_stop_reg
  (         .D(decode_Tx_stop),
            .Q(Tx_stop),
            .CE(en_16_x_baud),
            .C(clk) );
 
  // Tx_complete strobe
 
  LUT2 complete_lut
  (         .I0(count_carry[2]),
            .I1(en_16_x_baud),
            .O(decode_Tx_complete) );
 
        defparam complete_lut.INIT = 4'h8;
 
 
  FD Tx_complete_reg
  (          .D(decode_Tx_complete),
             .Q(Tx_complete),
             .C(clk) );
 
 
endmodule
 
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE KCUART_TX.V
//
////////////////////////////////////////////////////////////////////////////////////
 
 

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Subversion Repositories openfire2

[/] [openfire2/] [trunk/] [rtl/] [kcuart_tx.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	3	toni32	`////////////////////////////////////////////////////////////////////////////////`
2			`// Copyright (c) 2004 Xilinx, Inc.`
3			`// All Rights Reserved`
4			`////////////////////////////////////////////////////////////////////////////////`
5			`// ____ ____`
6			`// / /\/ /`
7			`// /___/ \ / Vendor: Xilinx`
8			`// \ \ \/ Version: 1.03`
9			`// \ \ Filename: kcuart_tx.v`
10			`// / / Date Last Modified: November 2, 2004`
11			`// /___/ /\ Date Created: October 14, 2002`
12			`// \ \ / \`
13			`// \___\/\___\`
14			`//`
15			`//Device: Xilinx`
16			`//Purpose:`
17			`// Constant (K) Compact UART Transmitter`
18			`//Reference:`
19			`// None`
20			`//Revision History:`
21			`// Rev 1.00 - kc - Start of design entry in VHDL, October 14, 2002`
22			`// Rev 1.01 - sus - Converted to verilog, August 4, 2004`
23			`// Rev 1.02 - njs - Synplicity attributes added, September 6, 2004`
24			`// Rev 1.03 - njs - Fixed simulation attributes from string to hex,`
25			`// November 2, 2004`
26			`//////////////////////////////////////////////////////////////////////////////////`
27			`// Contact: e-mail picoblaze@xilinx.com`
28			`//////////////////////////////////////////////////////////////////////////////////`
29			`//`
30			`// Disclaimer:`
31			`// LIMITED WARRANTY AND DISCLAIMER. These designs are`
32			`// provided to you "as is". Xilinx and its licensors make and you`
33			`// receive no warranties or conditions, express, implied,`
34			`// statutory or otherwise, and Xilinx specifically disclaims any`
35			`// implied warranties of merchantability, non-infringement, or`
36			`// fitness for a particular purpose. Xilinx does not warrant that`
37			`// the functions contained in these designs will meet your`
38			`// requirements, or that the operation of these designs will be`
39			`// uninterrupted or error free, or that defects in the Designs`
40			`// will be corrected. Furthermore, Xilinx does not warrant or`
41			`// make any representations regarding use or the results of the`
42			`// use of the designs in terms of correctness, accuracy,`
43			`// reliability, or otherwise.`
44			`//`
45			`// LIMITATION OF LIABILITY. In no event will Xilinx or its`
46			`// licensors be liable for any loss of data, lost profits, cost`
47			`// or procurement of substitute goods or services, or for any`
48			`// special, incidental, consequential, or indirect damages`
49			`// arising from the use or operation of the designs or`
50			`// accompanying documentation, however caused and on any theory`
51			`// of liability. This limitation will apply even if Xilinx`
52			`// has been advised of the possibility of such damage. This`
53			`// limitation shall apply not-withstanding the failure of the`
54			`// essential purpose of any limited remedies herein.`
55			`//////////////////////////////////////////////////////////////////////////////////`
56
57			`timescale 1 ps / 1ps
58
59			`module kcuart_tx`
60			`(data_in,`
61			`send_character,`
62			`en_16_x_baud,`
63			`serial_out,`
64			`Tx_complete,`
65			`clk);`
66
67			`input [7:0] data_in;`
68			`input send_character;`
69			`input en_16_x_baud;`
70			`output serial_out;`
71			`output Tx_complete;`
72			`input clk;`
73
74			`//`
75			`////////////////////////////////////////////////////////////////////////////////////`
76			`//`
77			`// Start of KCUART_TX`
78			`//`
79			`//`
80			`////////////////////////////////////////////////////////////////////////////////////`
81			`//`
82			`////////////////////////////////////////////////////////////////////////////////////`
83			`//`
84			`// wires used in KCUART_TX`
85			`//`
86			`////////////////////////////////////////////////////////////////////////////////////`
87			`//`
88			`wire data_01;`
89			`wire data_23;`
90			`wire data_45;`
91			`wire data_67;`
92			`wire data_0123;`
93			`wire data_4567;`
94			`wire data_01234567;`
95			`wire [2:0] bit_select;`
96			`wire [2:0] next_count;`
97			`wire [2:0] mask_count;`
98			`wire [2:0] mask_count_carry;`
99			`wire [2:0] count_carry;`
100			`wire ready_to_start;`
101			`wire decode_Tx_start;`
102			`wire Tx_start;`
103			`wire decode_Tx_run;`
104			`wire Tx_run;`
105			`wire decode_hot_state;`
106			`wire hot_state;`
107			`wire hot_delay;`
108			`wire Tx_bit;`
109			`wire decode_Tx_stop;`
110			`wire Tx_stop;`
111			`wire decode_Tx_complete;`
112
113			`////////////////////////////////////////////////////////////////////////////////////`
114			`//`
115			`// Start of KCUART_TX circuit description`
116			`//`
117			`////////////////////////////////////////////////////////////////////////////////////`
118			`//`
119
120			`// 8 to 1 multiplexer to convert parallel data to serial`
121
122			`LUT4 mux1_lut`
123			`( .I0(bit_select[0]),`
124			`.I1(data_in[0]),`
125			`.I2(data_in[1]),`
126			`.I3(Tx_run),`
127			`.O(data_01) );`
128
129			`defparam mux1_lut.INIT = 16'hE4FF;`
130
131
132			`LUT4 mux2_lut`
133			`( .I0(bit_select[0]),`
134			`.I1(data_in[2]),`
135			`.I2(data_in[3]),`
136			`.I3(Tx_run),`
137			`.O(data_23) );`
138
139			`defparam mux2_lut.INIT = 16'hE4FF;`
140
141
142			`LUT4 mux3_lut`
143			`(.I0(bit_select[0]),`
144			`.I1(data_in[4]),`
145			`.I2(data_in[5]),`
146			`.I3(Tx_run),`
147			`.O(data_45) );`
148
149			`defparam mux3_lut.INIT = 16'hE4FF;`
150
151
152			`LUT4 mux4_lut`
153			`(.I0(bit_select[0]),`
154			`.I1(data_in[6]),`
155			`.I2(data_in[7]),`
156			`.I3(Tx_run),`
157			`.O(data_67) );`
158
159			`defparam mux4_lut.INIT = 16'hE4FF;`
160
161
162			`MUXF5 mux5_muxf5`
163			`( .I1(data_23),`
164			`.I0(data_01),`
165			`.S(bit_select[1]),`
166			`.O(data_0123) );`
167
168			`MUXF5 mux6_muxf5`
169			`( .I1(data_67),`
170			`.I0(data_45),`
171			`.S(bit_select[1]),`
172			`.O(data_4567) );`
173
174			`MUXF6 mux7_muxf6`
175			`( .I1(data_4567),`
176			`.I0(data_0123),`
177			`.S(bit_select[2]),`
178			`.O(data_01234567) );`
179
180			`// Register serial output and force start and stop bits`
181
182			`FDRS pipeline_serial`
183			`( .D(data_01234567),`
184			`.Q(serial_out),`
185			`.R(Tx_start),`
186			`.S(Tx_stop),`
187			`.C(clk) ) ;`
188
189			`// 3-bit counter`
190			`// Counter is clock enabled by en_16_x_baud`
191			`// Counter will be reset when 'Tx_start' is active`
192			`// Counter will increment when Tx_bit is active`
193			`// Tx_run must be active to count`
194			`// count_carry[2] indicates when terminal count [7] is reached and Tx_bit=1 (ie overflow)`
195
196			`FDRE register_bit_0`
197			`(.D(next_count[0]),`
198			`.Q(bit_select[0]),`
199			`.CE(en_16_x_baud),`
200			`.R(Tx_start),`
201			`.C(clk) );`
202
203			`LUT2 count_lut_0`
204			`(.I0(bit_select[0]),`
205			`.I1(Tx_run),`
206			`.O(mask_count[0]) );`
207
208			`defparam count_lut_0.INIT = 4'h8;`
209
210
211			`MULT_AND mask_and_0`
212			`(.I0(bit_select[0]),`
213			`.I1(Tx_run),`
214			`.LO(mask_count_carry[0]) );`
215
216			`MUXCY count_muxcy_0`
217			`( .DI(mask_count_carry[0]),`
218			`.CI(Tx_bit),`
219			`.S(mask_count[0]),`
220			`.O(count_carry[0]) );`
221
222			`XORCY count_xor_0`
223			`(.LI(mask_count[0]),`
224			`.CI(Tx_bit),`
225			`.O(next_count[0]) );`
226
227			`FDRE register_bit_1`
228			`(.D(next_count[1]),`
229			`.Q(bit_select[1]),`
230			`.CE(en_16_x_baud),`
231			`.R(Tx_start),`
232			`.C(clk) );`
233
234			`LUT2 count_lut_1`
235			`(.I0(bit_select[1]),`
236			`.I1(Tx_run),`
237			`.O(mask_count[1]) );`
238
239			`defparam count_lut_1.INIT = 4'h8;`
240
241
242			`MULT_AND mask_and_1`
243			`( .I0(bit_select[1]),`
244			`.I1(Tx_run),`
245			`.LO(mask_count_carry[1]) );`
246
247			`MUXCY count_muxcy_1`
248			`( .DI(mask_count_carry[1]),`
249			`.CI(count_carry[0]),`
250			`.S(mask_count[1]),`
251			`.O(count_carry[1]) );`
252
253			`XORCY count_xor_1`
254			`( .LI(mask_count[1]),`
255			`.CI(count_carry[0]),`
256			`.O(next_count[1]) );`
257
258			`FDRE register_bit_2`
259			`( .D(next_count[2]),`
260			`.Q(bit_select[2]),`
261			`.CE(en_16_x_baud),`
262			`.R(Tx_start),`
263			`.C(clk) );`
264
265			`LUT2 count_lut_2`
266			`( .I0(bit_select[2]),`
267			`.I1(Tx_run),`
268			`.O(mask_count[2]) );`
269
270			`defparam count_lut_2.INIT = 4'h8;`
271
272
273			`MULT_AND mask_and_2`
274			`( .I0(bit_select[2]),`
275			`.I1(Tx_run),`
276			`.LO(mask_count_carry[2]) );`
277
278
279			`MUXCY count_muxcy_2`
280			`( .DI(mask_count_carry[2]),`
281			`.CI(count_carry[1]),`
282			`.S(mask_count[2]) ,`
283			`.O(count_carry[2]) );`
284
285			`XORCY count_xor_2`
286			`( .LI(mask_count[2]),`
287			`.CI(count_carry[1]),`
288			`.O(next_count[2]) );`
289
290			`// Ready to start decode`
291
292			`LUT3 ready_lut`
293			`( .I0(Tx_run),`
294			`.I1(Tx_start),`
295			`.I2(send_character),`
296			`.O(ready_to_start ) );`
297
298			`defparam ready_lut.INIT = 8'h10;`
299
300
301			`// Start bit enable`
302
303			`LUT4 start_lut`
304			`( .I0(Tx_bit),`
305			`.I1(Tx_stop),`
306			`.I2(ready_to_start),`
307			`.I3(Tx_start),`
308			`.O(decode_Tx_start ) );`
309
310			`defparam start_lut.INIT = 16'h0190;`
311
312
313			`FDE Tx_start_reg`
314			`( .D(decode_Tx_start),`
315			`.Q(Tx_start),`
316			`.CE(en_16_x_baud),`
317			`.C(clk) );`
318
319
320			`// Run bit enable`
321			`LUT4 run_lut`
322			`( .I0(count_carry[2]),`
323			`.I1(Tx_bit),`
324			`.I2(Tx_start),`
325			`.I3(Tx_run),`
326			`.O(decode_Tx_run ) );`
327
328			`defparam run_lut.INIT = 16'h1540;`
329
330
331			`FDE Tx_run_reg`
332			`( .D(decode_Tx_run),`
333			`.Q(Tx_run),`
334			`.CE(en_16_x_baud),`
335			`.C(clk) );`
336
337			`// Bit rate enable`
338
339			`LUT3 hot_state_lut`
340			`( .I0(Tx_stop),`
341			`.I1(ready_to_start),`
342			`.I2(Tx_bit),`
343			`.O(decode_hot_state) );`
344
345			`defparam hot_state_lut.INIT = 8'h94;`
346
347
348			`FDE hot_state_reg`
349			`( .D(decode_hot_state),`
350			`.Q(hot_state),`
351			`.CE(en_16_x_baud),`
352			`.C(clk) );`
353
354			`SRL16E delay14_srl`
355			`( .D(hot_state),`
356			`.CE(en_16_x_baud),`
357			`.CLK(clk),`
358			`.A0(1'b1),`
359			`.A1(1'b0),`
360			`.A2(1'b1),`
361			`.A3(1'b1),`
362			`.Q(hot_delay) );`
363
364			`defparam delay14_srl.INIT = 16'h0000;`
365
366
367			`FDE Tx_bit_reg`
368			`( .D(hot_delay),`
369			`.Q(Tx_bit),`
370			`.CE(en_16_x_baud),`
371			`.C(clk) );`
372
373			`// Stop bit enable`
374			`LUT4 stop_lut`
375			`( .I0(Tx_bit),`
376			`.I1(Tx_run),`
377			`.I2(count_carry[2]),`
378			`.I3(Tx_stop),`
379			`.O(decode_Tx_stop) );`
380
381			`defparam stop_lut.INIT = 16'h0180;`
382
383
384			`FDE Tx_stop_reg`
385			`( .D(decode_Tx_stop),`
386			`.Q(Tx_stop),`
387			`.CE(en_16_x_baud),`
388			`.C(clk) );`
389
390			`// Tx_complete strobe`
391
392			`LUT2 complete_lut`
393			`( .I0(count_carry[2]),`
394			`.I1(en_16_x_baud),`
395			`.O(decode_Tx_complete) );`
396
397			`defparam complete_lut.INIT = 4'h8;`
398
399
400			`FD Tx_complete_reg`
401			`( .D(decode_Tx_complete),`
402			`.Q(Tx_complete),`
403			`.C(clk) );`
404
405
406			`endmodule`
407
408			`////////////////////////////////////////////////////////////////////////////////////`
409			`//`
410			`// END OF FILE KCUART_TX.V`
411			`//`
412			`////////////////////////////////////////////////////////////////////////////////////`
413
414