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[/] [openfire2/] [trunk/] [rtl/] [openfire_fetch.v] - Blame information for rev 6

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1 3 toni32
/*      MODULE: openfire_fetch
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        DESCRIPTION: The fetch module interfaces with the instruction memory and
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fetches the next instruction.
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TO DO:
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- Add prefetch buffer
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- Add LMB interface
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AUTHOR:
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Stephen Douglas Craven
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Configurable Computing Lab
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Virginia Tech
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scraven@vt.edu
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REVISION HISTORY:
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Revision 0.2, 8/10/2005 SDC
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Initial release
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Revision 0.3, 12/17/2005 SDC
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Fixed PC size bug
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Revision 0.4  27/03/2007 Antonio J Anton
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Instruction port wait states
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COPYRIGHT:
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Copyright (c) 2005 Stephen Douglas Craven
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE. */
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`include "openfire_define.v"
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module openfire_fetch(
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        stall, clock, reset,                                                                    // top level
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        branch_taken, pc_branch, idata,                                         // inputs
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        instruction, imem_addr, pc_decode, imem_re              // outputs
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);
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// From top level -- all active high unless otherwise noted
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input           stall;
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input           reset;
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input           clock;
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// From EXECUTE module
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input                   branch_taken;   // strobe for latching in new pc
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// PCs are A_SPACE + 1 because lower 2 bits are always zero
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//      A_SPACE is addr space in words ... 2^A_SPACE * 4 = # Bytes
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input   [`A_SPACE+1:0]   pc_branch;      // PC of branch
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// From Instr Mem
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input   [31:0]           idata;
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output  [31:0]           imem_addr;
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output                                  imem_re;
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output  [`A_SPACE+1:0]   pc_decode;
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output  [31:0]           instruction;
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reg     [`A_SPACE+1:0]   pc_fetch;       // PCs only need to contain addressable instr mem
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reg     [`A_SPACE+1:0]   pc_decode;      // delayed PC for DECODE
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reg     [31:0]                   instruction;
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reg                                             imem_re;
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assign imem_addr[31:`A_SPACE+2] = 0;     // pad unused bits with zeros, 
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assign imem_addr[`A_SPACE+1:0]  = pc_fetch;
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always@(posedge clock)
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begin
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        if (reset)
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        begin
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                pc_fetch         <= `RESET_PC_ADDRESS;
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                pc_decode        <= `RESET_PC_ADDRESS;
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                imem_re          <= 1;
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                instruction  <= `NoOp;          // Execute NoOp on reset
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        end
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        else
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        begin                                                                   // update PC to branch or increment pc (if stall --> pc on hold)
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                if(!stall)
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                begin
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                  pc_fetch        <= branch_taken ? pc_branch : pc_fetch + 4;
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                  pc_decode   <= pc_fetch;
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                  instruction <= idata;
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`ifdef DEBUG_FETCH
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                  $display("FETCH : pc_fetch=%x, pc_decode=%x, instruction=%x", pc_fetch, pc_decode, instruction);
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`endif
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                end
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                imem_re <= !stall;
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        end
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end
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endmodule

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