URL https://opencores.org/ocsvn/openfire2/openfire2/trunk

Subversion Repositories openfire2

[/] [openfire2/] [trunk/] [rtl/] [openfire_iospace.v] - Blame information for rev 6

Details | Compare with Previous | View Log


/*      MODULE: openfire vga
        DESCRIPTION: I/O space and peripherals instantiation
 
AUTHOR:
Antonio J. Anton
Anro Ingenieros (www.anro-ingenieros.com)
aj@anro-ingenieros.com
 
REVISION HISTORY:
Revision 1.0, 26/03/2007
Initial release
 
COPYRIGHT:
Copyright (c) 2007 Antonio J. Anton
 
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
 
`timescale 1ns / 1ps
`include "openfire_define.v"
 
module openfire_iospace(
`ifdef SP3SK_USERIO
        leds, drivers_n, segments_n, pushbuttons, switches,
`endif
`ifdef UART1_ENABLE
        tx1, rx1,
`endif
`ifdef UART2_ENABLE
        tx2, rx2,
`endif
`ifdef SP3SK_PROM_DATA
        prom_din, prom_cclk, prom_reset_n,
`endif
`ifdef IO_MULTICYCLE
        done,
`endif
`ifdef ENABLE_INTERRUPTS
    interrupt,
`endif
        clk,  rst, read, write,
        addr, data_in, data_out
);
 
input                           clk;
input                           rst;
input                           read;                           // iospace read requesst
input                           write;                  // iospace write request
`ifdef IO_MULTICYCLE
output                  done;                           // iospace operation completed
`endif
input    [`IO_SIZE-1:0] addr;    // address of operation
input  [31:0]  data_in;                  // data from cpu
output [31:0]  data_out;         // data to cpu
`ifdef SP3SK_USERIO
output [7:0]     leds;                           // LEDS (1=on)
output [3:0]     drivers_n;              // 7SEG driver (negated)
output [7:0]     segments_n;             // segments (negated)
input    [3:0]   pushbuttons;    // 4 pushbuttons (  pushbuttons[3] = reset)
input    [7:0]   switches;               // 8 switches
`endif
`ifdef UART1_ENABLE
output                  tx1;                            // transmit #1
input                           rx1;                            // receive #1
`endif
`ifdef UART2_ENABLE
output                  tx2;                            // transmit #2
input                           rx2;                            // receive #2
`endif
`ifdef SP3SK_PROM_DATA
input                   prom_din;               // data in from PROM
output             prom_cclk;           // clock to PROM
output                  prom_reset_n;   // reset to PROM
`endif
`ifdef ENABLE_INTERRUPTS
output             interrupt;           // interrupt line to cpu
`endif
 
// ---- handle multicycle i/o operations ----
`ifdef IO_MULTICYCLE
assign ready = 1;
`endif
 
// --------------- UARTS -----------------
`ifdef UART1_ENABLE                                     // assure that baudrate generator is
        `define UART_BAUDRATEGEN_ENABLE // instantiated if a uart is in use
`endif
`ifdef UART2_ENABLE
        `define UART_BAUDRATEGEN_ENABLE
`endif
 
`ifdef UART_BAUDRATEGEN_ENABLE
reg     [4:0]    baud_count;                     // counter for a tick generator each 16 clocks
reg                             en_16_x_baud;           // tick signal every 16 clocks --> baud generator
`endif
 
`ifdef UART1_ENABLE
wire                    write_to_uart;          // write byte into send FIFO
wire                    tx_full;                                // TX FIFO is full
wire                    tx_half_full;           // TX FIFO is 1/2 full
reg                             read_from_uart; // read byte from receive FIFO
wire    [7:0]    rx_data;                                // recieved data
wire                    rx_data_present;        // RX FIFO has data
wire                    rx_full;                                // RX FIFO is full
wire                    rx_half_full;           // RX FIFO 1/2 full
`endif
 
`ifdef UART2_ENABLE
wire                    write_to_uart2; // indica que hay que meter en la TX FIFO un byte
wire                    tx2_full;                       // indica que la TX FIFO esta llena
wire                    tx2_half_full;          // indica que la TX FIFO esta 1/2 llena
reg                             read_from_uart2;        // obtener en rx_data un byte de la RX FIFO
wire    [7:0]    rx2_data;                       // donde esta el byte recibido
wire                    rx2_data_present;       // indica que hay datos en RX FIFO
wire                    rx2_full;                       // RX FIFO llena
wire                    rx2_half_full;          // RX FIFO 1/2 llena
`endif
 
//---------- baud rate generator -------------
// Set baud rate to 9600 for the UART communications     DIV=CLK/(16*BAUDRATE)
// Requires en_16_x_baud to be 153600Hz which is a single cycle pulse every 325 cycles at 50MHz 
// NOTE : If the highest value for baud_count exceeds 127 you will need to adjust 
//        the width in the reg declaration for baud_count.
`ifdef UART_BAUDRATEGEN_ENABLE
always @(posedge clk)
begin
 if (baud_count == `BAUD_COUNT)
        begin
      baud_count <= 1'b0;
      en_16_x_baud <= 1'b1;
        end
 else
        begin
                baud_count <= baud_count + 1;
                en_16_x_baud <= 1'b0;
 end
end
`endif
 
// -------- UART #1  ------------
// Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
// Each contains an embedded 16-byte FIFO buffer.
 
`ifdef UART1_ENABLE                                                     // hack to enable status register
        `define UART_STATUS_REG                                 // if at least one uart is present
`endif
`ifdef UART2_ENABLE
        `define UART_STATUS_REG
`endif
 
`ifdef UART1_ENABLE
uart_tx transmit(
                .data_in(data_in[31:24]),                       // 8 bits bajos del registro = dato a enviar
        .write_buffer(write_to_uart),           // 
        .reset_buffer(rst),
        .en_16_x_baud(en_16_x_baud),
        .serial_out(tx1),
        .buffer_full(tx_full),
        .buffer_half_full(tx_half_full),
        .clk(clk)
);
 
uart_rx receive(
                .serial_in(rx1),
        .data_out(rx_data),
        .read_buffer(read_from_uart),
        .reset_buffer(rst),
        .en_16_x_baud(en_16_x_baud),
        .buffer_data_present(rx_data_present),
        .buffer_full(rx_full),
        .buffer_half_full(rx_half_full),
        .clk(clk)
);
`endif
 
// -------- UART #2  ------------
// Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
// Each contains an embedded 16-byte FIFO buffer.
`ifdef UART2_ENABLE
uart_tx transmit2(
                .data_in(data_out[31:24]),                      // 8 bits bajos del registro = dato a enviar
        .write_buffer(write_to_uart2),  // 
        .reset_buffer(rst),
        .en_16_x_baud(en_16_x_baud),
        .serial_out(tx2),
        .buffer_full(tx2_full),
        .buffer_half_full(tx2_half_full),
        .clk(clk)
);
 
uart_rx receive2(
                .serial_in(rx2),
        .data_out(rx2_data),
        .read_buffer(read_from_uart2),
        .reset_buffer(rst),
        .en_16_x_baud(en_16_x_baud),
        .buffer_data_present(rx2_data_present),
        .buffer_full(rx2_full),
        .buffer_half_full(rx2_half_full),
        .clk(clk)
);
`endif
 
// ----- SP3 STARTER KIT USER PORTS : LEDS, 7SEG DISPLAY, SWITCHES & PUSHBUTTONS ----
`ifdef SP3SK_USERIO
reg  [7:0]       leds;                           // 8 leds
reg  [3:0]       drivers_n;              // 4 drivers
reg  [7:0]       segments_n;             // 8 segments
`endif
 
// ----- SP3 STARTER KIT PLATFORM FLASH ------------
`ifdef SP3SK_PROM_DATA
reg                             prom_read;                      // signal the prom_reader to read next byte
reg                             prom_next_sync; // signal the prom_reader to seek next file
wire                            prom_synced;            // notify prom is at the start of a file
wire                            prom_dataready; // notify prom has readed a byte
wire    [7:0]            prom_dataout;           // data readed from prom
 
PROM_reader_serial prom_file(
        .clock(clk),
        .reset(rst),
        .din(prom_din),
        .cclk(prom_cclk),
        .reset_prom_n(prom_reset_n),
        .read(prom_read),
        .next_sync(prom_next_sync),
        .sync(prom_synced),
        .data_ready(prom_dataready),
        .dout(prom_dataout),
        .sync_pattern(`PROM_SYNC_PATTERN)
);
`endif
 
// -------- TIMER #1 GENERATOR (31 bits) -----------
`ifdef TIMER1_GENERATOR
reg   [30:0]     max_timer1_count;       // 32 bit max-timer value
reg     [30:0]   timer1_count;           // current value of the counter
reg                             timer1_pulse;           // positive pulse generated when max_timer1_count is reached
reg                             timer1_running; // indicates if timer is running/stopped
 
always @(posedge clk)
begin
      if(rst | ~timer1_running)         // rst or not running --> restart timer
                begin
                  timer1_count  <= 0;
                  timer1_pulse <= 0;
                end
                else if (timer1_count == max_timer1_count)      // if max_timer1 reached --> generate 1 clock pulse
                begin
                timer1_count <= 1'b0;
                timer1_pulse <= 1'b1;
//synthesis translate_off
                                $display("TIMER1 TRIGGERED (max_timer1_count=0x%x)", max_timer1_count);
//synthesis translate_on
                end
      else
                begin
                timer1_count <= timer1_count + 1;
                timer1_pulse <= 1'b0;
                end
end
`endif
 
// ------- interrupt controller ---------
`ifdef ENABLE_INTERRUPTS
reg [31:0]               device_interrupt;                                       // enable interrupt for specific device
 
wire                            interrupt =                                             // interrupt line is an OR MASK of devices
`ifdef TIMER1_GENERATOR
                                                                (device_interrupt[0] & timer1_pulse) |                   // timer1 can generate interrupt
`endif
`ifdef UART1_ENABLE
                                                                (device_interrupt[1] & rx_data_present) |               // uart1 rx data present
`endif
`ifdef UART2_ENABLE
                                                                (device_interrupt[2] & rx2_data_present) |      // uart2 rx data present
`endif
                                                                0;
`endif
 
// --------------- decode output port (data to device) ----------------
always @(posedge clk)
begin
  if(rst)
  begin                                                 // initialize devices on reset
`ifdef SP3SK_USERIO
        segments_n                      <= 8'hFF;       // 7 segment display off
        drivers_n                       <= 4'hF;
        leds                                    <= 8'h00;       // leds off
`endif
`ifdef SP3SK_PROM_DATA
        prom_next_sync  <= 1'b0;                // no prom activity
        prom_read                       <= 1'b0;
`endif
`ifdef TIMER1_GENERATOR
        max_timer1_count        <= 0;                    // timer1 stopped
        timer1_running          <= 1'b0;
`endif
`ifdef ENABLE_INTERRUPTS
        device_interrupt        <= 0;                    // no interrupts
`endif
  end
  else if(write)                                // write to an output port
  begin
         case( addr[`IO_SIZE-1:0] )
`ifdef SP3SK_USERIO
                `ADDR_SP3_IO    : begin
                                                                segments_n      <= data_in[31:24];      // LSByte is the high bits
                                                                drivers_n       <= data_in[23:20];
                                                                leds                    <= data_in[15:8];
                                                          end
`endif
`ifdef UART1_ENABLE
           `ADDR_UART1          : $display("UART1 WRITE: <%c>", data_in[31:24]);
`endif
`ifdef UART2_ENABLE
           `ADDR_UART2          : $display("UART2 WRITE: <%c>", data_in[31:24]);
`endif
`ifdef SP3SK_PROM_DATA
                `ADDR_PROM     : begin
                                                                prom_next_sync <= data_in[23];
                                                           prom_read            <= data_in[22];
                                                     end
`endif
`ifdef TIMER1_GENERATOR
                `ADDR_TIMER1   : begin
                                                           max_timer1_count  <= data_in[30:0];
                                                                timer1_running     <= data_in[31];
//synthesis translate_off
                                                                if(data_in[31] == 0) $display("TIMER1 STOP");
                                                                else $display("TIMER1 START (max_timer1_count=0x%x)", data_in[30:0]);
//synthesis translate_on
                                                          end
`endif
`ifdef ENABLE_INTERRUPTS
                `ADDR_INT               : device_interrupt <= data_in;
`endif
      default        : $display("Error: Output port not valid: ", addr[`IO_SIZE-1:0]);
    endcase
  end
end
 
// write to UART transmitter FIFO buffer at address 01 hex.
// This is a combinatorial decode because the FIFO is the 'port register'.
`ifdef UART1_ENABLE
wire   uart1_selected = addr[`IO_SIZE-1:0] == `ADDR_UART1;
assign write_to_uart  = write & uart1_selected;
`endif
`ifdef UART2_ENABLE
wire     uart2_selected = addr[`IO_SIZE-1:0] == `ADDR_UART2;
assign write_to_uart2 = write & uart2_selected;
`endif
 
// --------------- decode input port (data to cpu) ----------------
reg [31:0] data_out;                                     // register to store data from an input port
//synthesis translate_off
initial data_out <= 0;
//synthesis translate_on
 
always @(posedge clk)
begin
  if(read)                              // request an input port
  begin
         case( addr[`IO_SIZE-1:0] )
`ifdef SP3SK_USERIO
                `ADDR_SP3_IO    : begin
                                                           data_out[31:24]      <= segments_n;          // LSByte is the high bits
                                                                data_out[23:20] <= drivers_n;
                                                                data_out[19:16] <= pushbuttons;
                                                                data_out[15:8]          <= leds;
                                                                data_out[7:0]            <= switches;
                                                          end
`endif
`ifdef UART_STATUS_REG
                `ADDR_UARTS             : begin                 // depending which uarts are enabled, fill the status register
  `ifdef UART1_ENABLE
                                                                data_out[28:24] <= { tx_full, tx_half_full, rx_full, rx_half_full, rx_data_present };
                                                                $display("UART-STATUS : rx1_data_present=%d, rx1_half_full=%d, rx1_full=%d, tx1_half_full=%d, tx1_full=%d",  rx_data_present, rx_half_full, rx_full, tx_half_full, tx_full);
  `endif
  `ifdef UART2_ENABLE
                                                                data_out[12:8] <= { tx2_full, tx2_half_full, rx2_full, rx2_half_full, rx2_data_present };
                                                                $display("UART-STATUS : rx2_data_present=%d, rx2_half_full=%d, rx2_full=%d, tx2_half_full=%d, tx2_full=%d",  rx2_data_present, rx2_half_full, rx2_full, tx2_half_full, tx2_full);
        `endif
                                                          end
`endif
`ifdef UART1_ENABLE
                `ADDR_UART1    : begin                                                          // receive data UART1
                                                                data_out[31:24] <= rx_data;
                                                                $display("UART1 READ: %c", rx_data);
                                                          end
`endif
`ifdef UART2_ENABLE
                `ADDR_UART2    : begin                                                          // receive data UART2
                                                                data_out[31:24] <= rx_data2;
                                                                $display("UART2 READ: %c", rx_data2);
                                                     end
`endif
`ifdef SP3SK_PROM_DATA
                `ADDR_PROM     : begin
                                                                data_out[31:24] <= prom_dataout;                // data from PROM (only valid if prom_dataready)
                                                                data_out[23]     <= prom_next_sync;     // actual register
                                                                data_out[22]     <= prom_read;                  // register
                                                                data_out[21]     <= prom_synced;                // prom is synced?
                                                                data_out[20]     <= prom_dataready;     // data is ready?
                                                     end
`endif
`ifdef TIMER1_GENERATOR
                `ADDR_TIMER1   : begin
                                                           data_out[30:0]         <= timer1_count;
                                                           data_out[31]    <= timer1_running;
//synthesis translate_off
                                                                if(timer1_running == 0) $display("TIMER1 STOPPED");
                                                                else $display("TIMER1 RUNNING (count=0x%x)", timer1_count);
//synthesis translate_on
                                                          end
`endif
`ifdef ENABLE_INTERRUPTS
                `ADDR_INT               : data_out <= device_interrupt;
`endif
      default        : $display("Error: Input port not valid: ", addr[`IO_SIZE-1:0]);
    endcase
  end
  // Form read strobe for UART receiver FIFO buffer.
  // The fact that the read strobe will occur after the actual data is read by 
  // the CPU is acceptable because it is really means 'I have read you'!
`ifdef UART1_ENABLE
  read_from_uart  <= read & uart1_selected;     // strobe para dato leido desde uart #1
`endif
`ifdef UART2_ENABLE
  read_from_uart2 <= read & uart2_selected;     // strobe para dato leido desde uart #2
`endif
end
 
endmodule

Browse

Tools

Subversion Repositories openfire2

[/] [openfire2/] [trunk/] [rtl/] [openfire_iospace.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	3	toni32	`/* MODULE: openfire vga`
2			`DESCRIPTION: I/O space and peripherals instantiation`
3
4			`AUTHOR:`
5			`Antonio J. Anton`
6			`Anro Ingenieros (www.anro-ingenieros.com)`
7			`aj@anro-ingenieros.com`
8
9			`REVISION HISTORY:`
10			`Revision 1.0, 26/03/2007`
11			`Initial release`
12
13			`COPYRIGHT:`
14			`Copyright (c) 2007 Antonio J. Anton`
15
16			`Permission is hereby granted, free of charge, to any person obtaining a copy of`
17			`this software and associated documentation files (the "Software"), to deal in`
18			`the Software without restriction, including without limitation the rights to`
19			`use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies`
20			`of the Software, and to permit persons to whom the Software is furnished to do`
21			`so, subject to the following conditions:`
22
23			`The above copyright notice and this permission notice shall be included in all`
24			`copies or substantial portions of the Software.`
25
26			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
27			`IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
28			`FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
29			`AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
30			`LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
31			`OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
32			`SOFTWARE.*/`
33
34			`timescale 1ns / 1ps
35			`include "openfire_define.v"
36
37			`module openfire_iospace(`
38			`ifdef SP3SK_USERIO
39			`leds, drivers_n, segments_n, pushbuttons, switches,`
40			`endif
41			`ifdef UART1_ENABLE
42			`tx1, rx1,`
43			`endif
44			`ifdef UART2_ENABLE
45			`tx2, rx2,`
46			`endif
47			`ifdef SP3SK_PROM_DATA
48			`prom_din, prom_cclk, prom_reset_n,`
49			`endif
50			`ifdef IO_MULTICYCLE
51			`done,`
52			`endif
53			`ifdef ENABLE_INTERRUPTS
54			`interrupt,`
55			`endif
56			`clk, rst, read, write,`
57			`addr, data_in, data_out`
58			`);`
59
60			`input clk;`
61			`input rst;`
62			`input read; // iospace read requesst`
63			`input write; // iospace write request`
64			`ifdef IO_MULTICYCLE
65			`output done; // iospace operation completed`
66			`endif
67			input [`IO_SIZE-1:0] addr; // address of operation
68			`input [31:0] data_in; // data from cpu`
69			`output [31:0] data_out; // data to cpu`
70			`ifdef SP3SK_USERIO
71			`output [7:0] leds; // LEDS (1=on)`
72			`output [3:0] drivers_n; // 7SEG driver (negated)`
73			`output [7:0] segments_n; // segments (negated)`
74			`input [3:0] pushbuttons; // 4 pushbuttons ( pushbuttons[3] = reset)`
75			`input [7:0] switches; // 8 switches`
76			`endif
77			`ifdef UART1_ENABLE
78			`output tx1; // transmit #1`
79			`input rx1; // receive #1`
80			`endif
81			`ifdef UART2_ENABLE
82			`output tx2; // transmit #2`
83			`input rx2; // receive #2`
84			`endif
85			`ifdef SP3SK_PROM_DATA
86			`input prom_din; // data in from PROM`
87			`output prom_cclk; // clock to PROM`
88			`output prom_reset_n; // reset to PROM`
89			`endif
90			`ifdef ENABLE_INTERRUPTS
91			`output interrupt; // interrupt line to cpu`
92			`endif
93
94			`// ---- handle multicycle i/o operations ----`
95			`ifdef IO_MULTICYCLE
96			`assign ready = 1;`
97			`endif
98
99			`// --------------- UARTS -----------------`
100			`ifdef UART1_ENABLE // assure that baudrate generator is
101			`define UART_BAUDRATEGEN_ENABLE // instantiated if a uart is in use
102			`endif
103			`ifdef UART2_ENABLE
104			`define UART_BAUDRATEGEN_ENABLE
105			`endif
106
107			`ifdef UART_BAUDRATEGEN_ENABLE
108			`reg [4:0] baud_count; // counter for a tick generator each 16 clocks`
109			`reg en_16_x_baud; // tick signal every 16 clocks --> baud generator`
110			`endif
111
112			`ifdef UART1_ENABLE
113			`wire write_to_uart; // write byte into send FIFO`
114			`wire tx_full; // TX FIFO is full`
115			`wire tx_half_full; // TX FIFO is 1/2 full`
116			`reg read_from_uart; // read byte from receive FIFO`
117			`wire [7:0] rx_data; // recieved data`
118			`wire rx_data_present; // RX FIFO has data`
119			`wire rx_full; // RX FIFO is full`
120			`wire rx_half_full; // RX FIFO 1/2 full`
121			`endif
122
123			`ifdef UART2_ENABLE
124			`wire write_to_uart2; // indica que hay que meter en la TX FIFO un byte`
125			`wire tx2_full; // indica que la TX FIFO esta llena`
126			`wire tx2_half_full; // indica que la TX FIFO esta 1/2 llena`
127			`reg read_from_uart2; // obtener en rx_data un byte de la RX FIFO`
128			`wire [7:0] rx2_data; // donde esta el byte recibido`
129			`wire rx2_data_present; // indica que hay datos en RX FIFO`
130			`wire rx2_full; // RX FIFO llena`
131			`wire rx2_half_full; // RX FIFO 1/2 llena`
132			`endif
133
134			`//---------- baud rate generator -------------`
135			`// Set baud rate to 9600 for the UART communications DIV=CLK/(16*BAUDRATE)`
136			`// Requires en_16_x_baud to be 153600Hz which is a single cycle pulse every 325 cycles at 50MHz`
137			`// NOTE : If the highest value for baud_count exceeds 127 you will need to adjust`
138			`// the width in the reg declaration for baud_count.`
139			`ifdef UART_BAUDRATEGEN_ENABLE
140			`always @(posedge clk)`
141			`begin`
142			if (baud_count == `BAUD_COUNT)
143			`begin`
144			`baud_count <= 1'b0;`
145			`en_16_x_baud <= 1'b1;`
146			`end`
147			`else`
148			`begin`
149			`baud_count <= baud_count + 1;`
150			`en_16_x_baud <= 1'b0;`
151			`end`
152			`end`
153			`endif
154
155			`// -------- UART #1 ------------`
156			`// Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.`
157			`// Each contains an embedded 16-byte FIFO buffer.`
158
159			`ifdef UART1_ENABLE // hack to enable status register
160			`define UART_STATUS_REG // if at least one uart is present
161			`endif
162			`ifdef UART2_ENABLE
163			`define UART_STATUS_REG
164			`endif
165
166			`ifdef UART1_ENABLE
167			`uart_tx transmit(`
168			`.data_in(data_in[31:24]), // 8 bits bajos del registro = dato a enviar`
169			`.write_buffer(write_to_uart), //`
170			`.reset_buffer(rst),`
171			`.en_16_x_baud(en_16_x_baud),`
172			`.serial_out(tx1),`
173			`.buffer_full(tx_full),`
174			`.buffer_half_full(tx_half_full),`
175			`.clk(clk)`
176			`);`
177
178			`uart_rx receive(`
179			`.serial_in(rx1),`
180			`.data_out(rx_data),`
181			`.read_buffer(read_from_uart),`
182			`.reset_buffer(rst),`
183			`.en_16_x_baud(en_16_x_baud),`
184			`.buffer_data_present(rx_data_present),`
185			`.buffer_full(rx_full),`
186			`.buffer_half_full(rx_half_full),`
187			`.clk(clk)`
188			`);`
189			`endif
190
191			`// -------- UART #2 ------------`
192			`// Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.`
193			`// Each contains an embedded 16-byte FIFO buffer.`
194			`ifdef UART2_ENABLE
195			`uart_tx transmit2(`
196			`.data_in(data_out[31:24]), // 8 bits bajos del registro = dato a enviar`
197			`.write_buffer(write_to_uart2), //`
198			`.reset_buffer(rst),`
199			`.en_16_x_baud(en_16_x_baud),`
200			`.serial_out(tx2),`
201			`.buffer_full(tx2_full),`
202			`.buffer_half_full(tx2_half_full),`
203			`.clk(clk)`
204			`);`
205
206			`uart_rx receive2(`
207			`.serial_in(rx2),`
208			`.data_out(rx2_data),`
209			`.read_buffer(read_from_uart2),`
210			`.reset_buffer(rst),`
211			`.en_16_x_baud(en_16_x_baud),`
212			`.buffer_data_present(rx2_data_present),`
213			`.buffer_full(rx2_full),`
214			`.buffer_half_full(rx2_half_full),`
215			`.clk(clk)`
216			`);`
217			`endif
218
219			`// ----- SP3 STARTER KIT USER PORTS : LEDS, 7SEG DISPLAY, SWITCHES & PUSHBUTTONS ----`
220			`ifdef SP3SK_USERIO
221			`reg [7:0] leds; // 8 leds`
222			`reg [3:0] drivers_n; // 4 drivers`
223			`reg [7:0] segments_n; // 8 segments`
224			`endif
225
226			`// ----- SP3 STARTER KIT PLATFORM FLASH ------------`
227			`ifdef SP3SK_PROM_DATA
228			`reg prom_read; // signal the prom_reader to read next byte`
229			`reg prom_next_sync; // signal the prom_reader to seek next file`
230			`wire prom_synced; // notify prom is at the start of a file`
231			`wire prom_dataready; // notify prom has readed a byte`
232			`wire [7:0] prom_dataout; // data readed from prom`
233
234			`PROM_reader_serial prom_file(`
235			`.clock(clk),`
236			`.reset(rst),`
237			`.din(prom_din),`
238			`.cclk(prom_cclk),`
239			`.reset_prom_n(prom_reset_n),`
240			`.read(prom_read),`
241			`.next_sync(prom_next_sync),`
242			`.sync(prom_synced),`
243			`.data_ready(prom_dataready),`
244			`.dout(prom_dataout),`
245			.sync_pattern(`PROM_SYNC_PATTERN)
246			`);`
247			`endif
248
249			`// -------- TIMER #1 GENERATOR (31 bits) -----------`
250			`ifdef TIMER1_GENERATOR
251			`reg [30:0] max_timer1_count; // 32 bit max-timer value`
252			`reg [30:0] timer1_count; // current value of the counter`
253			`reg timer1_pulse; // positive pulse generated when max_timer1_count is reached`
254			`reg timer1_running; // indicates if timer is running/stopped`
255
256			`always @(posedge clk)`
257			`begin`
258			`if(rst \| ~timer1_running) // rst or not running --> restart timer`
259			`begin`
260			`timer1_count <= 0;`
261			`timer1_pulse <= 0;`
262			`end`
263			`else if (timer1_count == max_timer1_count) // if max_timer1 reached --> generate 1 clock pulse`
264			`begin`
265			`timer1_count <= 1'b0;`
266			`timer1_pulse <= 1'b1;`
267			`//synthesis translate_off`
268			`$display("TIMER1 TRIGGERED (max_timer1_count=0x%x)", max_timer1_count);`
269			`//synthesis translate_on`
270			`end`
271			`else`
272			`begin`
273			`timer1_count <= timer1_count + 1;`
274			`timer1_pulse <= 1'b0;`
275			`end`
276			`end`
277			`endif
278
279			`// ------- interrupt controller ---------`
280			`ifdef ENABLE_INTERRUPTS
281			`reg [31:0] device_interrupt; // enable interrupt for specific device`
282
283			`wire interrupt = // interrupt line is an OR MASK of devices`
284			`ifdef TIMER1_GENERATOR
285			`(device_interrupt[0] & timer1_pulse) \| // timer1 can generate interrupt`
286			`endif
287			`ifdef UART1_ENABLE
288			`(device_interrupt[1] & rx_data_present) \| // uart1 rx data present`
289			`endif
290			`ifdef UART2_ENABLE
291			`(device_interrupt[2] & rx2_data_present) \| // uart2 rx data present`
292			`endif
293			`0;`
294			`endif
295
296			`// --------------- decode output port (data to device) ----------------`
297			`always @(posedge clk)`
298			`begin`
299			`if(rst)`
300			`begin // initialize devices on reset`
301			`ifdef SP3SK_USERIO
302			`segments_n <= 8'hFF; // 7 segment display off`
303			`drivers_n <= 4'hF;`
304			`leds <= 8'h00; // leds off`
305			`endif
306			`ifdef SP3SK_PROM_DATA
307			`prom_next_sync <= 1'b0; // no prom activity`
308			`prom_read <= 1'b0;`
309			`endif
310			`ifdef TIMER1_GENERATOR
311			`max_timer1_count <= 0; // timer1 stopped`
312			`timer1_running <= 1'b0;`
313			`endif
314			`ifdef ENABLE_INTERRUPTS
315			`device_interrupt <= 0; // no interrupts`
316			`endif
317			`end`
318			`else if(write) // write to an output port`
319			`begin`
320			case( addr[`IO_SIZE-1:0] )
321			`ifdef SP3SK_USERIO
322			`ADDR_SP3_IO : begin
323			`segments_n <= data_in[31:24]; // LSByte is the high bits`
324			`drivers_n <= data_in[23:20];`
325			`leds <= data_in[15:8];`
326			`end`
327			`endif
328			`ifdef UART1_ENABLE
329			`ADDR_UART1 : $display("UART1 WRITE: <%c>", data_in[31:24]);
330			`endif
331			`ifdef UART2_ENABLE
332			`ADDR_UART2 : $display("UART2 WRITE: <%c>", data_in[31:24]);
333			`endif
334			`ifdef SP3SK_PROM_DATA
335			`ADDR_PROM : begin
336			`prom_next_sync <= data_in[23];`
337			`prom_read <= data_in[22];`
338			`end`
339			`endif
340			`ifdef TIMER1_GENERATOR
341			`ADDR_TIMER1 : begin
342			`max_timer1_count <= data_in[30:0];`
343			`timer1_running <= data_in[31];`
344			`//synthesis translate_off`
345			`if(data_in[31] == 0) $display("TIMER1 STOP");`
346			`else $display("TIMER1 START (max_timer1_count=0x%x)", data_in[30:0]);`
347			`//synthesis translate_on`
348			`end`
349			`endif
350			`ifdef ENABLE_INTERRUPTS
351			`ADDR_INT : device_interrupt <= data_in;
352			`endif
353			default : $display("Error: Output port not valid: ", addr[`IO_SIZE-1:0]);
354			`endcase`
355			`end`
356			`end`
357
358			`// write to UART transmitter FIFO buffer at address 01 hex.`
359			`// This is a combinatorial decode because the FIFO is the 'port register'.`
360			`ifdef UART1_ENABLE
361			wire uart1_selected = addr[`IO_SIZE-1:0] == `ADDR_UART1;
362			`assign write_to_uart = write & uart1_selected;`
363			`endif
364			`ifdef UART2_ENABLE
365			wire uart2_selected = addr[`IO_SIZE-1:0] == `ADDR_UART2;
366			`assign write_to_uart2 = write & uart2_selected;`
367			`endif
368
369			`// --------------- decode input port (data to cpu) ----------------`
370			`reg [31:0] data_out; // register to store data from an input port`
371			`//synthesis translate_off`
372			`initial data_out <= 0;`
373			`//synthesis translate_on`
374
375			`always @(posedge clk)`
376			`begin`
377			`if(read) // request an input port`
378			`begin`
379			case( addr[`IO_SIZE-1:0] )
380			`ifdef SP3SK_USERIO
381			`ADDR_SP3_IO : begin
382			`data_out[31:24] <= segments_n; // LSByte is the high bits`
383			`data_out[23:20] <= drivers_n;`
384			`data_out[19:16] <= pushbuttons;`
385			`data_out[15:8] <= leds;`
386			`data_out[7:0] <= switches;`
387			`end`
388			`endif
389			`ifdef UART_STATUS_REG
390			`ADDR_UARTS : begin // depending which uarts are enabled, fill the status register
391			`ifdef UART1_ENABLE
392			`data_out[28:24] <= { tx_full, tx_half_full, rx_full, rx_half_full, rx_data_present };`
393			`$display("UART-STATUS : rx1_data_present=%d, rx1_half_full=%d, rx1_full=%d, tx1_half_full=%d, tx1_full=%d", rx_data_present, rx_half_full, rx_full, tx_half_full, tx_full);`
394			`endif
395			`ifdef UART2_ENABLE
396			`data_out[12:8] <= { tx2_full, tx2_half_full, rx2_full, rx2_half_full, rx2_data_present };`
397			`$display("UART-STATUS : rx2_data_present=%d, rx2_half_full=%d, rx2_full=%d, tx2_half_full=%d, tx2_full=%d", rx2_data_present, rx2_half_full, rx2_full, tx2_half_full, tx2_full);`
398			`endif
399			`end`
400			`endif
401			`ifdef UART1_ENABLE
402			`ADDR_UART1 : begin // receive data UART1
403			`data_out[31:24] <= rx_data;`
404			`$display("UART1 READ: %c", rx_data);`
405			`end`
406			`endif
407			`ifdef UART2_ENABLE
408			`ADDR_UART2 : begin // receive data UART2
409			`data_out[31:24] <= rx_data2;`
410			`$display("UART2 READ: %c", rx_data2);`
411			`end`
412			`endif
413			`ifdef SP3SK_PROM_DATA
414			`ADDR_PROM : begin
415			`data_out[31:24] <= prom_dataout; // data from PROM (only valid if prom_dataready)`
416			`data_out[23] <= prom_next_sync; // actual register`
417			`data_out[22] <= prom_read; // register`
418			`data_out[21] <= prom_synced; // prom is synced?`
419			`data_out[20] <= prom_dataready; // data is ready?`
420			`end`
421			`endif
422			`ifdef TIMER1_GENERATOR
423			`ADDR_TIMER1 : begin
424			`data_out[30:0] <= timer1_count;`
425			`data_out[31] <= timer1_running;`
426			`//synthesis translate_off`
427			`if(timer1_running == 0) $display("TIMER1 STOPPED");`
428			`else $display("TIMER1 RUNNING (count=0x%x)", timer1_count);`
429			`//synthesis translate_on`
430			`end`
431			`endif
432			`ifdef ENABLE_INTERRUPTS
433			`ADDR_INT : data_out <= device_interrupt;
434			`endif
435			default : $display("Error: Input port not valid: ", addr[`IO_SIZE-1:0]);
436			`endcase`
437			`end`
438			`// Form read strobe for UART receiver FIFO buffer.`
439			`// The fact that the read strobe will occur after the actual data is read by`
440			`// the CPU is acceptable because it is really means 'I have read you'!`
441			`ifdef UART1_ENABLE
442			`read_from_uart <= read & uart1_selected; // strobe para dato leido desde uart #1`
443			`endif
444			`ifdef UART2_ENABLE
445			`read_from_uart2 <= read & uart2_selected; // strobe para dato leido desde uart #2`
446			`endif
447			`end`
448
449			`endmodule`