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[/] [openfire2/] [trunk/] [rtl/] [openfire_soc.v] - Blame information for rev 6

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/*      MODULE: openfire soc
        DESCRIPTION: Contains top-level SOC
 
AUTHOR:
Antonio J. Anton
Anro Ingenieros (www.anro-ingenieros.com)
aj@anro-ingenieros.com
 
REVISION HISTORY:
Revision 1.0, 26/03/2007
Initial release
 
COPYRIGHT:
Copyright (c) 2007 Antonio J. Anton
 
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
 
`timescale 1ns / 1ps
`include "openfire_define.v"
 
module openfire_soc(
`ifndef SP3SK_USERIO
        rst,                                    // if no SP3SK IOs, then we need a reset signal
`endif
`ifdef SP3SK_USERIO
        leds,   drivers_n, segments_n, pushbuttons, switches,
`endif
`ifdef UART1_ENABLE
        tx1, rx1,
`endif
`ifdef UART2_ENABLE
        tx2, rx2,
`endif
`ifdef SP3SK_SRAM
        ram_addr, ram_oe_n, ram_we_n,
        ram1_io, ram1_ce_n, ram1_ub_n, ram1_lb_n,
        ram2_io, ram2_ce_n, ram2_ub_n, ram2_lb_n,
`endif
`ifdef SP3SK_VGA
        r, g, b, hsync_n, vsync_n,
`endif
`ifdef SP3SK_PROM_DATA
        prom_din, prom_cclk, prom_reset_n,
`endif
//      tx_ultrasonidos_p, tx_ultrasonidos_n, rx_ultrasonidos,
//      spi_clk, spi_datain, spi_dataout, 
//      spi_cs_1, spi_cs_2, spi_cs_3, spi_cs_4,
//      i2c_clk, i2c_data,
        clk_50mhz
);
 
`ifndef SP3SK_USERIO
input                           rst;                            // external RST (active HIGH)
`endif
input                                   clk_50mhz;              // board clock 50 MHZ
`ifdef SP3SK_USERIO
output  [7:0]    leds;                           // onboard LEDS
output  [3:0]            drivers_n;              // 7segments element's driver (negated)
output  [7:0]            segments_n;             // display segment
input           [3:0]            pushbuttons;    // 4 push-buttons
input           [7:0]            switches;               // 8 switches
`endif
`ifdef UART1_ENABLE
input                                   rx1;                            // RS232 rx
output                          tx1;                            // RS232 tx
`endif
`ifdef UART2_ENABLE
input                                   rx2;                            // RS232 rx #2
output                          tx2;                            // RS232 tx #2
`endif
`ifdef SP3SK_SRAM
output  [17:0]   ram_addr;               // SRAM ADDR (256K @)
output                          ram_oe_n;               // OE_N shared by 2 IC
output                          ram_we_n;               //      WE_N shared by 2 IC
inout           [15:0]   ram1_io;                        //      I/O data port SRAM1
output                          ram1_ce_n;              // SRAM1 CE_N   chip enable
output                          ram1_ub_n;              // UB_N upper byte select
output                          ram1_lb_n;              // LB_N  lower byte select
inout           [15:0]   ram2_io;                        //      I/O data port SRAM2
output                          ram2_ce_n;              // SRAM2 CE_N   chip enable
output                          ram2_ub_n;              // UB_N upper byte select
output                          ram2_lb_n;              // LB_N  lower byte select
`endif
`ifdef SP3SK_VGA
output                          r, g, b;                        // VGA components (1 bit per component)
output                          hsync_n;                        // VGA hsync_n
output                          vsync_n;                        // VGA vsync_n
`endif
`ifdef SP3SK_PROM_DATA
input                                   prom_din;
output                          prom_cclk;
output                          prom_reset_n;
`endif
//output                                tx_ultrasonidos_p;              // application specific ports
//output                                tx_ultrasonidos_n;
//input                         rx_ultrasonidos;
//output                                spi_clk;
//input                         spi_datain;
//output                                spi_dataout;
//output                                spi_cs_1;
//output                                spi_cs_2;
//output                                spi_cs_3;
//output                                spi_cs_4;
//inout                         i2c_clk;
//inout                         i2c_data;
 
// -------- connections ------------
`ifdef SP3SK_USERIO
wire                            rst = pushbuttons[3];           // reset generated from a push button
`endif
wire    [31:0]   imem_data;                              // ports to/from CPU
wire    [31:0]   imem_addr;
wire    [31:0]   dmem_data2mem;
wire    [31:0]   dmem_data2cpu;
wire    [31:0]   dmem_addr;
wire    [1:0]            dmem_input_sel;         // 0=byte, 1=hw, 2=word
wire  [3:0]              data_selector;                  // maps each byte in a word (msb..lsb)
wire                            dmem_we;                                        // request data write
wire                            dmem_re;                                        // request data read
wire                            imem_re;                                        // request instruction read
wire  [31:0]     dmem_data_frombram;     // arbitrer to/from BRAM
wire  [31:0]     dmem_data_tobram;
wire                            dmem_we_bram;
wire  [31:0]     imem_data_frombram;
`ifdef SP3SK_IODEVICES
wire    [31:0]   dmem_data_fromio;               // arbitrer to/from IO-SPACE
wire  [31:0]     dmem_data_toio;
wire                       dmem_we_io;
wire                            dmem_re_io;
`endif
`ifdef IO_MULTICYCLE
wire                            io_done;                                        // handle multicycle i/o operations
`endif
wire                       imem_done;                           // operation on imem completed
wire                       dmem_done;                           // operation on dmem completed
`ifdef SP3SK_SRAM
wire    [31:0]   sram_data2mem1;
wire    [31:0]   sram_data2cpu1;
wire                            sram_re1, sram_we1, sram_done1;
wire    [31:0]   sram_data2cpu2;
wire                            sram_re2, sram_done2;
wire    [17:0]   sram_addr3;                             // port #3 other uses
wire    [31:0]   sram_data2cpu3;
wire                            sram_re3, sram_done3;
`endif
 
`ifdef CLK_25MHZ                                                        // cpu clock generation
reg clk;
//synthesis translate_off
initial clk = 0;
//synthesis translate_on
always @(posedge clk_50mhz) clk <= ~clk;                // 25mhz clock
`else
wire                            clk = clk_50mhz;                                        // 50mhz clock
`endif
 
`ifdef ENABLE_INTERRUPTS
wire                            interrupt;                                                      // interrupt line
`endif
 
`ifdef ENABLE_ALIGNMENT_EXCEPTION
wire    dmem_alignment_exception;
`endif
 
// --------- instantiation of the SoC ----------------
openfire_cpu CPU(                                                       // openfire CPU
        .clock(clk),
        .reset(rst),
`ifdef ENABLE_INTERRUPTS
        .interrupt(interrupt),
`endif
`ifdef ENABLE_ALIGNMENT_EXCEPTION
        .dmem_alignment_exception(dmem_alignment_exception),
`endif
        .dmem_addr(dmem_addr),
        .dmem_data_in(dmem_data2cpu),
        .dmem_data_out(dmem_data2mem),
        .dmem_we(dmem_we),
        .dmem_re(dmem_re),
        .dmem_input_sel(dmem_input_sel),
        .dmem_done(dmem_done),
        .imem_addr(imem_addr),
        .imem_data_in(imem_data),
        .imem_re(imem_re),
        .imem_done(imem_done)
);
 
openfire_arbitrer ARBITRER(                     // bus arbitrer 
`ifdef SP3SK_SRAM
        .sram_data2mem(sram_data2mem1),
        .sram_data2cpu(sram_data2cpu1),
        .sram_dmem_re(sram_re1),
        .sram_dmem_we(sram_we1),
        .sram_dmem_done(sram_done1),
        .sram_ins2cpu(sram_data2cpu2),
        .sram_imem_re(sram_re2),
        .sram_imem_done(sram_done2),
`endif
`ifdef IO_MULTICYCLE
        .dmem_done_io(io_done),
`endif
`ifdef SP3SK_IODEVICES
        .dmem_we_io(dmem_we_io),
        .dmem_re_io(dmem_re_io),
        .dmem_data_fromio(dmem_data_fromio),
        .dmem_data_toio(dmem_data_toio),
`endif
`ifdef ENABLE_ALIGNMENT_EXCEPTION
        .dmem_alignment_exception(dmem_alignment_exception),
`endif
        .clock(clk),
        .reset(rst),
        .imem_done(imem_done),
        .dmem_done(dmem_done),
        .dmem_address(dmem_addr),
        .dmem_data_out(dmem_data2cpu),
        .dmem_data_in(dmem_data2mem),
        .dmem_re(dmem_re),
        .dmem_we(dmem_we),
        .dmem_input_sel(dmem_input_sel),
        .data_selector(data_selector),
        .imem_address(imem_addr),
        .imem_data(imem_data),
        .imem_re(imem_re),
        .dmem_data_frombram(dmem_data_frombram),
        .dmem_data_tobram(dmem_data_tobram),
        .dmem_we_bram(dmem_we_bram),
        .imem_data_frombram(imem_data_frombram)
);
 
`ifdef SP3SK_IODEVICES
openfire_iospace IOSPACE(                               // i/o space manager
`ifdef SP3SK_USERIO
        .leds(leds),
        .drivers_n(drivers_n),
        .segments_n(segments_n),
        .pushbuttons(pushbuttons),
        .switches(switches),
`endif
`ifdef UART1_ENABLE
        .tx1(tx1),
        .rx1(rx1),
`endif
`ifdef UART2_ENABLE
        .tx2(tx2),
        .rx2(rx2),
`endif
`ifdef SP3SK_PROM_DATA
         .prom_din(prom_din),
         .prom_cclk(prom_cclk),
         .prom_reset_n(prom_reset_n),
`endif
`ifdef ENABLE_INTERRUPTS
         .interrupt(interrupt),
`endif
`ifdef IO_MULTICYCLE
        .done(io_done),
`endif
        .clk(~clk),
        .rst(rst),
        .addr(dmem_addr[`IO_SIZE+1:2]),
        .data_in(dmem_data_toio),
        .data_out(dmem_data_fromio),
        .read(dmem_re_io),
        .write(dmem_we_io)
);
`endif
 
openfire_bootram BOOTRAM(                               // boot ram (block ram)
        .rst(rst),
        .clk(~clk),
        .ins_addr( imem_addr[12:2] ),
        .ins_output(imem_data_frombram),
        .data_sel(data_selector),
        .data_we(dmem_we_bram),
        .data_addr( dmem_addr[12:2] ),
        .data_input(dmem_data_tobram),
        .data_output(dmem_data_frombram)
);
 
`ifdef SP3SK_SRAM                                                       // sram controller
sram_controller sram_256kx32(
        .rst(rst), .clk(~clk),                          // controller at full speed
 
        .ram_addr(ram_addr), .ram_oe_n(ram_oe_n),   .ram_we_n(ram_we_n),        // sp3sk sram interface
        .ram1_io(ram1_io),   .ram1_ce_n(ram1_ce_n), .ram1_ub_n(ram1_ub_n), .ram1_lb_n(ram1_lb_n),
        .ram2_io(ram2_io),   .ram2_ce_n(ram2_ce_n), .ram2_ub_n(ram2_ub_n), .ram2_lb_n(ram2_lb_n),
 
        .addr1( dmem_addr[19:2] ),              // dmem port (read/write) byte capable
        .data2mem1(sram_data2mem1),
        .data2cpu1(sram_data2cpu1),
        .re1(sram_re1),
        .we1(sram_we1),
        .select1(data_selector),
        .done1(sram_done1),
 
        .addr2( imem_addr[19:2] ),              // imem port (read only) word only
        .data2cpu2(sram_data2cpu2),
        .re2(sram_re2),
        .done2(sram_done2),
 
        .addr3(sram_addr3),                                      // aux port (read only) word only
        .data2cpu3(sram_data2cpu3),
        .re3(sram_re3),
        .done3(sram_done3)
);
`endif
 
`ifdef SP3SK_VGA                                                        // vga module
vga_controller VGA(
        .reset(rst),
        .cpu_clk(clk),                                                  // for the sram fetch module
        .pixel_clk(clk),                                                // should be 25MHz for 640x480 video mode
        .hsync_n(hsync_n),
        .vsync_n(vsync_n),
        .red(r),
        .green(g),
        .blue(b),
        .ram_pointer(sram_addr3),
        .ram_data(sram_data2cpu3),
        .req(sram_re3),
        .rdy(sram_done3)
);
`endif
 
`include "openfire_debug.v"
endmodule
 

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[/] [openfire2/] [trunk/] [rtl/] [openfire_soc.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	3	toni32	`/* MODULE: openfire soc`
2			`DESCRIPTION: Contains top-level SOC`
3
4			`AUTHOR:`
5			`Antonio J. Anton`
6			`Anro Ingenieros (www.anro-ingenieros.com)`
7			`aj@anro-ingenieros.com`
8
9			`REVISION HISTORY:`
10			`Revision 1.0, 26/03/2007`
11			`Initial release`
12
13			`COPYRIGHT:`
14			`Copyright (c) 2007 Antonio J. Anton`
15
16			`Permission is hereby granted, free of charge, to any person obtaining a copy of`
17			`this software and associated documentation files (the "Software"), to deal in`
18			`the Software without restriction, including without limitation the rights to`
19			`use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies`
20			`of the Software, and to permit persons to whom the Software is furnished to do`
21			`so, subject to the following conditions:`
22
23			`The above copyright notice and this permission notice shall be included in all`
24			`copies or substantial portions of the Software.`
25
26			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
27			`IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
28			`FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
29			`AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
30			`LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
31			`OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
32			`SOFTWARE.*/`
33
34			`timescale 1ns / 1ps
35			`include "openfire_define.v"
36
37			`module openfire_soc(`
38			`ifndef SP3SK_USERIO
39			`rst, // if no SP3SK IOs, then we need a reset signal`
40			`endif
41			`ifdef SP3SK_USERIO
42			`leds, drivers_n, segments_n, pushbuttons, switches,`
43			`endif
44			`ifdef UART1_ENABLE
45			`tx1, rx1,`
46			`endif
47			`ifdef UART2_ENABLE
48			`tx2, rx2,`
49			`endif
50			`ifdef SP3SK_SRAM
51			`ram_addr, ram_oe_n, ram_we_n,`
52			`ram1_io, ram1_ce_n, ram1_ub_n, ram1_lb_n,`
53			`ram2_io, ram2_ce_n, ram2_ub_n, ram2_lb_n,`
54			`endif
55			`ifdef SP3SK_VGA
56			`r, g, b, hsync_n, vsync_n,`
57			`endif
58			`ifdef SP3SK_PROM_DATA
59			`prom_din, prom_cclk, prom_reset_n,`
60			`endif
61			`// tx_ultrasonidos_p, tx_ultrasonidos_n, rx_ultrasonidos,`
62			`// spi_clk, spi_datain, spi_dataout,`
63			`// spi_cs_1, spi_cs_2, spi_cs_3, spi_cs_4,`
64			`// i2c_clk, i2c_data,`
65			`clk_50mhz`
66			`);`
67
68			`ifndef SP3SK_USERIO
69			`input rst; // external RST (active HIGH)`
70			`endif
71			`input clk_50mhz; // board clock 50 MHZ`
72			`ifdef SP3SK_USERIO
73			`output [7:0] leds; // onboard LEDS`
74			`output [3:0] drivers_n; // 7segments element's driver (negated)`
75			`output [7:0] segments_n; // display segment`
76			`input [3:0] pushbuttons; // 4 push-buttons`
77			`input [7:0] switches; // 8 switches`
78			`endif
79			`ifdef UART1_ENABLE
80			`input rx1; // RS232 rx`
81			`output tx1; // RS232 tx`
82			`endif
83			`ifdef UART2_ENABLE
84			`input rx2; // RS232 rx #2`
85			`output tx2; // RS232 tx #2`
86			`endif
87			`ifdef SP3SK_SRAM
88			`output [17:0] ram_addr; // SRAM ADDR (256K @)`
89			`output ram_oe_n; // OE_N shared by 2 IC`
90			`output ram_we_n; // WE_N shared by 2 IC`
91			`inout [15:0] ram1_io; // I/O data port SRAM1`
92			`output ram1_ce_n; // SRAM1 CE_N chip enable`
93			`output ram1_ub_n; // UB_N upper byte select`
94			`output ram1_lb_n; // LB_N lower byte select`
95			`inout [15:0] ram2_io; // I/O data port SRAM2`
96			`output ram2_ce_n; // SRAM2 CE_N chip enable`
97			`output ram2_ub_n; // UB_N upper byte select`
98			`output ram2_lb_n; // LB_N lower byte select`
99			`endif
100			`ifdef SP3SK_VGA
101			`output r, g, b; // VGA components (1 bit per component)`
102			`output hsync_n; // VGA hsync_n`
103			`output vsync_n; // VGA vsync_n`
104			`endif
105			`ifdef SP3SK_PROM_DATA
106			`input prom_din;`
107			`output prom_cclk;`
108			`output prom_reset_n;`
109			`endif
110			`//output tx_ultrasonidos_p; // application specific ports`
111			`//output tx_ultrasonidos_n;`
112			`//input rx_ultrasonidos;`
113			`//output spi_clk;`
114			`//input spi_datain;`
115			`//output spi_dataout;`
116			`//output spi_cs_1;`
117			`//output spi_cs_2;`
118			`//output spi_cs_3;`
119			`//output spi_cs_4;`
120			`//inout i2c_clk;`
121			`//inout i2c_data;`
122
123			`// -------- connections ------------`
124			`ifdef SP3SK_USERIO
125			`wire rst = pushbuttons[3]; // reset generated from a push button`
126			`endif
127			`wire [31:0] imem_data; // ports to/from CPU`
128			`wire [31:0] imem_addr;`
129			`wire [31:0] dmem_data2mem;`
130			`wire [31:0] dmem_data2cpu;`
131			`wire [31:0] dmem_addr;`
132			`wire [1:0] dmem_input_sel; // 0=byte, 1=hw, 2=word`
133			`wire [3:0] data_selector; // maps each byte in a word (msb..lsb)`
134			`wire dmem_we; // request data write`
135			`wire dmem_re; // request data read`
136			`wire imem_re; // request instruction read`
137			`wire [31:0] dmem_data_frombram; // arbitrer to/from BRAM`
138			`wire [31:0] dmem_data_tobram;`
139			`wire dmem_we_bram;`
140			`wire [31:0] imem_data_frombram;`
141			`ifdef SP3SK_IODEVICES
142			`wire [31:0] dmem_data_fromio; // arbitrer to/from IO-SPACE`
143			`wire [31:0] dmem_data_toio;`
144			`wire dmem_we_io;`
145			`wire dmem_re_io;`
146			`endif
147			`ifdef IO_MULTICYCLE
148			`wire io_done; // handle multicycle i/o operations`
149			`endif
150			`wire imem_done; // operation on imem completed`
151			`wire dmem_done; // operation on dmem completed`
152			`ifdef SP3SK_SRAM
153			`wire [31:0] sram_data2mem1;`
154			`wire [31:0] sram_data2cpu1;`
155			`wire sram_re1, sram_we1, sram_done1;`
156			`wire [31:0] sram_data2cpu2;`
157			`wire sram_re2, sram_done2;`
158			`wire [17:0] sram_addr3; // port #3 other uses`
159			`wire [31:0] sram_data2cpu3;`
160			`wire sram_re3, sram_done3;`
161			`endif
162
163			`ifdef CLK_25MHZ // cpu clock generation
164			`reg clk;`
165			`//synthesis translate_off`
166			`initial clk = 0;`
167			`//synthesis translate_on`
168			`always @(posedge clk_50mhz) clk <= ~clk; // 25mhz clock`
169			`else
170			`wire clk = clk_50mhz; // 50mhz clock`
171			`endif
172
173			`ifdef ENABLE_INTERRUPTS
174			`wire interrupt; // interrupt line`
175			`endif
176
177			`ifdef ENABLE_ALIGNMENT_EXCEPTION
178			`wire dmem_alignment_exception;`
179			`endif
180
181			`// --------- instantiation of the SoC ----------------`
182			`openfire_cpu CPU( // openfire CPU`
183			`.clock(clk),`
184			`.reset(rst),`
185			`ifdef ENABLE_INTERRUPTS
186			`.interrupt(interrupt),`
187			`endif
188			`ifdef ENABLE_ALIGNMENT_EXCEPTION
189			`.dmem_alignment_exception(dmem_alignment_exception),`
190			`endif
191			`.dmem_addr(dmem_addr),`
192			`.dmem_data_in(dmem_data2cpu),`
193			`.dmem_data_out(dmem_data2mem),`
194			`.dmem_we(dmem_we),`
195			`.dmem_re(dmem_re),`
196			`.dmem_input_sel(dmem_input_sel),`
197			`.dmem_done(dmem_done),`
198			`.imem_addr(imem_addr),`
199			`.imem_data_in(imem_data),`
200			`.imem_re(imem_re),`
201			`.imem_done(imem_done)`
202			`);`
203
204			`openfire_arbitrer ARBITRER( // bus arbitrer`
205			`ifdef SP3SK_SRAM
206			`.sram_data2mem(sram_data2mem1),`
207			`.sram_data2cpu(sram_data2cpu1),`
208			`.sram_dmem_re(sram_re1),`
209			`.sram_dmem_we(sram_we1),`
210			`.sram_dmem_done(sram_done1),`
211			`.sram_ins2cpu(sram_data2cpu2),`
212			`.sram_imem_re(sram_re2),`
213			`.sram_imem_done(sram_done2),`
214			`endif
215			`ifdef IO_MULTICYCLE
216			`.dmem_done_io(io_done),`
217			`endif
218			`ifdef SP3SK_IODEVICES
219			`.dmem_we_io(dmem_we_io),`
220			`.dmem_re_io(dmem_re_io),`
221			`.dmem_data_fromio(dmem_data_fromio),`
222			`.dmem_data_toio(dmem_data_toio),`
223			`endif
224			`ifdef ENABLE_ALIGNMENT_EXCEPTION
225			`.dmem_alignment_exception(dmem_alignment_exception),`
226			`endif
227			`.clock(clk),`
228			`.reset(rst),`
229			`.imem_done(imem_done),`
230			`.dmem_done(dmem_done),`
231			`.dmem_address(dmem_addr),`
232			`.dmem_data_out(dmem_data2cpu),`
233			`.dmem_data_in(dmem_data2mem),`
234			`.dmem_re(dmem_re),`
235			`.dmem_we(dmem_we),`
236			`.dmem_input_sel(dmem_input_sel),`
237			`.data_selector(data_selector),`
238			`.imem_address(imem_addr),`
239			`.imem_data(imem_data),`
240			`.imem_re(imem_re),`
241			`.dmem_data_frombram(dmem_data_frombram),`
242			`.dmem_data_tobram(dmem_data_tobram),`
243			`.dmem_we_bram(dmem_we_bram),`
244			`.imem_data_frombram(imem_data_frombram)`
245			`);`
246
247			`ifdef SP3SK_IODEVICES
248			`openfire_iospace IOSPACE( // i/o space manager`
249			`ifdef SP3SK_USERIO
250			`.leds(leds),`
251			`.drivers_n(drivers_n),`
252			`.segments_n(segments_n),`
253			`.pushbuttons(pushbuttons),`
254			`.switches(switches),`
255			`endif
256			`ifdef UART1_ENABLE
257			`.tx1(tx1),`
258			`.rx1(rx1),`
259			`endif
260			`ifdef UART2_ENABLE
261			`.tx2(tx2),`
262			`.rx2(rx2),`
263			`endif
264			`ifdef SP3SK_PROM_DATA
265			`.prom_din(prom_din),`
266			`.prom_cclk(prom_cclk),`
267			`.prom_reset_n(prom_reset_n),`
268			`endif
269			`ifdef ENABLE_INTERRUPTS
270			`.interrupt(interrupt),`
271			`endif
272			`ifdef IO_MULTICYCLE
273			`.done(io_done),`
274			`endif
275			`.clk(~clk),`
276			`.rst(rst),`
277			.addr(dmem_addr[`IO_SIZE+1:2]),
278			`.data_in(dmem_data_toio),`
279			`.data_out(dmem_data_fromio),`
280			`.read(dmem_re_io),`
281			`.write(dmem_we_io)`
282			`);`
283			`endif
284
285			`openfire_bootram BOOTRAM( // boot ram (block ram)`
286			`.rst(rst),`
287			`.clk(~clk),`
288			`.ins_addr( imem_addr[12:2] ),`
289			`.ins_output(imem_data_frombram),`
290			`.data_sel(data_selector),`
291			`.data_we(dmem_we_bram),`
292			`.data_addr( dmem_addr[12:2] ),`
293			`.data_input(dmem_data_tobram),`
294			`.data_output(dmem_data_frombram)`
295			`);`
296
297			`ifdef SP3SK_SRAM // sram controller
298			`sram_controller sram_256kx32(`
299			`.rst(rst), .clk(~clk), // controller at full speed`
300
301			`.ram_addr(ram_addr), .ram_oe_n(ram_oe_n), .ram_we_n(ram_we_n), // sp3sk sram interface`
302			`.ram1_io(ram1_io), .ram1_ce_n(ram1_ce_n), .ram1_ub_n(ram1_ub_n), .ram1_lb_n(ram1_lb_n),`
303			`.ram2_io(ram2_io), .ram2_ce_n(ram2_ce_n), .ram2_ub_n(ram2_ub_n), .ram2_lb_n(ram2_lb_n),`
304
305			`.addr1( dmem_addr[19:2] ), // dmem port (read/write) byte capable`
306			`.data2mem1(sram_data2mem1),`
307			`.data2cpu1(sram_data2cpu1),`
308			`.re1(sram_re1),`
309			`.we1(sram_we1),`
310			`.select1(data_selector),`
311			`.done1(sram_done1),`
312
313			`.addr2( imem_addr[19:2] ), // imem port (read only) word only`
314			`.data2cpu2(sram_data2cpu2),`
315			`.re2(sram_re2),`
316			`.done2(sram_done2),`
317
318			`.addr3(sram_addr3), // aux port (read only) word only`
319			`.data2cpu3(sram_data2cpu3),`
320			`.re3(sram_re3),`
321			`.done3(sram_done3)`
322			`);`
323			`endif
324
325			`ifdef SP3SK_VGA // vga module
326			`vga_controller VGA(`
327			`.reset(rst),`
328			`.cpu_clk(clk), // for the sram fetch module`
329			`.pixel_clk(clk), // should be 25MHz for 640x480 video mode`
330			`.hsync_n(hsync_n),`
331			`.vsync_n(vsync_n),`
332			`.red(r),`
333			`.green(g),`
334			`.blue(b),`
335			`.ram_pointer(sram_addr3),`
336			`.ram_data(sram_data2cpu3),`
337			`.req(sram_re3),`
338			`.rdy(sram_done3)`
339			`);`
340			`endif
341
342			`include "openfire_debug.v"
343			`endmodule`
344