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[/] [openfire2/] [trunk/] [rtl/] [openfire_template_bootram.v] - Blame information for rev 3

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/*      MODULE: openfire bootram
        DESCRIPTION: Contains BRAM instanties loaded with the boot program
 
AUTHOR:
Antonio J. Anton
Anro Ingenieros (www.anro-ingenieros.com)
aj@anro-ingenieros.com
 
REVISION HISTORY:
Revision 1.0, 26/03/2007
Initial release
 
COPYRIGHT:
Copyright (c) 2007 Antonio J. Anton
 
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
 
`timescale 1ns / 1ps
 
// bootram is an internal 2048 x 32 bit dualport ram inside
// FPGA to let CPU boot without external resources
// this RAM is shared by program and data 
 
module openfire_bootram(
        rst, clk, ins_addr, ins_output,
        data_we, data_addr, data_input, data_output,
        data_sel
);
 
input                     rst;                          // reset sincrono
input                     clk;                          // reloj
input    [10:0] ins_addr;                        // 11 bit INS-ADDR
output [31:0] ins_output;                // 32 bit INSTRUCTION
input                     data_we;                      // activa escritura DATA
input    [10:0] data_addr;               // 11 bit DATA-ADDR
input  [31:0] data_input;                // 32 bit DATA-IN
output [31:0] data_output;               // 32 bit DATA-OUT
input    [3:0]  data_sel;                        // byte selector
 
// ------------ block ram instances -------------
RAMB16_S9_S9 MEM3(
      .DOA(ins_output[31:24]),      // Port A ins_output
      .DOB(data_output[31:24]),     // Port B data_output
      .DOPA( ),                                                 // Port A 1-bit Parity Output NO
      .DOPB( ),                                                 // Port B 1-bit Parity Output NO
      .ADDRA(ins_addr[10:0]),            // Port A 11-bit Address Input
      .ADDRB(data_addr[10:0]),           // Port B 11-bit Address Input
      .CLKA(clk),                                       // Port A Clock
      .CLKB(clk),                                       // Port B Clock
      .DIA(8'b0),                                       // Port A 8-bit Data Input NO
      .DIB(data_input[31:24]),      // Port B 8-bit Data Input
      .DIPA(1'b0),                                      // Port A 1-bit parity Input
      .DIPB(1'b0),                                      // Port-B 1-bit parity Input
      .ENA(1'b1),                                       // Port A RAM Enable Input
      .ENB(1'b1),                                                       // PortB RAM Enable Input
      .SSRA(rst),                                       // Port A Synchronous Set/Reset Input
      .SSRB(rst),                                       // Port B Synchronous Set/Reset Input
      .WEA(1'b0),                                       // Port A Write Enable Input NO
      .WEB(data_we & data_sel[3])       // Port B Write Enable Input
   );
 
RAMB16_S9_S9 MEM2(
      .DOA(ins_output[23:16]),      // Port A ins_output
      .DOB(data_output[23:16]),     // Port B data_output
      .DOPA( ),                                                 // Port A 1-bit Parity Output NO
      .DOPB( ),                                                 // Port B 1-bit Parity Output NO
      .ADDRA(ins_addr[10:0]),            // Port A 11-bit Address Input
      .ADDRB(data_addr[10:0]),           // Port B 11-bit Address Input
      .CLKA(clk),                                       // Port A Clock
      .CLKB(clk),                                       // Port B Clock
      .DIA(8'b0),                                       // Port A 8-bit Data Input NO
      .DIB(data_input[23:16]),      // Port B 8-bit Data Input
      .DIPA(1'b0),                                      // Port A 1-bit parity Input
      .DIPB(1'b0),                                      // Port-B 1-bit parity Input
      .ENA(1'b1),                                       // Port A RAM Enable Input
      .ENB(1'b1),                                               // PortB RAM Enable Input
      .SSRA(rst),                                       // Port A Synchronous Set/Reset Input
      .SSRB(rst),                                       // Port B Synchronous Set/Reset Input
      .WEA(1'b0),                                       // Port A Write Enable Input NO
      .WEB(data_we & data_sel[2])       // Port B Write Enable Input
   );
 
RAMB16_S9_S9 MEM1(
      .DOA(ins_output[15:8]),       // Port A ins_output
      .DOB(data_output[15:8]),      // Port B data_output
      .DOPA( ),                                                 // Port A 1-bit Parity Output NO
      .DOPB( ),                                                 // Port B 1-bit Parity Output NO
      .ADDRA(ins_addr[10:0]),            // Port A 11-bit Address Input
      .ADDRB(data_addr[10:0]),           // Port B 11-bit Address Input
      .CLKA(clk),                                       // Port A Clock
      .CLKB(clk),                                       // Port B Clock
      .DIA(8'b0),                                       // Port A 8-bit Data Input NO
      .DIB(data_input[15:8]),       // Port B 8-bit Data Input
      .DIPA(1'b0),                                      // Port A 1-bit parity Input
      .DIPB(1'b0),                                      // Port-B 1-bit parity Input
      .ENA(1'b1),                                       // Port A RAM Enable Input
      .ENB(1'b1),                                               // PortB RAM Enable Input
      .SSRA(rst),                                       // Port A Synchronous Set/Reset Input
      .SSRB(rst),                                       // Port B Synchronous Set/Reset Input
      .WEA(1'b0),                                       // Port A Write Enable Input NO
      .WEB(data_we & data_sel[1])       // Port B Write Enable Input
   );
 
RAMB16_S9_S9 MEM0(
      .DOA(ins_output[7:0]),        // Port A ins_output
      .DOB(data_output[7:0]),       // Port B data_output
      .DOPA( ),                                                 // Port A 1-bit Parity Output NO
      .DOPB( ),                                                 // Port B 1-bit Parity Output NO
      .ADDRA(ins_addr[10:0]),            // Port A 11-bit Address Input
      .ADDRB(data_addr[10:0]),           // Port B 11-bit Address Input
      .CLKA(clk),                                       // Port A Clock
      .CLKB(clk),                                       // Port B Clock
      .DIA(8'b0),                                       // Port A 8-bit Data Input NO
      .DIB(data_input[7:0]),        // Port B 8-bit Data Input
      .DIPA(1'b0),                                      // Port A 1-bit parity Input
      .DIPB(1'b0),                                      // Port-B 1-bit parity Input
      .ENA(1'b1),                                       // Port A RAM Enable Input
      .ENB(1'b1),                                                       // PortB RAM Enable Input
      .SSRA(rst),                                       // Port A Synchronous Set/Reset Input
      .SSRB(rst),                                       // Port B Synchronous Set/Reset Input
      .WEA(1'b0),                                       // Port A Write Enable Input NO
      .WEB(data_we & data_sel[0])        // Port B Write Enable Input
   );
 
// ---------------- memory content -----------------
// this macro is replaced by a series of
// defparam MEMx.INIT_yy  = 256'h{hexadecimal bytes};
// as per BIN file provided to bin2bram
//
// also de MEMx.INIT_A/B and MEMx.SRVAL_A/B are initialized
// with the 1st DWORD in the BIN file to be available at startup/reset
 
// $DUMP_INIT_RAM
 
// blockram configuration and parity bits are left empty
// so default values are used
 
endmodule

Line No.	Rev	Author	Line
1	3	toni32	`/* MODULE: openfire bootram`
2			`DESCRIPTION: Contains BRAM instanties loaded with the boot program`
3
4			`AUTHOR:`
5			`Antonio J. Anton`
6			`Anro Ingenieros (www.anro-ingenieros.com)`
7			`aj@anro-ingenieros.com`
8
9			`REVISION HISTORY:`
10			`Revision 1.0, 26/03/2007`
11			`Initial release`
12
13			`COPYRIGHT:`
14			`Copyright (c) 2007 Antonio J. Anton`
15
16			`Permission is hereby granted, free of charge, to any person obtaining a copy of`
17			`this software and associated documentation files (the "Software"), to deal in`
18			`the Software without restriction, including without limitation the rights to`
19			`use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies`
20			`of the Software, and to permit persons to whom the Software is furnished to do`
21			`so, subject to the following conditions:`
22
23			`The above copyright notice and this permission notice shall be included in all`
24			`copies or substantial portions of the Software.`
25
26			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
27			`IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
28			`FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
29			`AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
30			`LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
31			`OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
32			`SOFTWARE.*/`
33
34			`timescale 1ns / 1ps
35
36			`// bootram is an internal 2048 x 32 bit dualport ram inside`
37			`// FPGA to let CPU boot without external resources`
38			`// this RAM is shared by program and data`
39
40			`module openfire_bootram(`
41			`rst, clk, ins_addr, ins_output,`
42			`data_we, data_addr, data_input, data_output,`
43			`data_sel`
44			`);`
45
46			`input rst; // reset sincrono`
47			`input clk; // reloj`
48			`input [10:0] ins_addr; // 11 bit INS-ADDR`
49			`output [31:0] ins_output; // 32 bit INSTRUCTION`
50			`input data_we; // activa escritura DATA`
51			`input [10:0] data_addr; // 11 bit DATA-ADDR`
52			`input [31:0] data_input; // 32 bit DATA-IN`
53			`output [31:0] data_output; // 32 bit DATA-OUT`
54			`input [3:0] data_sel; // byte selector`
55
56			`// ------------ block ram instances -------------`
57			`RAMB16_S9_S9 MEM3(`
58			`.DOA(ins_output[31:24]), // Port A ins_output`
59			`.DOB(data_output[31:24]), // Port B data_output`
60			`.DOPA( ), // Port A 1-bit Parity Output NO`
61			`.DOPB( ), // Port B 1-bit Parity Output NO`
62			`.ADDRA(ins_addr[10:0]), // Port A 11-bit Address Input`
63			`.ADDRB(data_addr[10:0]), // Port B 11-bit Address Input`
64			`.CLKA(clk), // Port A Clock`
65			`.CLKB(clk), // Port B Clock`
66			`.DIA(8'b0), // Port A 8-bit Data Input NO`
67			`.DIB(data_input[31:24]), // Port B 8-bit Data Input`
68			`.DIPA(1'b0), // Port A 1-bit parity Input`
69			`.DIPB(1'b0), // Port-B 1-bit parity Input`
70			`.ENA(1'b1), // Port A RAM Enable Input`
71			`.ENB(1'b1), // PortB RAM Enable Input`
72			`.SSRA(rst), // Port A Synchronous Set/Reset Input`
73			`.SSRB(rst), // Port B Synchronous Set/Reset Input`
74			`.WEA(1'b0), // Port A Write Enable Input NO`
75			`.WEB(data_we & data_sel[3]) // Port B Write Enable Input`
76			`);`
77
78			`RAMB16_S9_S9 MEM2(`
79			`.DOA(ins_output[23:16]), // Port A ins_output`
80			`.DOB(data_output[23:16]), // Port B data_output`
81			`.DOPA( ), // Port A 1-bit Parity Output NO`
82			`.DOPB( ), // Port B 1-bit Parity Output NO`
83			`.ADDRA(ins_addr[10:0]), // Port A 11-bit Address Input`
84			`.ADDRB(data_addr[10:0]), // Port B 11-bit Address Input`
85			`.CLKA(clk), // Port A Clock`
86			`.CLKB(clk), // Port B Clock`
87			`.DIA(8'b0), // Port A 8-bit Data Input NO`
88			`.DIB(data_input[23:16]), // Port B 8-bit Data Input`
89			`.DIPA(1'b0), // Port A 1-bit parity Input`
90			`.DIPB(1'b0), // Port-B 1-bit parity Input`
91			`.ENA(1'b1), // Port A RAM Enable Input`
92			`.ENB(1'b1), // PortB RAM Enable Input`
93			`.SSRA(rst), // Port A Synchronous Set/Reset Input`
94			`.SSRB(rst), // Port B Synchronous Set/Reset Input`
95			`.WEA(1'b0), // Port A Write Enable Input NO`
96			`.WEB(data_we & data_sel[2]) // Port B Write Enable Input`
97			`);`
98
99			`RAMB16_S9_S9 MEM1(`
100			`.DOA(ins_output[15:8]), // Port A ins_output`
101			`.DOB(data_output[15:8]), // Port B data_output`
102			`.DOPA( ), // Port A 1-bit Parity Output NO`
103			`.DOPB( ), // Port B 1-bit Parity Output NO`
104			`.ADDRA(ins_addr[10:0]), // Port A 11-bit Address Input`
105			`.ADDRB(data_addr[10:0]), // Port B 11-bit Address Input`
106			`.CLKA(clk), // Port A Clock`
107			`.CLKB(clk), // Port B Clock`
108			`.DIA(8'b0), // Port A 8-bit Data Input NO`
109			`.DIB(data_input[15:8]), // Port B 8-bit Data Input`
110			`.DIPA(1'b0), // Port A 1-bit parity Input`
111			`.DIPB(1'b0), // Port-B 1-bit parity Input`
112			`.ENA(1'b1), // Port A RAM Enable Input`
113			`.ENB(1'b1), // PortB RAM Enable Input`
114			`.SSRA(rst), // Port A Synchronous Set/Reset Input`
115			`.SSRB(rst), // Port B Synchronous Set/Reset Input`
116			`.WEA(1'b0), // Port A Write Enable Input NO`
117			`.WEB(data_we & data_sel[1]) // Port B Write Enable Input`
118			`);`
119
120			`RAMB16_S9_S9 MEM0(`
121			`.DOA(ins_output[7:0]), // Port A ins_output`
122			`.DOB(data_output[7:0]), // Port B data_output`
123			`.DOPA( ), // Port A 1-bit Parity Output NO`
124			`.DOPB( ), // Port B 1-bit Parity Output NO`
125			`.ADDRA(ins_addr[10:0]), // Port A 11-bit Address Input`
126			`.ADDRB(data_addr[10:0]), // Port B 11-bit Address Input`
127			`.CLKA(clk), // Port A Clock`
128			`.CLKB(clk), // Port B Clock`
129			`.DIA(8'b0), // Port A 8-bit Data Input NO`
130			`.DIB(data_input[7:0]), // Port B 8-bit Data Input`
131			`.DIPA(1'b0), // Port A 1-bit parity Input`
132			`.DIPB(1'b0), // Port-B 1-bit parity Input`
133			`.ENA(1'b1), // Port A RAM Enable Input`
134			`.ENB(1'b1), // PortB RAM Enable Input`
135			`.SSRA(rst), // Port A Synchronous Set/Reset Input`
136			`.SSRB(rst), // Port B Synchronous Set/Reset Input`
137			`.WEA(1'b0), // Port A Write Enable Input NO`
138			`.WEB(data_we & data_sel[0]) // Port B Write Enable Input`
139			`);`
140
141			`// ---------------- memory content -----------------`
142			`// this macro is replaced by a series of`
143			`// defparam MEMx.INIT_yy = 256'h{hexadecimal bytes};`
144			`// as per BIN file provided to bin2bram`
145			`//`
146			`// also de MEMx.INIT_A/B and MEMx.SRVAL_A/B are initialized`
147			`// with the 1st DWORD in the BIN file to be available at startup/reset`
148
149			`// $DUMP_INIT_RAM`
150
151			`// blockram configuration and parity bits are left empty`
152			`// so default values are used`
153
154			`endmodule`

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[/] [openfire2/] [trunk/] [rtl/] [openfire_template_bootram.v] - Blame information for rev 3