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--------------------------------------------------------------------------------
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-- Project : openFPU64 Constants
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-------------------------------------------------------------------------------
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-- File : fpu_package.vhd
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-- Author : Peter Huewe <peterhuewe@gmx.de>
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-- Created : 2010-04-19
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-- Last update: 2010-04-19
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description: Some constants for openFPU64
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--
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010
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-------------------------------------------------------------------------------
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-- License: gplv3, see licence.txt
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package fpu_package is
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constant ZEROS: unsigned (100 downto 0) := (others => '0');
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constant ONES: unsigned (100 downto 0) := (others => '1');
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constant ALL_ZEROS : unsigned (10 downto 0) := (others => '0');
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constant ALL_ONES : unsigned (10 downto 0) := (others => '1');
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constant ZERO_MANTISSA : unsigned (54 downto 0) := (others => '0');
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constant DOUBLE_BIAS : unsigned (12 downto 0) := '0'&x"3ff"; -- 1023 - Bias for Exponent
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constant DOUBLE_BIAS_2COMPLEMENT : unsigned (12 downto 0) := not(DOUBLE_BIAS)+1; -- -1023 - Bias for Exponent
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constant SINGLE_BIAS : unsigned (7 downto 0) := x"7f"; -- 127 - Bias for Exponent
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constant SINGLE_BIAS_2COMPLEMENT : unsigned (7 downto 0) := not(x"7f"+1); -- -127 - Bias for Exponent
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constant DOUBLE_PRECISION : std_logic := '0';
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constant SINGLE_PRECISION: std_logic := '1';
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constant addr_a_hi : std_logic_vector(1 downto 0) := "00"; -- hi-word operand A - writeonly
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constant addr_a_lo : std_logic_vector(1 downto 0) := "01"; -- low-word operand A - writeonly
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constant addr_b_hi : std_logic_vector(1 downto 0) := "10"; -- hi-word operand B - writeonly
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constant addr_b_lo : std_logic_vector(1 downto 0) := "11"; -- low-word operand B - writeonly
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constant addr_result_hi : std_logic_vector(1 downto 0) := "00"; -- hi-word result - readonly
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constant addr_result_lo : std_logic_vector(1 downto 0) := "01"; -- low-word result - readonly
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constant addr_flags : std_logic_vector(1 downto 0) := "11"; -- exception flags - readonly
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constant mode_add : std_logic_vector (2 downto 0) := "000"; -- Addition Mode
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constant mode_sub : std_logic_vector (2 downto 0) := "001"; -- Subtraction Mode
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constant mode_mul : std_logic_vector (2 downto 0) := "010"; -- Multiply Mode
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constant mode_div : std_logic_vector (2 downto 0) := "011"; -- Division Mode
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constant mode_test : std_logic_vector (2 downto 0) := "111"; -- Testing Mode
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end fpu_package;
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