Subversion Repositories openfpu64

# TCL File Generated by Component Editor 9.1sp2

# Mon Apr 19 13:47:02 CEST 2010

# DO NOT MODIFY

# +-----------------------------------

# | 

# | openfpu64 "openfpu64" v1.9

# | Peter Huewe 2010.04.19.13:47:02

# | open source double precision FPU

# | 

# | /data/hardware/projects/gps410_v2_r3_dpfpu/openfpu64.vhd

# | 

# |    ./fpu_package.vhd syn

# |    ./openfpu64.vhd syn

# |    ./fpu_add.vhd syn

# |    ./fpu_mul.vhd syn

# | 

# +-----------------------------------

# +-----------------------------------

# | request TCL package from ACDS 9.1

# | 

package require -exact sopc 9.1

# | 

# +-----------------------------------

# +-----------------------------------

# | module openfpu64

# | 

set_module_property DESCRIPTION "open source double precision FPU"

set_module_property NAME openfpu64

set_module_property VERSION 1.9

set_module_property INTERNAL false

set_module_property GROUP ""

set_module_property AUTHOR "Peter Huewe"

set_module_property DISPLAY_NAME openfpu64

set_module_property TOP_LEVEL_HDL_FILE openfpu64.vhd

set_module_property TOP_LEVEL_HDL_MODULE openfpu64

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL TRUE

# | 

# +-----------------------------------

# +-----------------------------------

# | files

# | 

add_file fpu_package.vhd SYNTHESIS

add_file openfpu64.vhd SYNTHESIS

add_file fpu_add.vhd SYNTHESIS

add_file fpu_mul.vhd SYNTHESIS

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# +-----------------------------------

# +-----------------------------------

# | parameters

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# +-----------------------------------

# +-----------------------------------

# | display items

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# +-----------------------------------

# +-----------------------------------

# | connection point clock_reset

# | 

add_interface clock_reset clock end

set_interface_property clock_reset ENABLED true

add_interface_port clock_reset reset_n reset_n Input 1

add_interface_port clock_reset clk clk Input 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point avalon_slave_0

# | 

add_interface avalon_slave_0 avalon end

set_interface_property avalon_slave_0 addressAlignment DYNAMIC

set_interface_property avalon_slave_0 associatedClock clock_reset

set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false

set_interface_property avalon_slave_0 explicitAddressSpan 0

set_interface_property avalon_slave_0 holdTime 0

set_interface_property avalon_slave_0 isMemoryDevice false

set_interface_property avalon_slave_0 isNonVolatileStorage false

set_interface_property avalon_slave_0 linewrapBursts false

set_interface_property avalon_slave_0 maximumPendingReadTransactions 0

set_interface_property avalon_slave_0 printableDevice false

set_interface_property avalon_slave_0 readLatency 0

set_interface_property avalon_slave_0 readWaitTime 1

set_interface_property avalon_slave_0 setupTime 0

set_interface_property avalon_slave_0 timingUnits Cycles

set_interface_property avalon_slave_0 writeWaitTime 0

set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset

set_interface_property avalon_slave_0 ENABLED true

add_interface_port avalon_slave_0 read read Input 1

add_interface_port avalon_slave_0 write write Input 1

add_interface_port avalon_slave_0 address address Input 5

add_interface_port avalon_slave_0 readdata readdata Output 32

add_interface_port avalon_slave_0 writedata writedata Input 32

add_interface_port avalon_slave_0 waitrequest waitrequest Output 1

add_interface_port avalon_slave_0 begintransfer begintransfer Input 1

# | 

# +-----------------------------------