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//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ogfx_gpu_dma.v
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//
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// *Module Description:
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// Graphic-Processing unit 2D-DMA.
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module ogfx_gpu_dma (
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// OUTPUTs
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gpu_exec_done_o, // GPU execution done
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gpu_dma_busy_o, // GPU DMA execution on going
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vid_ram_addr_o, // Video-RAM address
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vid_ram_din_o, // Video-RAM data
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vid_ram_wen_o, // Video-RAM write strobe (active low)
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vid_ram_cen_o, // Video-RAM chip enable (active low)
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// INPUTs
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mclk, // Main system clock
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puc_rst, // Main system reset
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cfg_dst_px_addr_i, // Destination pixel address configuration
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cfg_dst_cl_swp_i, // Destination Column/Line-Swap configuration
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cfg_dst_x_swp_i, // Destination X-Swap configuration
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cfg_dst_y_swp_i, // Destination Y-Swap configuration
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cfg_fill_color_i, // Fill color (for rectangle fill operation)
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cfg_pix_op_sel_i, // Pixel operation to be performed during the copy
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cfg_rec_width_i, // Rectangle width configuration
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cfg_rec_height_i, // Rectangle height configuration
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cfg_src_px_addr_i, // Source pixel address configuration
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cfg_src_cl_swp_i, // Source Column/Line-Swap configuration
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cfg_src_x_swp_i, // Source X-Swap configuration
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cfg_src_y_swp_i, // Source Y-Swap configuration
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cfg_transparent_color_i, // Transparent color (for rectangle transparent copy operation)
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display_width_i, // Display width
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gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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gpu_enable_i, // GPU enable
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exec_fill_i, // Rectangle fill on going
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exec_copy_i, // Rectangle copy on going
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exec_copy_trans_i, // Rectangle transparent copy on going
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trig_exec_i, // Trigger rectangle execution
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vid_ram_dout_i, // Video-RAM data input
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vid_ram_dout_rdy_nxt_i // Video-RAM data output ready during next cycle
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);
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// OUTPUTs
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//=========
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output gpu_exec_done_o; // GPU execution done
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output gpu_dma_busy_o; // GPU DMA execution on going
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output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
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output [15:0] vid_ram_din_o; // Video-RAM data
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output vid_ram_wen_o; // Video-RAM write strobe (active low)
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output vid_ram_cen_o; // Video-RAM chip enable (active low)
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// INPUTs
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//=========
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input mclk; // Main system clock
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input puc_rst; // Main system reset
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input [`APIX_MSB:0] cfg_dst_px_addr_i; // Destination pixel address configuration
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input cfg_dst_cl_swp_i; // Destination Column/Line-Swap configuration
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input cfg_dst_x_swp_i; // Destination X-Swap configuration
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input cfg_dst_y_swp_i; // Destination Y-Swap configuration
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input [15:0] cfg_fill_color_i; // Fill color (for rectangle fill operation)
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input [3:0] cfg_pix_op_sel_i; // Pixel operation to be performed during the copy
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input [`LPIX_MSB:0] cfg_rec_width_i; // Rectangle width configuration
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input [`LPIX_MSB:0] cfg_rec_height_i; // Rectangle height configuration
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input [`APIX_MSB:0] cfg_src_px_addr_i; // Source pixel address configuration
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input cfg_src_cl_swp_i; // Source Column/Line-Swap configuration
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input cfg_src_x_swp_i; // Source X-Swap configuration
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input cfg_src_y_swp_i; // Source Y-Swap configuration
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input [15:0] cfg_transparent_color_i; // Transparent color (for rectangle transparent copy operation)
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input [`LPIX_MSB:0] display_width_i; // Display width
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input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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input gpu_enable_i; // GPU enable
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input exec_fill_i; // Rectangle fill on going
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input exec_copy_i; // Rectangle copy on going
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input exec_copy_trans_i; // Rectangle transparent copy on going
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input trig_exec_i; // Trigger rectangle execution
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input [15:0] vid_ram_dout_i; // Video-RAM data input
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input vid_ram_dout_rdy_nxt_i; // Video-RAM data output ready during next cycle
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//=============================================================================
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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// Video modes decoding
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wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
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wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
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wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
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wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
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wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);
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// Pixel operation decoding
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wire pix_op_00 = (cfg_pix_op_sel_i == 4'b0000); // S
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wire pix_op_01 = (cfg_pix_op_sel_i == 4'b0001); // not S
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wire pix_op_02 = (cfg_pix_op_sel_i == 4'b0010); // not D
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wire pix_op_03 = (cfg_pix_op_sel_i == 4'b0011); // S and D
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wire pix_op_04 = (cfg_pix_op_sel_i == 4'b0100); // S or D
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wire pix_op_05 = (cfg_pix_op_sel_i == 4'b0101); // S xor D
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wire pix_op_06 = (cfg_pix_op_sel_i == 4'b0110); // not (S and D)
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wire pix_op_07 = (cfg_pix_op_sel_i == 4'b0111); // not (S or D)
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wire pix_op_08 = (cfg_pix_op_sel_i == 4'b1000); // not (S xor D)
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wire pix_op_09 = (cfg_pix_op_sel_i == 4'b1001); // (not S) and D
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wire pix_op_10 = (cfg_pix_op_sel_i == 4'b1010); // S and (not D)
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wire pix_op_11 = (cfg_pix_op_sel_i == 4'b1011); // (not S) or D
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wire pix_op_12 = (cfg_pix_op_sel_i == 4'b1100); // S or (not D)
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wire pix_op_13 = (cfg_pix_op_sel_i == 4'b1101); // Fill 0 if S not transparent
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wire pix_op_14 = (cfg_pix_op_sel_i == 4'b1110); // Fill 1 if S not transparent
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wire pix_op_15 = (cfg_pix_op_sel_i == 4'b1111); // Fill 'fill_color' if S not transparent
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wire dma_done;
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wire pixel_is_transparent;
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// 16 bits one-hot decoder
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function [15:0] one_hot16;
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input [3:0] binary;
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begin
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one_hot16 = 16'h0000;
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one_hot16[binary] = 1'b1;
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end
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endfunction
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//=============================================================================
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// 2) DMA STATE MACHINE
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//=============================================================================
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// State definition
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parameter IDLE = 3'h0;
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parameter INIT = 3'h1;
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parameter SKIP = 3'h2;
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parameter SRC_READ = 3'h3;
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parameter DST_READ = 3'h4;
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parameter DST_WRITE = 3'h5;
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// State machine
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reg [2:0] dma_state;
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reg [2:0] dma_state_nxt;
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// State arcs
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wire needs_src_read = (exec_copy_i & ~pix_op_02) | exec_copy_trans_i;
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wire needs_dst_read = (exec_fill_i | exec_copy_trans_i | exec_copy_i) & (~(pix_op_00 | pix_op_01 | pix_op_13 | pix_op_14 | pix_op_15) | ~gfx_mode_16_bpp);
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wire needs_dst_write = (exec_fill_i | exec_copy_trans_i | exec_copy_i) & ~pixel_is_transparent;
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wire data_ready_nxt = (dma_state==SRC_READ) |
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(((dma_state==DST_READ) |
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(dma_state==DST_WRITE)) & ~pixel_is_transparent) ? vid_ram_dout_rdy_nxt_i : 1'b1;
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// State transition
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always @(dma_state or trig_exec_i or needs_src_read or needs_dst_read or data_ready_nxt or dma_done or needs_dst_write)
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case (dma_state)
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IDLE : dma_state_nxt = ~trig_exec_i ? IDLE : INIT ;
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INIT : dma_state_nxt = needs_src_read ? SRC_READ :
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needs_dst_read ? DST_READ :
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needs_dst_write ? DST_WRITE : SKIP ;
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SKIP : dma_state_nxt = dma_done ? IDLE : SKIP ;
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SRC_READ : dma_state_nxt = ~data_ready_nxt ? SRC_READ :
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needs_dst_read ? DST_READ : DST_WRITE ;
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DST_READ : dma_state_nxt = ~data_ready_nxt ? DST_READ :
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needs_dst_write ? DST_WRITE :
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dma_done ? IDLE : SRC_READ ;
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DST_WRITE : dma_state_nxt = ~data_ready_nxt ? DST_WRITE :
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dma_done ? IDLE :
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needs_src_read ? SRC_READ :
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needs_dst_read ? DST_READ : DST_WRITE ;
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// pragma coverage off
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default : dma_state_nxt = IDLE;
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// pragma coverage on
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endcase
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// State machine
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) dma_state <= IDLE;
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else if (~gpu_enable_i) dma_state <= IDLE;
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else dma_state <= dma_state_nxt;
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// Utility signals
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wire dma_init = (dma_state==INIT);
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wire dma_pixel_done = (dma_state==SKIP) | ((dma_state==DST_READ) & pixel_is_transparent) |
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((dma_state==DST_WRITE) & data_ready_nxt ) ;
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assign gpu_exec_done_o = (dma_state==IDLE) & ~trig_exec_i;
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assign gpu_dma_busy_o = (dma_state!=IDLE);
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//=============================================================================
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// 3) COUNT TRANSFERS
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//=============================================================================
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reg [`LPIX_MSB:0] height_cnt;
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wire height_cnt_done;
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reg [`LPIX_MSB:0] width_cnt;
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wire width_cnt_done;
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// Height Counter
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wire height_cnt_init = dma_init;
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wire height_cnt_dec = dma_pixel_done & width_cnt_done & ~height_cnt_done;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) height_cnt <= {{`LPIX_MSB{1'h0}},1'b1};
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else if (height_cnt_init) height_cnt <= cfg_rec_height_i;
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else if (height_cnt_dec) height_cnt <= height_cnt-{{`LPIX_MSB{1'h0}},1'b1};
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assign height_cnt_done = (height_cnt=={{`LPIX_MSB{1'h0}}, 1'b1});
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// Width Counter
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wire width_cnt_init = dma_init | height_cnt_dec;
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wire width_cnt_dec = dma_pixel_done & ~width_cnt_done;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) width_cnt <= {{`LPIX_MSB{1'h0}},1'b1};
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else if (width_cnt_init) width_cnt <= cfg_rec_width_i;
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else if (width_cnt_dec) width_cnt <= width_cnt-{{`LPIX_MSB{1'h0}},1'b1};
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assign width_cnt_done = (width_cnt=={{`LPIX_MSB{1'h0}}, 1'b1});
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// DMA Transfer is done when both counters are done
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assign dma_done = height_cnt_done & width_cnt_done;
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//=============================================================================
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// 4) SOURCE ADDRESS GENERATION
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//=============================================================================
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reg [`APIX_MSB:0] vram_src_addr;
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wire [`APIX_MSB:0] vram_src_addr_calc;
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wire vram_src_addr_inc = dma_pixel_done & needs_src_read;
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wire [`APIX_MSB:0] vram_src_addr_nxt = trig_exec_i ? cfg_src_px_addr_i : vram_src_addr_calc;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) vram_src_addr <= {`APIX_MSB+1{1'b0}};
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else if (trig_exec_i | vram_src_addr_inc) vram_src_addr <= vram_src_addr_nxt;
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// Compute the next address
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ogfx_gpu_dma_addr ogfx_gpu_dma_src_addr_inst (
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// OUTPUTs
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.vid_ram_addr_nxt_o ( vram_src_addr_calc ), // Next Video-RAM address
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// INPUTs
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.mclk ( mclk ), // Main system clock
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.puc_rst ( puc_rst ), // Main system reset
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.display_width_i ( display_width_i ), // Display width
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|
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.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
|
305 |
|
|
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
|
306 |
|
|
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
|
307 |
|
|
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
|
308 |
|
|
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
|
309 |
|
|
.vid_ram_addr_i ( vram_src_addr ), // Video-RAM address
|
310 |
|
|
.vid_ram_addr_init_i ( dma_init ), // Video-RAM address initialization
|
311 |
|
|
.vid_ram_addr_step_i ( vram_src_addr_inc ), // Video-RAM address step
|
312 |
|
|
.vid_ram_width_i ( cfg_rec_width_i ), // Video-RAM width
|
313 |
|
|
.vid_ram_win_x_swap_i ( cfg_src_x_swp_i ), // Video-RAM X-Swap configuration
|
314 |
|
|
.vid_ram_win_y_swap_i ( cfg_src_y_swp_i ), // Video-RAM Y-Swap configuration
|
315 |
|
|
.vid_ram_win_cl_swap_i ( cfg_src_cl_swp_i ) // Video-RAM CL-Swap configuration
|
316 |
|
|
);
|
317 |
|
|
|
318 |
|
|
//=============================================================================
|
319 |
|
|
// 5) SOURCE DATA MASK
|
320 |
|
|
//=============================================================================
|
321 |
|
|
|
322 |
|
|
reg [15:0] vram_src_mask;
|
323 |
|
|
wire [15:0] vram_src_mask_shift = one_hot16(vram_src_addr_nxt[3:0]);
|
324 |
|
|
wire [15:0] vram_src_mask_vram_nxt = ({16{gfx_mode_1_bpp }} & vram_src_mask_shift ) |
|
325 |
|
|
({16{gfx_mode_2_bpp }} & {{2{vram_src_mask_shift[14]}},
|
326 |
|
|
{2{vram_src_mask_shift[12]}},
|
327 |
|
|
{2{vram_src_mask_shift[10]}},
|
328 |
|
|
{2{vram_src_mask_shift[8] }},
|
329 |
|
|
{2{vram_src_mask_shift[6] }},
|
330 |
|
|
{2{vram_src_mask_shift[4] }},
|
331 |
|
|
{2{vram_src_mask_shift[2] }},
|
332 |
|
|
{2{vram_src_mask_shift[0] }}}) |
|
333 |
|
|
({16{gfx_mode_4_bpp }} & {{4{vram_src_mask_shift[12]}},
|
334 |
|
|
{4{vram_src_mask_shift[8] }},
|
335 |
|
|
{4{vram_src_mask_shift[4] }},
|
336 |
|
|
{4{vram_src_mask_shift[0] }}}) |
|
337 |
|
|
({16{gfx_mode_8_bpp }} & {{8{vram_src_mask_shift[8] }},
|
338 |
|
|
{8{vram_src_mask_shift[0] }}}) |
|
339 |
|
|
({16{gfx_mode_16_bpp}} & {16{1'b1}} ) ;
|
340 |
|
|
|
341 |
|
|
wire [15:0] vram_src_mask_fill_nxt = ({16{gfx_mode_1_bpp }} & 16'h0001) |
|
342 |
|
|
({16{gfx_mode_2_bpp }} & 16'h0003) |
|
343 |
|
|
({16{gfx_mode_4_bpp }} & 16'h000f) |
|
344 |
|
|
({16{gfx_mode_8_bpp }} & 16'h00ff) |
|
345 |
|
|
({16{gfx_mode_16_bpp}} & 16'hffff) ;
|
346 |
|
|
|
347 |
|
|
wire [15:0] vram_src_mask_nxt = exec_fill_i ? vram_src_mask_fill_nxt :
|
348 |
|
|
vram_src_mask_vram_nxt ;
|
349 |
|
|
|
350 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
351 |
|
|
if (puc_rst) vram_src_mask <= 16'h0000;
|
352 |
|
|
else if (trig_exec_i | vram_src_addr_inc) vram_src_mask <= vram_src_mask_nxt;
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
//=============================================================================
|
356 |
|
|
// 6) DESTINATION ADDRESS GENERATION
|
357 |
|
|
//=============================================================================
|
358 |
|
|
|
359 |
|
|
reg [`APIX_MSB:0] vram_dst_addr;
|
360 |
|
|
wire [`APIX_MSB:0] vram_dst_addr_calc;
|
361 |
|
|
|
362 |
|
|
wire vram_dst_addr_inc = dma_pixel_done;
|
363 |
|
|
wire [`APIX_MSB:0] vram_dst_addr_nxt = trig_exec_i ? cfg_dst_px_addr_i : vram_dst_addr_calc;
|
364 |
|
|
|
365 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
366 |
|
|
if (puc_rst) vram_dst_addr <= {`APIX_MSB+1{1'b0}};
|
367 |
|
|
else if (trig_exec_i | vram_dst_addr_inc) vram_dst_addr <= vram_dst_addr_nxt;
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
// Compute the next address
|
371 |
|
|
ogfx_gpu_dma_addr ogfx_gpu_dma_dst_addr_inst (
|
372 |
|
|
|
373 |
|
|
// OUTPUTs
|
374 |
|
|
.vid_ram_addr_nxt_o ( vram_dst_addr_calc ), // Next Video-RAM address
|
375 |
|
|
|
376 |
|
|
// INPUTs
|
377 |
|
|
.mclk ( mclk ), // Main system clock
|
378 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
379 |
|
|
.display_width_i ( display_width_i ), // Display width
|
380 |
|
|
.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
|
381 |
|
|
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
|
382 |
|
|
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
|
383 |
|
|
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
|
384 |
|
|
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
|
385 |
|
|
.vid_ram_addr_i ( vram_dst_addr ), // Video-RAM address
|
386 |
|
|
.vid_ram_addr_init_i ( dma_init ), // Video-RAM address initialization
|
387 |
|
|
.vid_ram_addr_step_i ( vram_dst_addr_inc ), // Video-RAM address step
|
388 |
|
|
.vid_ram_width_i ( cfg_rec_width_i ), // Video-RAM width
|
389 |
|
|
.vid_ram_win_x_swap_i ( cfg_dst_x_swp_i ), // Video-RAM X-Swap configuration
|
390 |
|
|
.vid_ram_win_y_swap_i ( cfg_dst_y_swp_i ), // Video-RAM Y-Swap configuration
|
391 |
|
|
.vid_ram_win_cl_swap_i ( cfg_dst_cl_swp_i ) // Video-RAM CL-Swap configuration
|
392 |
|
|
);
|
393 |
|
|
|
394 |
|
|
//=============================================================================
|
395 |
|
|
// 7) DESTINATION DATA MASK
|
396 |
|
|
//=============================================================================
|
397 |
|
|
|
398 |
|
|
reg [15:0] vram_dst_mask;
|
399 |
|
|
wire [15:0] vram_dst_mask_shift = one_hot16(vram_dst_addr_nxt[3:0]);
|
400 |
|
|
wire [15:0] vram_dst_mask_nxt = ({16{gfx_mode_1_bpp }} & vram_dst_mask_shift ) |
|
401 |
|
|
({16{gfx_mode_2_bpp }} & {{2{vram_dst_mask_shift[14]}},
|
402 |
|
|
{2{vram_dst_mask_shift[12]}},
|
403 |
|
|
{2{vram_dst_mask_shift[10]}},
|
404 |
|
|
{2{vram_dst_mask_shift[8] }},
|
405 |
|
|
{2{vram_dst_mask_shift[6] }},
|
406 |
|
|
{2{vram_dst_mask_shift[4] }},
|
407 |
|
|
{2{vram_dst_mask_shift[2] }},
|
408 |
|
|
{2{vram_dst_mask_shift[0] }}}) |
|
409 |
|
|
({16{gfx_mode_4_bpp }} & {{4{vram_dst_mask_shift[12]}},
|
410 |
|
|
{4{vram_dst_mask_shift[8] }},
|
411 |
|
|
{4{vram_dst_mask_shift[4] }},
|
412 |
|
|
{4{vram_dst_mask_shift[0] }}}) |
|
413 |
|
|
({16{gfx_mode_8_bpp }} & {{8{vram_dst_mask_shift[8] }},
|
414 |
|
|
{8{vram_dst_mask_shift[0] }}}) |
|
415 |
|
|
({16{gfx_mode_16_bpp}} & {16{1'b1}} ) ;
|
416 |
|
|
|
417 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
418 |
|
|
if (puc_rst) vram_dst_mask <= 16'h0000;
|
419 |
|
|
else if (trig_exec_i | vram_dst_addr_inc) vram_dst_mask <= vram_dst_mask_nxt;
|
420 |
|
|
|
421 |
|
|
|
422 |
|
|
//=============================================================================
|
423 |
|
|
// 8) VIDEO-MEMORY INTERFACE
|
424 |
|
|
//=============================================================================
|
425 |
|
|
|
426 |
|
|
//--------------------------
|
427 |
|
|
// Source data
|
428 |
|
|
//--------------------------
|
429 |
|
|
|
430 |
|
|
// Align source data to destination for lower resolution
|
431 |
|
|
wire [15:0] src_data_mask = ((exec_fill_i ? cfg_fill_color_i : vid_ram_dout_i) & vram_src_mask);
|
432 |
|
|
wire src_data_mask_1_bpp = (|src_data_mask);
|
433 |
|
|
wire [1:0] src_data_mask_2_bpp = {(|{src_data_mask[15], src_data_mask[13], src_data_mask[11], src_data_mask[9], src_data_mask[7], src_data_mask[5], src_data_mask[3], src_data_mask[1]}),
|
434 |
|
|
(|{src_data_mask[14], src_data_mask[12], src_data_mask[10], src_data_mask[8], src_data_mask[6], src_data_mask[4], src_data_mask[2], src_data_mask[0]})};
|
435 |
|
|
wire [3:0] src_data_mask_4_bpp = {(|{src_data_mask[15], src_data_mask[11], src_data_mask[7] , src_data_mask[3]}),
|
436 |
|
|
(|{src_data_mask[14], src_data_mask[10], src_data_mask[6] , src_data_mask[2]}),
|
437 |
|
|
(|{src_data_mask[13], src_data_mask[9] , src_data_mask[5] , src_data_mask[1]}),
|
438 |
|
|
(|{src_data_mask[12], src_data_mask[8] , src_data_mask[4] , src_data_mask[0]})};
|
439 |
|
|
wire [7:0] src_data_mask_8_bpp = {(|{src_data_mask[15], src_data_mask[7]}),
|
440 |
|
|
(|{src_data_mask[14], src_data_mask[6]}),
|
441 |
|
|
(|{src_data_mask[13], src_data_mask[5]}),
|
442 |
|
|
(|{src_data_mask[12], src_data_mask[4]}),
|
443 |
|
|
(|{src_data_mask[11], src_data_mask[3]}),
|
444 |
|
|
(|{src_data_mask[10], src_data_mask[2]}),
|
445 |
|
|
(|{src_data_mask[9] , src_data_mask[1]}),
|
446 |
|
|
(|{src_data_mask[8] , src_data_mask[0]})};
|
447 |
|
|
wire [15:0] src_data_mask_16_bpp = src_data_mask;
|
448 |
|
|
|
449 |
|
|
wire [15:0] src_data_align = ({16{gfx_mode_1_bpp }} & {16{src_data_mask_1_bpp}}) |
|
450 |
|
|
({16{gfx_mode_2_bpp }} & {8{src_data_mask_2_bpp}}) |
|
451 |
|
|
({16{gfx_mode_4_bpp }} & {4{src_data_mask_4_bpp}}) |
|
452 |
|
|
({16{gfx_mode_8_bpp }} & {2{src_data_mask_8_bpp}}) |
|
453 |
|
|
({16{gfx_mode_16_bpp}} & src_data_mask_16_bpp ) ;
|
454 |
|
|
|
455 |
|
|
// Detect read accesses
|
456 |
|
|
reg src_data_ready;
|
457 |
|
|
wire src_data_ready_nxt = ((dma_state==SRC_READ) & data_ready_nxt) | (exec_fill_i & dma_init);
|
458 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
459 |
|
|
if (puc_rst) src_data_ready <= 1'b0;
|
460 |
|
|
else src_data_ready <= src_data_ready_nxt;
|
461 |
|
|
|
462 |
|
|
// Read data buffer
|
463 |
|
|
reg [15:0] src_data_buf;
|
464 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
465 |
|
|
if (puc_rst) src_data_buf <= 16'h0000;
|
466 |
|
|
else if (src_data_ready) src_data_buf <= src_data_align;
|
467 |
|
|
|
468 |
|
|
// Source data
|
469 |
|
|
wire [15:0] src_data = src_data_ready ? src_data_align : src_data_buf;
|
470 |
|
|
|
471 |
|
|
//--------------------------
|
472 |
|
|
// Destination data
|
473 |
|
|
//--------------------------
|
474 |
|
|
|
475 |
|
|
// Detect read access
|
476 |
|
|
reg dst_data_ready;
|
477 |
|
|
wire dst_data_ready_nxt = ((dma_state==DST_READ) & data_ready_nxt);
|
478 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
479 |
|
|
if (puc_rst) dst_data_ready <= 1'b0;
|
480 |
|
|
else dst_data_ready <= dst_data_ready_nxt;
|
481 |
|
|
|
482 |
|
|
// Read data buffer
|
483 |
|
|
reg [15:0] dst_data_buf;
|
484 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
485 |
|
|
if (puc_rst) dst_data_buf <= 16'h0000;
|
486 |
|
|
else if (dst_data_ready) dst_data_buf <= vid_ram_dout_i;
|
487 |
|
|
|
488 |
|
|
// Source data
|
489 |
|
|
wire [15:0] dst_data = dst_data_ready ? vid_ram_dout_i : dst_data_buf;
|
490 |
|
|
|
491 |
|
|
//--------------------------
|
492 |
|
|
// Detect transparency
|
493 |
|
|
//--------------------------
|
494 |
|
|
wire [15:0] transparent_color_align = ({16{gfx_mode_1_bpp }} & {16{cfg_transparent_color_i[0] }}) |
|
495 |
|
|
({16{gfx_mode_2_bpp }} & {8{cfg_transparent_color_i[1:0]}}) |
|
496 |
|
|
({16{gfx_mode_4_bpp }} & {4{cfg_transparent_color_i[3:0]}}) |
|
497 |
|
|
({16{gfx_mode_8_bpp }} & {2{cfg_transparent_color_i[7:0]}}) |
|
498 |
|
|
({16{gfx_mode_16_bpp}} & cfg_transparent_color_i ) ;
|
499 |
|
|
|
500 |
|
|
wire pixel_is_transparent_nxt = ((exec_copy_trans_i & src_data_ready ) |
|
501 |
|
|
(exec_copy_i & src_data_ready & (pix_op_13 | pix_op_14 | pix_op_15)) |
|
502 |
|
|
(exec_fill_i & (pix_op_13 | pix_op_14 | pix_op_15)) ) & (src_data_align==transparent_color_align);
|
503 |
|
|
reg pixel_is_transparent_reg;
|
504 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
505 |
|
|
if (puc_rst) pixel_is_transparent_reg <= 1'b0;
|
506 |
|
|
else if (dma_pixel_done | (dma_state==IDLE)) pixel_is_transparent_reg <= 1'b0;
|
507 |
|
|
else if (pixel_is_transparent_nxt) pixel_is_transparent_reg <= 1'b1;
|
508 |
|
|
|
509 |
|
|
assign pixel_is_transparent = (pixel_is_transparent_nxt | pixel_is_transparent_reg);
|
510 |
|
|
|
511 |
|
|
//--------------------------
|
512 |
|
|
// Pixel operation
|
513 |
|
|
//--------------------------
|
514 |
|
|
wire [15:0] fill_color_align = ({16{gfx_mode_1_bpp }} & {16{cfg_fill_color_i[0] }}) |
|
515 |
|
|
({16{gfx_mode_2_bpp }} & {8{cfg_fill_color_i[1:0]}}) |
|
516 |
|
|
({16{gfx_mode_4_bpp }} & {4{cfg_fill_color_i[3:0]}}) |
|
517 |
|
|
({16{gfx_mode_8_bpp }} & {2{cfg_fill_color_i[7:0]}}) |
|
518 |
|
|
({16{gfx_mode_16_bpp}} & cfg_fill_color_i ) ;
|
519 |
|
|
|
520 |
|
|
wire [15:0] pixel_data = ({16{pix_op_00}} & ( src_data )) | // S
|
521 |
|
|
({16{pix_op_01}} & (~src_data )) | // not S
|
522 |
|
|
({16{pix_op_02}} & ( ~dst_data)) | // not D
|
523 |
|
|
|
524 |
|
|
({16{pix_op_03}} & ( src_data & dst_data)) | // S and D
|
525 |
|
|
({16{pix_op_04}} & ( src_data | dst_data)) | // S or D
|
526 |
|
|
({16{pix_op_05}} & ( src_data ^ dst_data)) | // S xor D
|
527 |
|
|
|
528 |
|
|
({16{pix_op_06}} & ~( src_data & dst_data)) | // not (S and D)
|
529 |
|
|
({16{pix_op_07}} & ~( src_data | dst_data)) | // not (S or D)
|
530 |
|
|
({16{pix_op_08}} & ~( src_data ^ dst_data)) | // not (S xor D)
|
531 |
|
|
|
532 |
|
|
({16{pix_op_09}} & (~src_data & dst_data)) | // (not S) and D
|
533 |
|
|
({16{pix_op_10}} & ( src_data & ~dst_data)) | // S and (not D)
|
534 |
|
|
({16{pix_op_11}} & (~src_data | dst_data)) | // (not S) or D
|
535 |
|
|
({16{pix_op_12}} & ( src_data | ~dst_data)) | // S or (not D)
|
536 |
|
|
|
537 |
|
|
({16{pix_op_13}} & ( 16'h0000 )) | // Fill 0 if S not transparent
|
538 |
|
|
({16{pix_op_14}} & ( 16'hffff )) | // Fill 1 if S not transparent
|
539 |
|
|
({16{pix_op_15}} & ( fill_color_align )) ; // Fill 'fill_color' if S not transparent
|
540 |
|
|
|
541 |
|
|
|
542 |
|
|
|
543 |
|
|
// RAM interface
|
544 |
|
|
assign vid_ram_din_o = (pixel_data & vram_dst_mask) | (dst_data & ~vram_dst_mask);
|
545 |
|
|
|
546 |
|
|
assign vid_ram_addr_o = (dma_state==SRC_READ) ? vram_src_addr[`APIX_MSB:4] :
|
547 |
|
|
vram_dst_addr[`APIX_MSB:4] ;
|
548 |
|
|
|
549 |
|
|
assign vid_ram_wen_o = ~( (dma_state==DST_WRITE) & ~pixel_is_transparent) ;
|
550 |
|
|
|
551 |
|
|
assign vid_ram_cen_o = ~( (dma_state==SRC_READ) |
|
552 |
|
|
((dma_state==DST_READ) & ~pixel_is_transparent) |
|
553 |
|
|
((dma_state==DST_WRITE) & ~pixel_is_transparent));
|
554 |
|
|
|
555 |
|
|
|
556 |
|
|
endmodule // ogfx_gpu_dma
|
557 |
|
|
|
558 |
|
|
`ifdef OGFX_NO_INCLUDE
|
559 |
|
|
`else
|
560 |
|
|
`include "openGFX430_undefines.v"
|
561 |
|
|
`endif
|