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[/] [opengfx430/] [trunk/] [core/] [rtl/] [verilog/] [ogfx_ram_arbiter.v] - Blame information for rev 3

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1 3 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ogfx_ram_arbiter.v
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//
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// *Module Description:
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//                      RAM arbiter for LUT and VIDEO memories
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//                      LUT-RAM arbitration:
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//
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//                              - Software interface: fixed highest priority
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//                              - Refresh  interface: fixed lowest priority
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//
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//                      Video-RAM arbitration:
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//
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//                              - Software interface: fixed highest priority
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//                              - Refresh  interface: round-robin with GPIO if
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//                              - GPU      interface: round-robin with Refresh if
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module  ogfx_ram_arbiter (
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    mclk,                                                // Main system clock
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    puc_rst,                                             // Main system reset
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   //------------------------------------------------------------
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   // SW interface, fixed highest priority
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    lut_ram_sw_addr_i,                                   // LUT-RAM Software address
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    lut_ram_sw_din_i,                                    // LUT-RAM Software data
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    lut_ram_sw_wen_i,                                    // LUT-RAM Software write strobe (active low)
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    lut_ram_sw_cen_i,                                    // LUT-RAM Software chip enable (active low)
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    lut_ram_sw_dout_o,                                   // LUT-RAM Software data input
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   // Refresh-backend, fixed lowest priority
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    lut_ram_refr_addr_i,                                 // LUT-RAM Refresh address
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    lut_ram_refr_din_i,                                  // LUT-RAM Refresh data
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    lut_ram_refr_wen_i,                                  // LUT-RAM Refresh write strobe (active low)
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    lut_ram_refr_cen_i,                                  // LUT-RAM Refresh enable (active low)
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    lut_ram_refr_dout_o,                                 // LUT-RAM Refresh data output
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    lut_ram_refr_dout_rdy_nxt_o,                         // LUT-RAM Refresh data output ready during next cycle
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   // LUT Memory interface
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    lut_ram_addr_o,                                      // LUT-RAM address
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    lut_ram_din_o,                                       // LUT-RAM data
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    lut_ram_wen_o,                                       // LUT-RAM write strobe (active low)
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    lut_ram_cen_o,                                       // LUT-RAM chip enable (active low)
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    lut_ram_dout_i,                                      // LUT-RAM data input
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   //------------------------------------------------------------
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   // SW interface, fixed highest priority
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    vid_ram_sw_addr_i,                                   // Video-RAM Software address
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    vid_ram_sw_din_i,                                    // Video-RAM Software data
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    vid_ram_sw_wen_i,                                    // Video-RAM Software write strobe (active low)
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    vid_ram_sw_cen_i,                                    // Video-RAM Software chip enable (active low)
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    vid_ram_sw_dout_o,                                   // Video-RAM Software data input
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   // GPU interface (round-robin with refresh-backend)
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    vid_ram_gpu_addr_i,                                  // Video-RAM GPU address
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    vid_ram_gpu_din_i,                                   // Video-RAM GPU data
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    vid_ram_gpu_wen_i,                                   // Video-RAM GPU write strobe (active low)
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    vid_ram_gpu_cen_i,                                   // Video-RAM GPU chip enable (active low)
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    vid_ram_gpu_dout_o,                                  // Video-RAM GPU data input
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    vid_ram_gpu_dout_rdy_nxt_o,                          // Video-RAM GPU data output ready during next cycle
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   // Refresh-backend (round-robin with GPU interface)
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    vid_ram_refr_addr_i,                                 // Video-RAM Refresh address
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    vid_ram_refr_din_i,                                  // Video-RAM Refresh data
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    vid_ram_refr_wen_i,                                  // Video-RAM Refresh write strobe (active low)
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    vid_ram_refr_cen_i,                                  // Video-RAM Refresh enable (active low)
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    vid_ram_refr_dout_o,                                 // Video-RAM Refresh data output
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    vid_ram_refr_dout_rdy_nxt_o,                         // Video-RAM Refresh data output ready during next cycle
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   // Video Memory interface
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    vid_ram_addr_o,                                      // Video-RAM address
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    vid_ram_din_o,                                       // Video-RAM data
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    vid_ram_wen_o,                                       // Video-RAM write strobe (active low)
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    vid_ram_cen_o,                                       // Video-RAM chip enable (active low)
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    vid_ram_dout_i                                       // Video-RAM data input
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   //------------------------------------------------------------
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);
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// CLOCK/RESET
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//=============
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input                mclk;                               // Main system clock
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input                puc_rst;                            // Main system reset
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// LUT MEMORY
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//=============
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// SW interface, fixed highest priority
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input  [`LRAM_MSB:0] lut_ram_sw_addr_i;                  // LUT-RAM Software address
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input         [15:0] lut_ram_sw_din_i;                   // LUT-RAM Software data
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input                lut_ram_sw_wen_i;                   // LUT-RAM Software write strobe (active low)
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input                lut_ram_sw_cen_i;                   // LUT-RAM Software chip enable (active low)
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output        [15:0] lut_ram_sw_dout_o;                  // LUT-RAM Software data input
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// Refresh-backend, fixed lowest priority
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input  [`LRAM_MSB:0] lut_ram_refr_addr_i;                // LUT-RAM Refresh address
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input         [15:0] lut_ram_refr_din_i;                 // LUT-RAM Refresh data
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input                lut_ram_refr_wen_i;                 // LUT-RAM Refresh write strobe (active low)
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input                lut_ram_refr_cen_i;                 // LUT-RAM Refresh enable (active low)
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output        [15:0] lut_ram_refr_dout_o;                // LUT-RAM Refresh data output
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output               lut_ram_refr_dout_rdy_nxt_o;        // LUT-RAM Refresh data output ready during next cycle
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// LUT Memory interface
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output [`LRAM_MSB:0] lut_ram_addr_o;                     // LUT-RAM address
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output        [15:0] lut_ram_din_o;                      // LUT-RAM data
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output               lut_ram_wen_o;                      // LUT-RAM write strobe (active low)
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output               lut_ram_cen_o;                      // LUT-RAM chip enable (active low)
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input         [15:0] lut_ram_dout_i;                     // LUT-RAM data input
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// VIDEO MEMORY
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//==============
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// SW interface, fixed highest priority
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input  [`VRAM_MSB:0] vid_ram_sw_addr_i;                  // Video-RAM Software address
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input         [15:0] vid_ram_sw_din_i;                   // Video-RAM Software data
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input                vid_ram_sw_wen_i;                   // Video-RAM Software write strobe (active low)
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input                vid_ram_sw_cen_i;                   // Video-RAM Software chip enable (active low)
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output        [15:0] vid_ram_sw_dout_o;                  // Video-RAM Software data input
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// GPU interface (round-robin with refresh-backend)
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input  [`VRAM_MSB:0] vid_ram_gpu_addr_i;                 // Video-RAM GPU address
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input         [15:0] vid_ram_gpu_din_i;                  // Video-RAM GPU data
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input                vid_ram_gpu_wen_i;                  // Video-RAM GPU write strobe (active low)
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input                vid_ram_gpu_cen_i;                  // Video-RAM GPU chip enable (active low)
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output        [15:0] vid_ram_gpu_dout_o;                 // Video-RAM GPU data input
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output               vid_ram_gpu_dout_rdy_nxt_o;         // Video-RAM GPU data output ready during next cycle
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// Refresh-backend (round-robin with GPU interface)
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input  [`VRAM_MSB:0] vid_ram_refr_addr_i;                // Video-RAM Refresh address
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input         [15:0] vid_ram_refr_din_i;                 // Video-RAM Refresh data
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input                vid_ram_refr_wen_i;                 // Video-RAM Refresh write strobe (active low)
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input                vid_ram_refr_cen_i;                 // Video-RAM Refresh enable (active low)
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output        [15:0] vid_ram_refr_dout_o;                // Video-RAM Refresh data output
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output               vid_ram_refr_dout_rdy_nxt_o;        // Video-RAM Refresh data output ready during next cycle
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// Video Memory interface
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output [`VRAM_MSB:0] vid_ram_addr_o;                     // Video-RAM address
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output        [15:0] vid_ram_din_o;                      // Video-RAM data
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output               vid_ram_wen_o;                      // Video-RAM write strobe (active low)
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output               vid_ram_cen_o;                      // Video-RAM chip enable (active low)
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input         [15:0] vid_ram_dout_i;                     // Video-RAM data input
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//=============================================================================
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// 1)  WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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reg     gpu_is_last_owner;
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//=============================================================================
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// 2) LUT MEMORY ARBITER
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//=============================================================================
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// Arbitration signals
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wire    sw_lram_access_granted       = ~lut_ram_sw_cen_i;
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wire    refr_lram_access_granted     = ~sw_lram_access_granted & ~lut_ram_refr_cen_i;
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// LUT RAM signal muxing
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assign  lut_ram_sw_dout_o            =  lut_ram_dout_i;
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assign  lut_ram_refr_dout_o          =  lut_ram_dout_i;
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assign  lut_ram_refr_dout_rdy_nxt_o  =  refr_lram_access_granted;
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assign  lut_ram_addr_o               = ({`LRAM_AWIDTH{ sw_lram_access_granted  }} & lut_ram_sw_addr_i  ) |
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                                       ({`LRAM_AWIDTH{ refr_lram_access_granted}} & lut_ram_refr_addr_i) ;
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assign  lut_ram_din_o                = ({          16{ sw_lram_access_granted  }} & lut_ram_sw_din_i   ) |
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                                       ({          16{ refr_lram_access_granted}} & lut_ram_refr_din_i ) ;
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assign  lut_ram_wen_o                = (              ~sw_lram_access_granted     | lut_ram_sw_wen_i   ) &
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                                       (              ~refr_lram_access_granted   | lut_ram_refr_wen_i ) ;
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assign  lut_ram_cen_o                =  lut_ram_sw_cen_i & lut_ram_refr_cen_i;
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//=============================================================================
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// 3) VIDEO MEMORY ARBITER
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//=============================================================================
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// Arbitration signals
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wire sw_vram_access_granted   = ~vid_ram_sw_cen_i;
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wire gpu_vram_access_granted  = ~sw_vram_access_granted &                                           // No SW access
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                                ((~vid_ram_gpu_cen_i &  vid_ram_refr_cen_i)                       | // GPU requests alone
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                                 (~vid_ram_gpu_cen_i & ~vid_ram_refr_cen_i & ~gpu_is_last_owner)) ; // GPU & REFR both requests (arbitration required)
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wire refr_vram_access_granted = ~sw_vram_access_granted &                                           // No SW access
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                                (( vid_ram_gpu_cen_i & ~vid_ram_refr_cen_i)                       | // GPU requests alone
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                                 (~vid_ram_gpu_cen_i & ~vid_ram_refr_cen_i &  gpu_is_last_owner)) ; // GPU & REFR both requests (arbitration required)
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// Detect who was the last to own the RAM between the GPU and Refresh interface
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always @ (posedge mclk or posedge puc_rst)
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  if (puc_rst)                       gpu_is_last_owner <=  1'b0;
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  else if (gpu_vram_access_granted ) gpu_is_last_owner <=  1'b1;
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  else if (refr_vram_access_granted) gpu_is_last_owner <=  1'b0;
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// Video RAM signal muxing
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assign  vid_ram_sw_dout_o            = vid_ram_dout_i;
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assign  vid_ram_gpu_dout_o           = vid_ram_dout_i;
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assign  vid_ram_gpu_dout_rdy_nxt_o   = gpu_vram_access_granted;
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assign  vid_ram_refr_dout_o          = vid_ram_dout_i;
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assign  vid_ram_refr_dout_rdy_nxt_o  = refr_vram_access_granted;
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assign  vid_ram_addr_o               = ({`VRAM_AWIDTH{ sw_vram_access_granted  }} & vid_ram_sw_addr_i  ) |
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                                       ({`VRAM_AWIDTH{ gpu_vram_access_granted }} & vid_ram_gpu_addr_i ) |
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                                       ({`VRAM_AWIDTH{ refr_vram_access_granted}} & vid_ram_refr_addr_i) ;
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assign  vid_ram_din_o                = ({          16{ sw_vram_access_granted  }} & vid_ram_sw_din_i   ) |
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                                       ({          16{ gpu_vram_access_granted }} & vid_ram_gpu_din_i  ) |
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                                       ({          16{ refr_vram_access_granted}} & vid_ram_refr_din_i ) ;
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assign  vid_ram_wen_o                = (              ~sw_vram_access_granted     | vid_ram_sw_wen_i   ) &
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                                       (              ~gpu_vram_access_granted    | vid_ram_gpu_wen_i  ) &
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                                       (              ~refr_vram_access_granted   | vid_ram_refr_wen_i ) ;
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assign  vid_ram_cen_o                = vid_ram_sw_cen_i & vid_ram_gpu_cen_i & vid_ram_refr_cen_i;
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endmodule // ogfx_ram_arbiter
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_undefines.v"
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`endif

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