Subversion Repositories opengfx430

//----------------------------------------------------------------------------

// Copyright (C) 2015 Authors

//

// This source file may be used and distributed without restriction provided

// that this copyright statement is not removed from the file and that any

// derivative work contains the original copyright notice and the associated

// disclaimer.

//

// This source file is free software; you can redistribute it and/or modify

// it under the terms of the GNU Lesser General Public License as published

// by the Free Software Foundation; either version 2.1 of the License, or

// (at your option) any later version.

//

// This source is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public

// License for more details.

//

// You should have received a copy of the GNU Lesser General Public License

// along with this source; if not, write to the Free Software Foundation,

// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

//

//----------------------------------------------------------------------------

//

// *File Name: ogfx_reg.v

//

// *Module Description:

//                      Registers for oMSP programming.

//

// *Author(s):

//              - Olivier Girard,    olgirard@gmail.com

//

//----------------------------------------------------------------------------

// $Rev$

// $LastChangedBy$

// $LastChangedDate$

//----------------------------------------------------------------------------

`ifdef OGFX_NO_INCLUDE

`else

`include "openGFX430_defines.v"

`endif

module  ogfx_reg (

// OUTPUTs

    irq_gfx_o,                                 // Graphic Controller interrupt

    gpu_data_o,                                // GPU data

    gpu_data_avail_o,                          // GPU data available

    gpu_enable_o,                              // GPU enable

    lt24_reset_n_o,                            // LT24 Reset (Active Low)

    lt24_on_o,                                 // LT24 on/off

    lt24_cfg_clk_o,                            // LT24 Interface clock configuration

    lt24_cfg_refr_o,                           // LT24 Interface refresh configuration

    lt24_cfg_refr_sync_en_o,                   // LT24 Interface refresh sync enable configuration

    lt24_cfg_refr_sync_val_o,                  // LT24 Interface refresh sync value configuration

    lt24_cmd_refr_o,                           // LT24 Interface refresh command

    lt24_cmd_val_o,                            // LT24 Generic command value

    lt24_cmd_has_param_o,                      // LT24 Generic command has parameters

    lt24_cmd_param_o,                          // LT24 Generic command parameter value

    lt24_cmd_param_rdy_o,                      // LT24 Generic command trigger

    lt24_cmd_dfill_o,                          // LT24 Data fill value

    lt24_cmd_dfill_wr_o,                       // LT24 Data fill trigger

    display_width_o,                           // Display width

    display_height_o,                          // Display height

    display_size_o,                            // Display size (number of pixels)

    display_y_swap_o,                          // Display configuration: swap Y axis (horizontal symmetry)

    display_x_swap_o,                          // Display configuration: swap X axis (vertical symmetry)

    display_cl_swap_o,                         // Display configuration: swap column/lines

    gfx_mode_o,                                // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)

    per_dout_o,                                // Peripheral data output

    refresh_frame_addr_o,                      // Refresh frame base address

    hw_lut_palette_sel_o,                      // Hardware LUT palette configuration

    hw_lut_bgcolor_o,                          // Hardware LUT background-color selection

    hw_lut_fgcolor_o,                          // Hardware LUT foreground-color selection

    sw_lut_enable_o,                           // Refresh LUT-RAM enable

    sw_lut_bank_select_o,                      // Refresh LUT-RAM bank selection

`ifdef WITH_PROGRAMMABLE_LUT

    lut_ram_addr_o,                            // LUT-RAM address

    lut_ram_din_o,                             // LUT-RAM data

    lut_ram_wen_o,                             // LUT-RAM write strobe (active low)

    lut_ram_cen_o,                             // LUT-RAM chip enable (active low)

`endif

    vid_ram_addr_o,                            // Video-RAM address

    vid_ram_din_o,                             // Video-RAM data

    vid_ram_wen_o,                             // Video-RAM write strobe (active low)

    vid_ram_cen_o,                             // Video-RAM chip enable (active low)

// INPUTs

    dbg_freeze_i,                              // Freeze address auto-incr on read

    gpu_cmd_done_evt_i,                        // GPU command done event

    gpu_cmd_error_evt_i,                       // GPU command error event

    gpu_dma_busy_i,                            // GPU DMA execution on going

    gpu_get_data_i,                            // GPU get next data

    lt24_status_i,                             // LT24 FSM Status

    lt24_start_evt_i,                          // LT24 FSM is starting

    lt24_done_evt_i,                           // LT24 FSM is done

    mclk,                                      // Main system clock

    per_addr_i,                                // Peripheral address

    per_din_i,                                 // Peripheral data input

    per_en_i,                                  // Peripheral enable (high active)

    per_we_i,                                  // Peripheral write enable (high active)

    puc_rst,                                   // Main system reset

`ifdef WITH_PROGRAMMABLE_LUT

    lut_ram_dout_i,                            // LUT-RAM data input

`endif

    vid_ram_dout_i                             // Video-RAM data input

);

// PARAMETERs

//============

parameter     [14:0] BASE_ADDR = 15'h0200;     // Register base address

                                               //  - 7 LSBs must stay cleared: 0x0080, 0x0100,

                                               //                              0x0180, 0x0200,

                                               //                              0x0280, ...

// OUTPUTs

//============

output               irq_gfx_o;                // Graphic Controller interrupt

output        [15:0] gpu_data_o;               // GPU data

output               gpu_data_avail_o;         // GPU data available

output               gpu_enable_o;             // GPU enable

output               lt24_reset_n_o;           // LT24 Reset (Active Low)

output               lt24_on_o;                // LT24 on/off

output         [2:0] lt24_cfg_clk_o;           // LT24 Interface clock configuration

output        [11:0] lt24_cfg_refr_o;          // LT24 Interface refresh configuration

output               lt24_cfg_refr_sync_en_o;  // LT24 Interface refresh sync configuration

output         [9:0] lt24_cfg_refr_sync_val_o; // LT24 Interface refresh sync value configuration

output               lt24_cmd_refr_o;          // LT24 Interface refresh command

output         [7:0] lt24_cmd_val_o;           // LT24 Generic command value

output               lt24_cmd_has_param_o;     // LT24 Generic command has parameters

output        [15:0] lt24_cmd_param_o;         // LT24 Generic command parameter value

output               lt24_cmd_param_rdy_o;     // LT24 Generic command trigger

output        [15:0] lt24_cmd_dfill_o;         // LT24 Data fill value

output               lt24_cmd_dfill_wr_o;      // LT24 Data fill trigger

output [`LPIX_MSB:0] display_width_o;          // Display width

output [`LPIX_MSB:0] display_height_o;         // Display height

output [`SPIX_MSB:0] display_size_o;           // Display size (number of pixels)

output               display_y_swap_o;         // Display configuration: swap Y axis (horizontal symmetry)

output               display_x_swap_o;         // Display configuration: swap X axis (vertical symmetry)

output               display_cl_swap_o;        // Display configuration: swap column/lines

output         [2:0] gfx_mode_o;               // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)

output        [15:0] per_dout_o;               // Peripheral data output

output [`APIX_MSB:0] refresh_frame_addr_o;     // Refresh frame base address

output         [2:0] hw_lut_palette_sel_o;     // Hardware LUT palette configuration

output         [3:0] hw_lut_bgcolor_o;         // Hardware LUT background-color selection

output         [3:0] hw_lut_fgcolor_o;         // Hardware LUT foreground-color selection

output               sw_lut_enable_o;          // Refresh LUT-RAM enable

output               sw_lut_bank_select_o;     // Refresh LUT-RAM bank selection

`ifdef WITH_PROGRAMMABLE_LUT

output [`LRAM_MSB:0] lut_ram_addr_o;           // LUT-RAM address

output        [15:0] lut_ram_din_o;            // LUT-RAM data

output               lut_ram_wen_o;            // LUT-RAM write strobe (active low)

output               lut_ram_cen_o;            // LUT-RAM chip enable (active low)

`endif

output [`VRAM_MSB:0] vid_ram_addr_o;           // Video-RAM address

output        [15:0] vid_ram_din_o;            // Video-RAM data

output               vid_ram_wen_o;            // Video-RAM write strobe (active low)

output               vid_ram_cen_o;            // Video-RAM chip enable (active low)

// INPUTs

//============

input                dbg_freeze_i;             // Freeze address auto-incr on read

input                gpu_cmd_done_evt_i;       // GPU command done event

input                gpu_cmd_error_evt_i;      // GPU command error event

input                gpu_dma_busy_i;           // GPU DMA execution on going

input                gpu_get_data_i;           // GPU get next data

input          [4:0] lt24_status_i;            // LT24 FSM Status

input                lt24_start_evt_i;         // LT24 FSM is starting

input                lt24_done_evt_i;          // LT24 FSM is done

input                mclk;                     // Main system clock

input         [13:0] per_addr_i;               // Peripheral address

input         [15:0] per_din_i;                // Peripheral data input

input                per_en_i;                 // Peripheral enable (high active)

input          [1:0] per_we_i;                 // Peripheral write enable (high active)

input                puc_rst;                  // Main system reset

`ifdef WITH_PROGRAMMABLE_LUT

input         [15:0] lut_ram_dout_i;           // LUT-RAM data input

`endif

input         [15:0] vid_ram_dout_i;           // Video-RAM data input

//=============================================================================

// 1)  PARAMETER DECLARATION

//=============================================================================

// Decoder bit width (defines how many bits are considered for address decoding)

parameter              DEC_WD              =  7;

// Register addresses offset

parameter [DEC_WD-1:0] GFX_CTRL            = 'h00,  // General control/status/irq

                       GFX_STATUS          = 'h08,

                       GFX_IRQ             = 'h0A,

                       DISPLAY_WIDTH       = 'h10,  // Display configuration

                       DISPLAY_HEIGHT      = 'h12,

                       DISPLAY_SIZE_LO     = 'h14,

                       DISPLAY_SIZE_HI     = 'h16,

                       DISPLAY_CFG         = 'h18,

                       DISPLAY_REFR_CNT    = 'h1A,

                       LT24_CFG            = 'h20,  // LT24 configuration and Generic command sending

                       LT24_REFRESH        = 'h22,

                       LT24_REFRESH_SYNC   = 'h24,

                       LT24_CMD            = 'h26,

                       LT24_CMD_PARAM      = 'h28,

                       LT24_CMD_DFILL      = 'h2A,

                       LT24_STATUS         = 'h2C,

                       LUT_CFG             = 'h30,  // LUT Configuration & Memory Access Gate

                       LUT_RAM_ADDR        = 'h32,

                       LUT_RAM_DATA        = 'h34,

                       FRAME_SELECT        = 'h3E,  // Frame pointers and selection

                       FRAME0_PTR_LO       = 'h40,

                       FRAME0_PTR_HI       = 'h42,

                       FRAME1_PTR_LO       = 'h44,

                       FRAME1_PTR_HI       = 'h46,

                       FRAME2_PTR_LO       = 'h48,

                       FRAME2_PTR_HI       = 'h4A,

                       FRAME3_PTR_LO       = 'h4C,

                       FRAME3_PTR_HI       = 'h4E,

                       VID_RAM0_CFG        = 'h50,  // First Video Memory Access Gate

                       VID_RAM0_WIDTH      = 'h52,

                       VID_RAM0_ADDR_LO    = 'h54,

                       VID_RAM0_ADDR_HI    = 'h56,

                       VID_RAM0_DATA       = 'h58,

                       VID_RAM1_CFG        = 'h60,  // Second Video Memory Access Gate

                       VID_RAM1_WIDTH      = 'h62,

                       VID_RAM1_ADDR_LO    = 'h64,

                       VID_RAM1_ADDR_HI    = 'h66,

                       VID_RAM1_DATA       = 'h68,

                       GPU_CMD_LO          = 'h70,  // Graphic Processing Unit

                       GPU_CMD_HI          = 'h72,

                       GPU_STAT            = 'h74;

// Register one-hot decoder utilities

parameter              DEC_SZ              =  (1 << DEC_WD);

parameter [DEC_SZ-1:0] BASE_REG            =  {{DEC_SZ-1{1'b0}}, 1'b1};

// Register one-hot decoder

parameter [DEC_SZ-1:0] GFX_CTRL_D          = (BASE_REG << GFX_CTRL          ),

                       GFX_STATUS_D        = (BASE_REG << GFX_STATUS        ),

                       GFX_IRQ_D           = (BASE_REG << GFX_IRQ           ),

                       DISPLAY_WIDTH_D     = (BASE_REG << DISPLAY_WIDTH     ),

                       DISPLAY_HEIGHT_D    = (BASE_REG << DISPLAY_HEIGHT    ),

                       DISPLAY_SIZE_LO_D   = (BASE_REG << DISPLAY_SIZE_LO   ),

                       DISPLAY_SIZE_HI_D   = (BASE_REG << DISPLAY_SIZE_HI   ),

                       DISPLAY_CFG_D       = (BASE_REG << DISPLAY_CFG       ),

                       DISPLAY_REFR_CNT_D  = (BASE_REG << DISPLAY_REFR_CNT  ),

                       LT24_CFG_D          = (BASE_REG << LT24_CFG          ),

                       LT24_REFRESH_D      = (BASE_REG << LT24_REFRESH      ),

                       LT24_REFRESH_SYNC_D = (BASE_REG << LT24_REFRESH_SYNC ),

                       LT24_CMD_D          = (BASE_REG << LT24_CMD          ),

                       LT24_CMD_PARAM_D    = (BASE_REG << LT24_CMD_PARAM    ),

                       LT24_CMD_DFILL_D    = (BASE_REG << LT24_CMD_DFILL    ),

                       LT24_STATUS_D       = (BASE_REG << LT24_STATUS       ),

                       LUT_CFG_D           = (BASE_REG << LUT_CFG           ),

                       LUT_RAM_ADDR_D      = (BASE_REG << LUT_RAM_ADDR      ),

                       LUT_RAM_DATA_D      = (BASE_REG << LUT_RAM_DATA      ),

                       FRAME_SELECT_D      = (BASE_REG << FRAME_SELECT      ),

                       FRAME0_PTR_LO_D     = (BASE_REG << FRAME0_PTR_LO     ),

                       FRAME0_PTR_HI_D     = (BASE_REG << FRAME0_PTR_HI     ),

                       FRAME1_PTR_LO_D     = (BASE_REG << FRAME1_PTR_LO     ),

                       FRAME1_PTR_HI_D     = (BASE_REG << FRAME1_PTR_HI     ),

                       FRAME2_PTR_LO_D     = (BASE_REG << FRAME2_PTR_LO     ),

                       FRAME2_PTR_HI_D     = (BASE_REG << FRAME2_PTR_HI     ),

                       FRAME3_PTR_LO_D     = (BASE_REG << FRAME3_PTR_LO     ),

                       FRAME3_PTR_HI_D     = (BASE_REG << FRAME3_PTR_HI     ),

                       VID_RAM0_CFG_D      = (BASE_REG << VID_RAM0_CFG      ),

                       VID_RAM0_WIDTH_D    = (BASE_REG << VID_RAM0_WIDTH    ),

                       VID_RAM0_ADDR_LO_D  = (BASE_REG << VID_RAM0_ADDR_LO  ),

                       VID_RAM0_ADDR_HI_D  = (BASE_REG << VID_RAM0_ADDR_HI  ),

                       VID_RAM0_DATA_D     = (BASE_REG << VID_RAM0_DATA     ),

                       VID_RAM1_CFG_D      = (BASE_REG << VID_RAM1_CFG      ),

                       VID_RAM1_WIDTH_D    = (BASE_REG << VID_RAM1_WIDTH    ),

                       VID_RAM1_ADDR_LO_D  = (BASE_REG << VID_RAM1_ADDR_LO  ),

                       VID_RAM1_ADDR_HI_D  = (BASE_REG << VID_RAM1_ADDR_HI  ),

                       VID_RAM1_DATA_D     = (BASE_REG << VID_RAM1_DATA     ),

                       GPU_CMD_LO_D        = (BASE_REG << GPU_CMD_LO        ),

                       GPU_CMD_HI_D        = (BASE_REG << GPU_CMD_HI        ),

                       GPU_STAT_D          = (BASE_REG << GPU_STAT          );

//============================================================================

// 2)  REGISTER DECODER

//============================================================================

// Local register selection

wire               reg_sel   =  per_en_i & (per_addr_i[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);

// Register local address

wire  [DEC_WD-1:0] reg_addr  =  {per_addr_i[DEC_WD-2:0], 1'b0};

// Register address decode

wire  [DEC_SZ-1:0] reg_dec   =  (GFX_CTRL_D          &  {DEC_SZ{(reg_addr == GFX_CTRL          )}})  |

                                (GFX_STATUS_D        &  {DEC_SZ{(reg_addr == GFX_STATUS        )}})  |

                                (GFX_IRQ_D           &  {DEC_SZ{(reg_addr == GFX_IRQ           )}})  |

                                (DISPLAY_WIDTH_D     &  {DEC_SZ{(reg_addr == DISPLAY_WIDTH     )}})  |

                                (DISPLAY_HEIGHT_D    &  {DEC_SZ{(reg_addr == DISPLAY_HEIGHT    )}})  |

                                (DISPLAY_SIZE_LO_D   &  {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO   )}})  |

                                (DISPLAY_SIZE_HI_D   &  {DEC_SZ{(reg_addr == DISPLAY_SIZE_HI   )}})  |

                                (DISPLAY_CFG_D       &  {DEC_SZ{(reg_addr == DISPLAY_CFG       )}})  |

                                (DISPLAY_REFR_CNT_D  &  {DEC_SZ{(reg_addr == DISPLAY_REFR_CNT  )}})  |

                                (LT24_CFG_D          &  {DEC_SZ{(reg_addr == LT24_CFG          )}})  |

                                (LT24_REFRESH_D      &  {DEC_SZ{(reg_addr == LT24_REFRESH      )}})  |

                                (LT24_REFRESH_SYNC_D &  {DEC_SZ{(reg_addr == LT24_REFRESH_SYNC )}})  |

                                (LT24_CMD_D          &  {DEC_SZ{(reg_addr == LT24_CMD          )}})  |

                                (LT24_CMD_PARAM_D    &  {DEC_SZ{(reg_addr == LT24_CMD_PARAM    )}})  |

                                (LT24_CMD_DFILL_D    &  {DEC_SZ{(reg_addr == LT24_CMD_DFILL    )}})  |

                                (LT24_STATUS_D       &  {DEC_SZ{(reg_addr == LT24_STATUS       )}})  |

                                (LUT_CFG_D           &  {DEC_SZ{(reg_addr == LUT_CFG           )}})  |

                                (LUT_RAM_ADDR_D      &  {DEC_SZ{(reg_addr == LUT_RAM_ADDR      )}})  |

                                (LUT_RAM_DATA_D      &  {DEC_SZ{(reg_addr == LUT_RAM_DATA      )}})  |

                                (FRAME_SELECT_D      &  {DEC_SZ{(reg_addr == FRAME_SELECT      )}})  |

                                (FRAME0_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME0_PTR_LO     )}})  |

                                (FRAME0_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME0_PTR_HI     )}})  |

                                (FRAME1_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME1_PTR_LO     )}})  |

                                (FRAME1_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME1_PTR_HI     )}})  |

                                (FRAME2_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME2_PTR_LO     )}})  |

                                (FRAME2_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME2_PTR_HI     )}})  |

                                (FRAME3_PTR_LO_D     &  {DEC_SZ{(reg_addr == FRAME3_PTR_LO     )}})  |

                                (FRAME3_PTR_HI_D     &  {DEC_SZ{(reg_addr == FRAME3_PTR_HI     )}})  |

                                (VID_RAM0_CFG_D      &  {DEC_SZ{(reg_addr == VID_RAM0_CFG      )}})  |

                                (VID_RAM0_WIDTH_D    &  {DEC_SZ{(reg_addr == VID_RAM0_WIDTH    )}})  |

                                (VID_RAM0_ADDR_LO_D  &  {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO  )}})  |

                                (VID_RAM0_ADDR_HI_D  &  {DEC_SZ{(reg_addr == VID_RAM0_ADDR_HI  )}})  |

                                (VID_RAM0_DATA_D     &  {DEC_SZ{(reg_addr == VID_RAM0_DATA     )}})  |

                                (VID_RAM1_CFG_D      &  {DEC_SZ{(reg_addr == VID_RAM1_CFG      )}})  |

                                (VID_RAM1_WIDTH_D    &  {DEC_SZ{(reg_addr == VID_RAM1_WIDTH    )}})  |

                                (VID_RAM1_ADDR_LO_D  &  {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO  )}})  |

                                (VID_RAM1_ADDR_HI_D  &  {DEC_SZ{(reg_addr == VID_RAM1_ADDR_HI  )}})  |

                                (VID_RAM1_DATA_D     &  {DEC_SZ{(reg_addr == VID_RAM1_DATA     )}})  |

                                (GPU_CMD_LO_D        &  {DEC_SZ{(reg_addr == GPU_CMD_LO        )}})  |

                                (GPU_CMD_HI_D        &  {DEC_SZ{(reg_addr == GPU_CMD_HI        )}})  |

                                (GPU_STAT_D          &  {DEC_SZ{(reg_addr == GPU_STAT          )}});

// Read/Write probes

wire               reg_write =  |per_we_i & reg_sel;

wire               reg_read  = ~|per_we_i & reg_sel;

// Read/Write vectors

wire  [DEC_SZ-1:0] reg_wr    = reg_dec & {DEC_SZ{reg_write}};

wire  [DEC_SZ-1:0] reg_rd    = reg_dec & {DEC_SZ{reg_read}};

// Other wire declarations

wire [`APIX_MSB:0] frame0_ptr;

`ifdef WITH_FRAME1_POINTER

wire [`APIX_MSB:0] frame1_ptr;

`endif

`ifdef WITH_FRAME2_POINTER

wire [`APIX_MSB:0] frame2_ptr;

`endif

`ifdef WITH_FRAME3_POINTER

wire [`APIX_MSB:0] frame3_ptr;

`endif

wire [`APIX_MSB:0] vid_ram0_base_addr;

wire [`APIX_MSB:0] vid_ram1_base_addr;

wire               refr_cnt_done_evt;

wire               gpu_fifo_done_evt;

wire               gpu_fifo_ovfl_evt;

//============================================================================

// 3) REGISTERS

//============================================================================

//------------------------------------------------

// GFX_CTRL Register

//------------------------------------------------

reg  [15:0] gfx_ctrl;

wire        gfx_ctrl_wr = reg_wr[GFX_CTRL];

always @ (posedge mclk or posedge puc_rst)

  if (puc_rst)          gfx_ctrl <=  16'h0000;

  else if (gfx_ctrl_wr) gfx_ctrl <=  per_din_i;

// Bitfield assignments

wire        gfx_irq_refr_done_en     =  gfx_ctrl[0];

wire        gfx_irq_refr_start_en    =  gfx_ctrl[1];

wire        gfx_irq_refr_cnt_done_en =  gfx_ctrl[2];

wire        gfx_irq_gpu_fifo_done_en =  gfx_ctrl[4];

wire        gfx_irq_gpu_fifo_ovfl_en =  gfx_ctrl[5];

wire        gfx_irq_gpu_cmd_done_en  =  gfx_ctrl[6];

wire        gfx_irq_gpu_cmd_error_en =  gfx_ctrl[7];

assign      gfx_mode_o               =  gfx_ctrl[10:8]; // 1xx: 16 bits-per-pixel

                                                        // 011:  8 bits-per-pixel

                                                        // 010:  4 bits-per-pixel

                                                        // 001:  2 bits-per-pixel

                                                        // 000:  1 bits-per-pixel

wire        gpu_enable_o             =  gfx_ctrl[12];

// Video modes decoding

wire        gfx_mode_1_bpp           =  (gfx_mode_o == 3'b000);

wire        gfx_mode_2_bpp           =  (gfx_mode_o == 3'b001);

wire        gfx_mode_4_bpp           =  (gfx_mode_o == 3'b010);

wire        gfx_mode_8_bpp           =  (gfx_mode_o == 3'b011);

wire        gfx_mode_16_bpp          = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);

//------------------------------------------------

// GFX_STATUS Register

//------------------------------------------------

wire  [15:0] gfx_status;

wire         gpu_busy;

assign       gfx_status[0]    = lt24_status_i[2]; // Screen Refresh is busy

assign       gfx_status[3:1]  = 3'b000;

assign       gfx_status[4]    = gpu_data_avail_o;

assign       gfx_status[5]    = 1'b0;

assign       gfx_status[6]    = gpu_busy;

assign       gfx_status[7]    = 1'b0;

assign       gfx_status[15:8] = 15'h0000;

//------------------------------------------------

// GFX_IRQ Register

//------------------------------------------------

wire [15:0] gfx_irq;

// Clear IRQ when 1 is written. Set IRQ when FSM is done

wire        gfx_irq_refr_done_clr     = per_din_i[0] & reg_wr[GFX_IRQ];

wire        gfx_irq_refr_done_set     = lt24_done_evt_i;

wire        gfx_irq_refr_start_clr    = per_din_i[1] & reg_wr[GFX_IRQ];

wire        gfx_irq_refr_start_set    = lt24_start_evt_i;

wire        gfx_irq_refr_cnt_done_clr = per_din_i[2] & reg_wr[GFX_IRQ];

wire        gfx_irq_refr_cnt_done_set = refr_cnt_done_evt;

wire        gfx_irq_gpu_fifo_done_clr = per_din_i[4] & reg_wr[GFX_IRQ];

wire        gfx_irq_gpu_fifo_done_set = gpu_fifo_done_evt;

wire        gfx_irq_gpu_fifo_ovfl_clr = per_din_i[5] & reg_wr[GFX_IRQ];

wire        gfx_irq_gpu_fifo_ovfl_set = gpu_fifo_ovfl_evt;

wire        gfx_irq_gpu_cmd_done_clr  = per_din_i[6] & reg_wr[GFX_IRQ];

wire        gfx_irq_gpu_cmd_done_set  = gpu_cmd_done_evt_i;

wire        gfx_irq_gpu_cmd_error_clr = per_din_i[7] & reg_wr[GFX_IRQ];

wire        gfx_irq_gpu_cmd_error_set = gpu_cmd_error_evt_i;

reg         gfx_irq_refr_done;

reg         gfx_irq_refr_start;

reg         gfx_irq_refr_cnt_done;

reg         gfx_irq_gpu_fifo_done;

reg         gfx_irq_gpu_fifo_ovfl;

reg         gfx_irq_gpu_cmd_done;

reg         gfx_irq_gpu_cmd_error;

always @ (posedge mclk or posedge puc_rst)

  if (puc_rst)

    begin

       gfx_irq_refr_done     <=  1'b0;

       gfx_irq_refr_start    <=  1'b0;

       gfx_irq_refr_cnt_done <=  1'b0;

       gfx_irq_gpu_fifo_done <=  1'b0;

       gfx_irq_gpu_fifo_ovfl <=  1'b0;

       gfx_irq_gpu_cmd_done  <=  1'b0;

       gfx_irq_gpu_cmd_error <=  1'b0;

    end

  else

    begin

       gfx_irq_refr_done     <=  (gfx_irq_refr_done_set     | (~gfx_irq_refr_done_clr     & gfx_irq_refr_done    )); // IRQ set has priority over clear

       gfx_irq_refr_start    <=  (gfx_irq_refr_start_set    | (~gfx_irq_refr_start_clr    & gfx_irq_refr_start   )); // IRQ set has priority over clear

       gfx_irq_refr_cnt_done <=  (gfx_irq_refr_cnt_done_set | (~gfx_irq_refr_cnt_done_clr & gfx_irq_refr_cnt_done)); // IRQ set has priority over clear

       gfx_irq_gpu_fifo_done <=  (gfx_irq_gpu_fifo_done_set | (~gfx_irq_gpu_fifo_done_clr & gfx_irq_gpu_fifo_done)); // IRQ set has priority over clear

       gfx_irq_gpu_fifo_ovfl <=  (gfx_irq_gpu_fifo_ovfl_set | (~gfx_irq_gpu_fifo_ovfl_clr & gfx_irq_gpu_fifo_ovfl)); // IRQ set has priority over clear

       gfx_irq_gpu_cmd_done  <=  (gfx_irq_gpu_cmd_done_set  | (~gfx_irq_gpu_cmd_done_clr  & gfx_irq_gpu_cmd_done )); // IRQ set has priority over clear

       gfx_irq_gpu_cmd_error <=  (gfx_irq_gpu_cmd_error_set | (~gfx_irq_gpu_cmd_error_clr & gfx_irq_gpu_cmd_error)); // IRQ set has priority over clear

    end

assign  gfx_irq   = {8'h00,

                     gfx_irq_gpu_cmd_error, gfx_irq_gpu_cmd_done, gfx_irq_gpu_fifo_ovfl, gfx_irq_gpu_fifo_done,

                     2'h0, gfx_irq_refr_start, gfx_irq_refr_done};

assign  irq_gfx_o = (gfx_irq_refr_done     & gfx_irq_refr_done_en)     |

                    (gfx_irq_refr_start    & gfx_irq_refr_start_en)    |

                    (gfx_irq_refr_cnt_done & gfx_irq_refr_cnt_done_en) |

                    (gfx_irq_gpu_cmd_error & gfx_irq_gpu_cmd_error_en) |

                    (gfx_irq_gpu_cmd_done  & gfx_irq_gpu_cmd_done_en)  |

                    (gfx_irq_gpu_fifo_ovfl & gfx_irq_gpu_fifo_ovfl_en) |

                    (gfx_irq_gpu_fifo_done & gfx_irq_gpu_fifo_done_en);  // Graphic Controller interrupt

//------------------------------------------------

// DISPLAY_WIDTH Register

//------------------------------------------------

reg  [`LPIX_MSB:0] display_width_o;

wire               display_width_wr = reg_wr[DISPLAY_WIDTH];

wire [`LPIX_MSB:0] display_w_h_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] :

                                                                  {{`LPIX_MSB{1'b0}}, 1'b1};

always @ (posedge mclk or posedge puc_rst)

  if (puc_rst)               display_width_o <=  {{`LPIX_MSB{1'b0}}, 1'b1};

  else if (display_width_wr) display_width_o <=  display_w_h_nxt;

wire [16:0] display_width_tmp = {{16-`LPIX_MSB{1'b0}}, display_width_o};

wire [15:0] display_width_rd  = display_width_tmp[15:0];

//------------------------------------------------

// DISPLAY_HEIGHT Register

//------------------------------------------------

reg  [`LPIX_MSB:0] display_height_o;

wire               display_height_wr = reg_wr[DISPLAY_HEIGHT];

always @ (posedge mclk or posedge puc_rst)

  if (puc_rst)                display_height_o <=  {{`LPIX_MSB{1'b0}}, 1'b1};

  else if (display_height_wr) display_height_o <=  display_w_h_nxt;

wire [16:0] display_height_tmp = {{16-`LPIX_MSB{1'b0}}, display_height_o};

wire [15:0] display_height_rd  = display_height_tmp[15:0];

//------------------------------------------------

// DISPLAY_SIZE_HI Register

//------------------------------------------------

`ifdef WITH_DISPLAY_SIZE_HI

reg  [`SPIX_HI_MSB:0] display_size_hi;

wire                  display_size_hi_wr = reg_wr[DISPLAY_SIZE_HI];

always @ (posedge mclk or posedge puc_rst)

  if (puc_rst)                 display_size_hi <=  {`SPIX_HI_MSB+1{1'h0}};

  else if (display_size_hi_wr) display_size_hi <=  per_din_i[`SPIX_HI_MSB:0];

wire  [16:0] display_size_hi_tmp = {{16-`SPIX_HI_MSB{1'h0}}, display_size_hi};

wire  [15:0] display_size_hi_rd  = display_size_hi_tmp[15:0];

`endif

//------------------------------------------------

// DISPLAY_SIZE_LO Register

//------------------------------------------------

reg  [`SPIX_LO_MSB:0] display_size_lo;

wire                  display_size_lo_wr = reg_wr[DISPLAY_SIZE_LO];

always @ (posedge mclk or posedge puc_rst)

  if (puc_rst)                 display_size_lo <=  {{`SPIX_LO_MSB{1'h0}}, 1'b1};

  else if (display_size_lo_wr) display_size_lo <=  per_din_i[`SPIX_LO_MSB:0];

wire  [16:0] display_size_lo_tmp = {{16-`SPIX_LO_MSB{1'h0}}, display_size_lo};

wire  [15:0] display_size_lo_rd  = display_size_lo_tmp[15:0];

`ifdef WITH_DISPLAY_SIZE_HI

assign display_size_o = {display_size_hi, display_size_lo};

`else

assign display_size_o =  display_size_lo;

`endif

//------------------------------------------------

// DISPLAY_CFG Register

//------------------------------------------------

reg   display_x_swap_o;

reg   display_y_swap_o;

reg   display_cl_swap_o;

wire  display_cfg_wr = reg_wr[DISPLAY_CFG];

always @ (posedge mclk or posedge puc_rst)

  if (puc_rst)

    begin

       display_cl_swap_o <=  1'b0;

       display_y_swap_o  <=  1'b0;

       display_x_swap_o  <=  1'b0;

    end

  else if (display_cfg_wr)

    begin

       display_cl_swap_o <=  per_din_i[0];