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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ogfx_reg.v
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//
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// *Module Description:
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// Registers for oMSP programming.
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module ogfx_reg (
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// OUTPUTs
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irq_gfx_o, // Graphic Controller interrupt
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gpu_data_o, // GPU data
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gpu_data_avail_o, // GPU data available
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gpu_enable_o, // GPU enable
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lt24_reset_n_o, // LT24 Reset (Active Low)
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lt24_on_o, // LT24 on/off
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lt24_cfg_clk_o, // LT24 Interface clock configuration
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lt24_cfg_refr_o, // LT24 Interface refresh configuration
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lt24_cfg_refr_sync_en_o, // LT24 Interface refresh sync enable configuration
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lt24_cfg_refr_sync_val_o, // LT24 Interface refresh sync value configuration
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lt24_cmd_refr_o, // LT24 Interface refresh command
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lt24_cmd_val_o, // LT24 Generic command value
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lt24_cmd_has_param_o, // LT24 Generic command has parameters
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lt24_cmd_param_o, // LT24 Generic command parameter value
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lt24_cmd_param_rdy_o, // LT24 Generic command trigger
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lt24_cmd_dfill_o, // LT24 Data fill value
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lt24_cmd_dfill_wr_o, // LT24 Data fill trigger
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display_width_o, // Display width
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display_height_o, // Display height
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display_size_o, // Display size (number of pixels)
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display_y_swap_o, // Display configuration: swap Y axis (horizontal symmetry)
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display_x_swap_o, // Display configuration: swap X axis (vertical symmetry)
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display_cl_swap_o, // Display configuration: swap column/lines
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gfx_mode_o, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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per_dout_o, // Peripheral data output
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refresh_frame_addr_o, // Refresh frame base address
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refresh_lut_select_o, // Refresh LUT bank selection
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_addr_o, // LUT-RAM address
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lut_ram_din_o, // LUT-RAM data
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lut_ram_wen_o, // LUT-RAM write strobe (active low)
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lut_ram_cen_o, // LUT-RAM chip enable (active low)
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`endif
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vid_ram_addr_o, // Video-RAM address
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vid_ram_din_o, // Video-RAM data
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vid_ram_wen_o, // Video-RAM write strobe (active low)
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vid_ram_cen_o, // Video-RAM chip enable (active low)
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// INPUTs
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dbg_freeze_i, // Freeze address auto-incr on read
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gpu_cmd_done_evt_i, // GPU command done event
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gpu_cmd_error_evt_i, // GPU command error event
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gpu_dma_busy_i, // GPU DMA execution on going
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gpu_get_data_i, // GPU get next data
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lt24_status_i, // LT24 FSM Status
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lt24_start_evt_i, // LT24 FSM is starting
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lt24_done_evt_i, // LT24 FSM is done
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mclk, // Main system clock
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per_addr_i, // Peripheral address
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per_din_i, // Peripheral data input
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per_en_i, // Peripheral enable (high active)
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per_we_i, // Peripheral write enable (high active)
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puc_rst, // Main system reset
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_dout_i, // LUT-RAM data input
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`endif
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vid_ram_dout_i // Video-RAM data input
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);
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// OUTPUTs
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//=========
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output irq_gfx_o; // Graphic Controller interrupt
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output [15:0] gpu_data_o; // GPU data
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output gpu_data_avail_o; // GPU data available
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output gpu_enable_o; // GPU enable
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output lt24_reset_n_o; // LT24 Reset (Active Low)
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output lt24_on_o; // LT24 on/off
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output [2:0] lt24_cfg_clk_o; // LT24 Interface clock configuration
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output [11:0] lt24_cfg_refr_o; // LT24 Interface refresh configuration
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output lt24_cfg_refr_sync_en_o; // LT24 Interface refresh sync configuration
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output [9:0] lt24_cfg_refr_sync_val_o; // LT24 Interface refresh sync value configuration
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output lt24_cmd_refr_o; // LT24 Interface refresh command
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output [7:0] lt24_cmd_val_o; // LT24 Generic command value
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output lt24_cmd_has_param_o; // LT24 Generic command has parameters
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output [15:0] lt24_cmd_param_o; // LT24 Generic command parameter value
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output lt24_cmd_param_rdy_o; // LT24 Generic command trigger
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output [15:0] lt24_cmd_dfill_o; // LT24 Data fill value
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output lt24_cmd_dfill_wr_o; // LT24 Data fill trigger
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output [`LPIX_MSB:0] display_width_o; // Display width
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output [`LPIX_MSB:0] display_height_o; // Display height
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output [`SPIX_MSB:0] display_size_o; // Display size (number of pixels)
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output display_y_swap_o; // Display configuration: swap Y axis (horizontal symmetry)
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output display_x_swap_o; // Display configuration: swap X axis (vertical symmetry)
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output display_cl_swap_o; // Display configuration: swap column/lines
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output [2:0] gfx_mode_o; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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output [15:0] per_dout_o; // Peripheral data output
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output [`APIX_MSB:0] refresh_frame_addr_o; // Refresh frame base address
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output [1:0] refresh_lut_select_o; // Refresh LUT bank selection
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`ifdef WITH_PROGRAMMABLE_LUT
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output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
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output [15:0] lut_ram_din_o; // LUT-RAM data
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output lut_ram_wen_o; // LUT-RAM write strobe (active low)
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output lut_ram_cen_o; // LUT-RAM chip enable (active low)
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`endif
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output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
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output [15:0] vid_ram_din_o; // Video-RAM data
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output vid_ram_wen_o; // Video-RAM write strobe (active low)
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output vid_ram_cen_o; // Video-RAM chip enable (active low)
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// INPUTs
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//=========
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input dbg_freeze_i; // Freeze address auto-incr on read
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input gpu_cmd_done_evt_i; // GPU command done event
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input gpu_cmd_error_evt_i; // GPU command error event
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input gpu_dma_busy_i; // GPU DMA execution on going
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input gpu_get_data_i; // GPU get next data
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input [4:0] lt24_status_i; // LT24 FSM Status
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input lt24_start_evt_i; // LT24 FSM is starting
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input lt24_done_evt_i; // LT24 FSM is done
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input mclk; // Main system clock
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input [13:0] per_addr_i; // Peripheral address
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input [15:0] per_din_i; // Peripheral data input
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input per_en_i; // Peripheral enable (high active)
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input [1:0] per_we_i; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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`ifdef WITH_PROGRAMMABLE_LUT
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input [15:0] lut_ram_dout_i; // LUT-RAM data input
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`endif
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input [15:0] vid_ram_dout_i; // Video-RAM data input
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//=============================================================================
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// 1) PARAMETER DECLARATION
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//=============================================================================
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// Register base address (must be aligned to decoder bit width)
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parameter [14:0] BASE_ADDR = 15'h0200;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 7;
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// Register addresses offset
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parameter [DEC_WD-1:0] GFX_CTRL = 'h00, // General control/status/irq
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GFX_STATUS = 'h08,
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GFX_IRQ = 'h0A,
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DISPLAY_WIDTH = 'h10, // Display configuration
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DISPLAY_HEIGHT = 'h12,
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DISPLAY_SIZE_LO = 'h14,
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DISPLAY_SIZE_HI = 'h16,
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DISPLAY_CFG = 'h18,
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DISPLAY_REFR_CNT = 'h1A,
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LT24_CFG = 'h20, // LT24 configuration and Generic command sending
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LT24_REFRESH = 'h22,
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LT24_REFRESH_SYNC = 'h24,
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LT24_CMD = 'h26,
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LT24_CMD_PARAM = 'h28,
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LT24_CMD_DFILL = 'h2A,
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LT24_STATUS = 'h2C,
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LUT_RAM_ADDR = 'h30, // LUT Memory Access Gate
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LUT_RAM_DATA = 'h32,
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FRAME_SELECT = 'h3E, // Frame pointers and selection
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FRAME0_PTR_LO = 'h40,
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FRAME0_PTR_HI = 'h42,
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FRAME1_PTR_LO = 'h44,
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FRAME1_PTR_HI = 'h46,
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FRAME2_PTR_LO = 'h48,
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FRAME2_PTR_HI = 'h4A,
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FRAME3_PTR_LO = 'h4C,
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FRAME3_PTR_HI = 'h4E,
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VID_RAM0_CFG = 'h50, // First Video Memory Access Gate
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VID_RAM0_WIDTH = 'h52,
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VID_RAM0_ADDR_LO = 'h54,
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VID_RAM0_ADDR_HI = 'h56,
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VID_RAM0_DATA = 'h58,
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VID_RAM1_CFG = 'h60, // Second Video Memory Access Gate
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VID_RAM1_WIDTH = 'h62,
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VID_RAM1_ADDR_LO = 'h64,
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VID_RAM1_ADDR_HI = 'h66,
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VID_RAM1_DATA = 'h68,
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GPU_CMD_LO = 'h70, // Graphic Processing Unit
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GPU_CMD_HI = 'h72,
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GPU_STAT = 'h74;
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// Register one-hot decoder utilities
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parameter DEC_SZ = (1 << DEC_WD);
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] GFX_CTRL_D = (BASE_REG << GFX_CTRL ),
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GFX_STATUS_D = (BASE_REG << GFX_STATUS ),
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GFX_IRQ_D = (BASE_REG << GFX_IRQ ),
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DISPLAY_WIDTH_D = (BASE_REG << DISPLAY_WIDTH ),
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DISPLAY_HEIGHT_D = (BASE_REG << DISPLAY_HEIGHT ),
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DISPLAY_SIZE_LO_D = (BASE_REG << DISPLAY_SIZE_LO ),
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DISPLAY_SIZE_HI_D = (BASE_REG << DISPLAY_SIZE_HI ),
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DISPLAY_CFG_D = (BASE_REG << DISPLAY_CFG ),
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DISPLAY_REFR_CNT_D = (BASE_REG << DISPLAY_REFR_CNT ),
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LT24_CFG_D = (BASE_REG << LT24_CFG ),
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LT24_REFRESH_D = (BASE_REG << LT24_REFRESH ),
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LT24_REFRESH_SYNC_D = (BASE_REG << LT24_REFRESH_SYNC ),
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LT24_CMD_D = (BASE_REG << LT24_CMD ),
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LT24_CMD_PARAM_D = (BASE_REG << LT24_CMD_PARAM ),
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LT24_CMD_DFILL_D = (BASE_REG << LT24_CMD_DFILL ),
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LT24_STATUS_D = (BASE_REG << LT24_STATUS ),
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LUT_RAM_ADDR_D = (BASE_REG << LUT_RAM_ADDR ),
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LUT_RAM_DATA_D = (BASE_REG << LUT_RAM_DATA ),
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FRAME_SELECT_D = (BASE_REG << FRAME_SELECT ),
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FRAME0_PTR_LO_D = (BASE_REG << FRAME0_PTR_LO ),
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FRAME0_PTR_HI_D = (BASE_REG << FRAME0_PTR_HI ),
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FRAME1_PTR_LO_D = (BASE_REG << FRAME1_PTR_LO ),
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FRAME1_PTR_HI_D = (BASE_REG << FRAME1_PTR_HI ),
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FRAME2_PTR_LO_D = (BASE_REG << FRAME2_PTR_LO ),
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FRAME2_PTR_HI_D = (BASE_REG << FRAME2_PTR_HI ),
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FRAME3_PTR_LO_D = (BASE_REG << FRAME3_PTR_LO ),
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FRAME3_PTR_HI_D = (BASE_REG << FRAME3_PTR_HI ),
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VID_RAM0_CFG_D = (BASE_REG << VID_RAM0_CFG ),
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VID_RAM0_WIDTH_D = (BASE_REG << VID_RAM0_WIDTH ),
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VID_RAM0_ADDR_LO_D = (BASE_REG << VID_RAM0_ADDR_LO ),
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VID_RAM0_ADDR_HI_D = (BASE_REG << VID_RAM0_ADDR_HI ),
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VID_RAM0_DATA_D = (BASE_REG << VID_RAM0_DATA ),
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VID_RAM1_CFG_D = (BASE_REG << VID_RAM1_CFG ),
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VID_RAM1_WIDTH_D = (BASE_REG << VID_RAM1_WIDTH ),
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VID_RAM1_ADDR_LO_D = (BASE_REG << VID_RAM1_ADDR_LO ),
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VID_RAM1_ADDR_HI_D = (BASE_REG << VID_RAM1_ADDR_HI ),
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VID_RAM1_DATA_D = (BASE_REG << VID_RAM1_DATA ),
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GPU_CMD_LO_D = (BASE_REG << GPU_CMD_LO ),
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GPU_CMD_HI_D = (BASE_REG << GPU_CMD_HI ),
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GPU_STAT_D = (BASE_REG << GPU_STAT );
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|
295 |
|
|
//============================================================================
|
296 |
|
|
// 2) REGISTER DECODER
|
297 |
|
|
//============================================================================
|
298 |
|
|
|
299 |
|
|
// Local register selection
|
300 |
|
|
wire reg_sel = per_en_i & (per_addr_i[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
|
301 |
|
|
|
302 |
|
|
// Register local address
|
303 |
|
|
wire [DEC_WD-1:0] reg_addr = {per_addr_i[DEC_WD-2:0], 1'b0};
|
304 |
|
|
|
305 |
|
|
// Register address decode
|
306 |
|
|
wire [DEC_SZ-1:0] reg_dec = (GFX_CTRL_D & {DEC_SZ{(reg_addr == GFX_CTRL )}}) |
|
307 |
|
|
(GFX_STATUS_D & {DEC_SZ{(reg_addr == GFX_STATUS )}}) |
|
308 |
|
|
(GFX_IRQ_D & {DEC_SZ{(reg_addr == GFX_IRQ )}}) |
|
309 |
|
|
|
310 |
|
|
(DISPLAY_WIDTH_D & {DEC_SZ{(reg_addr == DISPLAY_WIDTH )}}) |
|
311 |
|
|
(DISPLAY_HEIGHT_D & {DEC_SZ{(reg_addr == DISPLAY_HEIGHT )}}) |
|
312 |
6 |
olivier.gi |
(DISPLAY_SIZE_LO_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO )}}) |
|
313 |
3 |
olivier.gi |
(DISPLAY_SIZE_HI_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_HI )}}) |
|
314 |
|
|
(DISPLAY_CFG_D & {DEC_SZ{(reg_addr == DISPLAY_CFG )}}) |
|
315 |
8 |
olivier.gi |
(DISPLAY_REFR_CNT_D & {DEC_SZ{(reg_addr == DISPLAY_REFR_CNT )}}) |
|
316 |
3 |
olivier.gi |
|
317 |
|
|
(LT24_CFG_D & {DEC_SZ{(reg_addr == LT24_CFG )}}) |
|
318 |
|
|
(LT24_REFRESH_D & {DEC_SZ{(reg_addr == LT24_REFRESH )}}) |
|
319 |
|
|
(LT24_REFRESH_SYNC_D & {DEC_SZ{(reg_addr == LT24_REFRESH_SYNC )}}) |
|
320 |
|
|
(LT24_CMD_D & {DEC_SZ{(reg_addr == LT24_CMD )}}) |
|
321 |
|
|
(LT24_CMD_PARAM_D & {DEC_SZ{(reg_addr == LT24_CMD_PARAM )}}) |
|
322 |
|
|
(LT24_CMD_DFILL_D & {DEC_SZ{(reg_addr == LT24_CMD_DFILL )}}) |
|
323 |
|
|
(LT24_STATUS_D & {DEC_SZ{(reg_addr == LT24_STATUS )}}) |
|
324 |
|
|
|
325 |
|
|
(LUT_RAM_ADDR_D & {DEC_SZ{(reg_addr == LUT_RAM_ADDR )}}) |
|
326 |
|
|
(LUT_RAM_DATA_D & {DEC_SZ{(reg_addr == LUT_RAM_DATA )}}) |
|
327 |
|
|
|
328 |
|
|
(FRAME_SELECT_D & {DEC_SZ{(reg_addr == FRAME_SELECT )}}) |
|
329 |
6 |
olivier.gi |
(FRAME0_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME0_PTR_LO )}}) |
|
330 |
3 |
olivier.gi |
(FRAME0_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME0_PTR_HI )}}) |
|
331 |
6 |
olivier.gi |
(FRAME1_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME1_PTR_LO )}}) |
|
332 |
3 |
olivier.gi |
(FRAME1_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME1_PTR_HI )}}) |
|
333 |
6 |
olivier.gi |
(FRAME2_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME2_PTR_LO )}}) |
|
334 |
3 |
olivier.gi |
(FRAME2_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME2_PTR_HI )}}) |
|
335 |
6 |
olivier.gi |
(FRAME3_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME3_PTR_LO )}}) |
|
336 |
3 |
olivier.gi |
(FRAME3_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME3_PTR_HI )}}) |
|
337 |
|
|
|
338 |
|
|
(VID_RAM0_CFG_D & {DEC_SZ{(reg_addr == VID_RAM0_CFG )}}) |
|
339 |
|
|
(VID_RAM0_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM0_WIDTH )}}) |
|
340 |
6 |
olivier.gi |
(VID_RAM0_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO )}}) |
|
341 |
3 |
olivier.gi |
(VID_RAM0_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_HI )}}) |
|
342 |
|
|
(VID_RAM0_DATA_D & {DEC_SZ{(reg_addr == VID_RAM0_DATA )}}) |
|
343 |
|
|
|
344 |
|
|
(VID_RAM1_CFG_D & {DEC_SZ{(reg_addr == VID_RAM1_CFG )}}) |
|
345 |
|
|
(VID_RAM1_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM1_WIDTH )}}) |
|
346 |
6 |
olivier.gi |
(VID_RAM1_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO )}}) |
|
347 |
3 |
olivier.gi |
(VID_RAM1_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_HI )}}) |
|
348 |
|
|
(VID_RAM1_DATA_D & {DEC_SZ{(reg_addr == VID_RAM1_DATA )}}) |
|
349 |
|
|
|
350 |
6 |
olivier.gi |
(GPU_CMD_LO_D & {DEC_SZ{(reg_addr == GPU_CMD_LO )}}) |
|
351 |
|
|
(GPU_CMD_HI_D & {DEC_SZ{(reg_addr == GPU_CMD_HI )}}) |
|
352 |
3 |
olivier.gi |
(GPU_STAT_D & {DEC_SZ{(reg_addr == GPU_STAT )}});
|
353 |
|
|
|
354 |
|
|
// Read/Write probes
|
355 |
|
|
wire reg_write = |per_we_i & reg_sel;
|
356 |
|
|
wire reg_read = ~|per_we_i & reg_sel;
|
357 |
|
|
|
358 |
|
|
// Read/Write vectors
|
359 |
|
|
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
|
360 |
|
|
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
|
361 |
|
|
|
362 |
|
|
// Other wire declarations
|
363 |
|
|
wire [`APIX_MSB:0] frame0_ptr;
|
364 |
|
|
`ifdef WITH_FRAME1_POINTER
|
365 |
|
|
wire [`APIX_MSB:0] frame1_ptr;
|
366 |
|
|
`endif
|
367 |
|
|
`ifdef WITH_FRAME2_POINTER
|
368 |
|
|
wire [`APIX_MSB:0] frame2_ptr;
|
369 |
|
|
`endif
|
370 |
|
|
`ifdef WITH_FRAME3_POINTER
|
371 |
|
|
wire [`APIX_MSB:0] frame3_ptr;
|
372 |
|
|
`endif
|
373 |
|
|
wire [`APIX_MSB:0] vid_ram0_base_addr;
|
374 |
|
|
wire [`APIX_MSB:0] vid_ram1_base_addr;
|
375 |
|
|
`ifdef WITH_EXTRA_LUT_BANK
|
376 |
|
|
reg lut_bank_select;
|
377 |
|
|
`endif
|
378 |
|
|
wire gpu_fifo_done_evt;
|
379 |
|
|
wire gpu_fifo_ovfl_evt;
|
380 |
|
|
|
381 |
|
|
|
382 |
|
|
//============================================================================
|
383 |
|
|
// 3) REGISTERS
|
384 |
|
|
//============================================================================
|
385 |
|
|
|
386 |
|
|
//------------------------------------------------
|
387 |
|
|
// GFX_CTRL Register
|
388 |
|
|
//------------------------------------------------
|
389 |
|
|
reg [15:0] gfx_ctrl;
|
390 |
|
|
|
391 |
|
|
wire gfx_ctrl_wr = reg_wr[GFX_CTRL];
|
392 |
|
|
|
393 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
394 |
|
|
if (puc_rst) gfx_ctrl <= 16'h0000;
|
395 |
|
|
else if (gfx_ctrl_wr) gfx_ctrl <= per_din_i;
|
396 |
|
|
|
397 |
|
|
// Bitfield assignments
|
398 |
|
|
wire gfx_irq_refr_done_en = gfx_ctrl[0];
|
399 |
|
|
wire gfx_irq_refr_start_en = gfx_ctrl[1];
|
400 |
|
|
wire gfx_irq_gpu_fifo_done_en = gfx_ctrl[4];
|
401 |
|
|
wire gfx_irq_gpu_fifo_ovfl_en = gfx_ctrl[5];
|
402 |
|
|
wire gfx_irq_gpu_cmd_done_en = gfx_ctrl[6];
|
403 |
|
|
wire gfx_irq_gpu_cmd_error_en = gfx_ctrl[7];
|
404 |
|
|
assign gfx_mode_o = gfx_ctrl[10:8]; // 1xx: 16 bits-per-pixel
|
405 |
|
|
// 011: 8 bits-per-pixel
|
406 |
|
|
// 010: 4 bits-per-pixel
|
407 |
|
|
// 001: 2 bits-per-pixel
|
408 |
|
|
// 000: 1 bits-per-pixel
|
409 |
|
|
wire gpu_enable_o = gfx_ctrl[12];
|
410 |
|
|
|
411 |
|
|
// Video modes decoding
|
412 |
|
|
wire gfx_mode_1_bpp = (gfx_mode_o == 3'b000);
|
413 |
|
|
wire gfx_mode_2_bpp = (gfx_mode_o == 3'b001);
|
414 |
|
|
wire gfx_mode_4_bpp = (gfx_mode_o == 3'b010);
|
415 |
|
|
wire gfx_mode_8_bpp = (gfx_mode_o == 3'b011);
|
416 |
|
|
wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);
|
417 |
|
|
|
418 |
|
|
//------------------------------------------------
|
419 |
|
|
// GFX_STATUS Register
|
420 |
|
|
//------------------------------------------------
|
421 |
|
|
wire [15:0] gfx_status;
|
422 |
|
|
|
423 |
|
|
assign gfx_status[0] = lt24_status_i[2]; // Screen Refresh is busy
|
424 |
|
|
assign gfx_status[15:1] = 15'h0000;
|
425 |
|
|
|
426 |
|
|
//------------------------------------------------
|
427 |
|
|
// GFX_IRQ Register
|
428 |
|
|
//------------------------------------------------
|
429 |
|
|
wire [15:0] gfx_irq;
|
430 |
|
|
|
431 |
|
|
// Clear IRQ when 1 is written. Set IRQ when FSM is done
|
432 |
|
|
wire gfx_irq_refr_done_clr = per_din_i[0] & reg_wr[GFX_IRQ];
|
433 |
|
|
wire gfx_irq_refr_done_set = lt24_done_evt_i;
|
434 |
|
|
|
435 |
|
|
wire gfx_irq_refr_start_clr = per_din_i[1] & reg_wr[GFX_IRQ];
|
436 |
|
|
wire gfx_irq_refr_start_set = lt24_start_evt_i;
|
437 |
|
|
|
438 |
|
|
wire gfx_irq_gpu_fifo_done_clr = per_din_i[4] & reg_wr[GFX_IRQ];
|
439 |
|
|
wire gfx_irq_gpu_fifo_done_set = gpu_fifo_done_evt;
|
440 |
|
|
|
441 |
|
|
wire gfx_irq_gpu_fifo_ovfl_clr = per_din_i[5] & reg_wr[GFX_IRQ];
|
442 |
|
|
wire gfx_irq_gpu_fifo_ovfl_set = gpu_fifo_ovfl_evt;
|
443 |
|
|
|
444 |
|
|
wire gfx_irq_gpu_cmd_done_clr = per_din_i[6] & reg_wr[GFX_IRQ];
|
445 |
|
|
wire gfx_irq_gpu_cmd_done_set = gpu_cmd_done_evt_i;
|
446 |
|
|
|
447 |
|
|
wire gfx_irq_gpu_cmd_error_clr = per_din_i[7] & reg_wr[GFX_IRQ];
|
448 |
|
|
wire gfx_irq_gpu_cmd_error_set = gpu_cmd_error_evt_i;
|
449 |
|
|
|
450 |
|
|
reg gfx_irq_refr_done;
|
451 |
|
|
reg gfx_irq_refr_start;
|
452 |
|
|
reg gfx_irq_gpu_fifo_done;
|
453 |
|
|
reg gfx_irq_gpu_fifo_ovfl;
|
454 |
|
|
reg gfx_irq_gpu_cmd_done;
|
455 |
|
|
reg gfx_irq_gpu_cmd_error;
|
456 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
457 |
|
|
if (puc_rst)
|
458 |
|
|
begin
|
459 |
|
|
gfx_irq_refr_done <= 1'b0;
|
460 |
|
|
gfx_irq_refr_start <= 1'b0;
|
461 |
|
|
gfx_irq_gpu_fifo_done <= 1'b0;
|
462 |
|
|
gfx_irq_gpu_fifo_ovfl <= 1'b0;
|
463 |
|
|
gfx_irq_gpu_cmd_done <= 1'b0;
|
464 |
|
|
gfx_irq_gpu_cmd_error <= 1'b0;
|
465 |
|
|
end
|
466 |
|
|
else
|
467 |
|
|
begin
|
468 |
|
|
gfx_irq_refr_done <= (gfx_irq_refr_done_set | (~gfx_irq_refr_done_clr & gfx_irq_refr_done )); // IRQ set has priority over clear
|
469 |
|
|
gfx_irq_refr_start <= (gfx_irq_refr_start_set | (~gfx_irq_refr_start_clr & gfx_irq_refr_start )); // IRQ set has priority over clear
|
470 |
|
|
gfx_irq_gpu_fifo_done <= (gfx_irq_gpu_fifo_done_set | (~gfx_irq_gpu_fifo_done_clr & gfx_irq_gpu_fifo_done)); // IRQ set has priority over clear
|
471 |
|
|
gfx_irq_gpu_fifo_ovfl <= (gfx_irq_gpu_fifo_ovfl_set | (~gfx_irq_gpu_fifo_ovfl_clr & gfx_irq_gpu_fifo_ovfl)); // IRQ set has priority over clear
|
472 |
|
|
gfx_irq_gpu_cmd_done <= (gfx_irq_gpu_cmd_done_set | (~gfx_irq_gpu_cmd_done_clr & gfx_irq_gpu_cmd_done )); // IRQ set has priority over clear
|
473 |
|
|
gfx_irq_gpu_cmd_error <= (gfx_irq_gpu_cmd_error_set | (~gfx_irq_gpu_cmd_error_clr & gfx_irq_gpu_cmd_error)); // IRQ set has priority over clear
|
474 |
|
|
end
|
475 |
|
|
|
476 |
|
|
assign gfx_irq = {8'h00,
|
477 |
|
|
gfx_irq_gpu_cmd_error, gfx_irq_gpu_cmd_done, gfx_irq_gpu_fifo_ovfl, gfx_irq_gpu_fifo_done,
|
478 |
|
|
2'h0, gfx_irq_refr_start, gfx_irq_refr_done};
|
479 |
|
|
|
480 |
|
|
assign irq_gfx_o = (gfx_irq_refr_done & gfx_irq_refr_done_en) |
|
481 |
|
|
(gfx_irq_refr_start & gfx_irq_refr_start_en) |
|
482 |
|
|
(gfx_irq_gpu_cmd_error & gfx_irq_gpu_cmd_error_en) |
|
483 |
|
|
(gfx_irq_gpu_cmd_done & gfx_irq_gpu_cmd_done_en) |
|
484 |
|
|
(gfx_irq_gpu_fifo_ovfl & gfx_irq_gpu_fifo_ovfl_en) |
|
485 |
|
|
(gfx_irq_gpu_fifo_done & gfx_irq_gpu_fifo_done_en); // Graphic Controller interrupt
|
486 |
|
|
|
487 |
|
|
//------------------------------------------------
|
488 |
|
|
// DISPLAY_WIDTH Register
|
489 |
|
|
//------------------------------------------------
|
490 |
|
|
reg [`LPIX_MSB:0] display_width_o;
|
491 |
|
|
|
492 |
|
|
wire display_width_wr = reg_wr[DISPLAY_WIDTH];
|
493 |
|
|
wire [`LPIX_MSB:0] display_w_h_nxt = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] :
|
494 |
|
|
{{`LPIX_MSB{1'b0}}, 1'b1};
|
495 |
|
|
|
496 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
497 |
|
|
if (puc_rst) display_width_o <= {{`LPIX_MSB{1'b0}}, 1'b1};
|
498 |
|
|
else if (display_width_wr) display_width_o <= display_w_h_nxt;
|
499 |
|
|
|
500 |
|
|
wire [16:0] display_width_tmp = {{16-`LPIX_MSB{1'b0}}, display_width_o};
|
501 |
|
|
wire [15:0] display_width_rd = display_width_tmp[15:0];
|
502 |
|
|
|
503 |
|
|
//------------------------------------------------
|
504 |
|
|
// DISPLAY_HEIGHT Register
|
505 |
|
|
//------------------------------------------------
|
506 |
|
|
reg [`LPIX_MSB:0] display_height_o;
|
507 |
|
|
|
508 |
|
|
wire display_height_wr = reg_wr[DISPLAY_HEIGHT];
|
509 |
|
|
|
510 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
511 |
|
|
if (puc_rst) display_height_o <= {{`LPIX_MSB{1'b0}}, 1'b1};
|
512 |
|
|
else if (display_height_wr) display_height_o <= display_w_h_nxt;
|
513 |
|
|
|
514 |
|
|
wire [16:0] display_height_tmp = {{16-`LPIX_MSB{1'b0}}, display_height_o};
|
515 |
|
|
wire [15:0] display_height_rd = display_height_tmp[15:0];
|
516 |
|
|
|
517 |
|
|
//------------------------------------------------
|
518 |
|
|
// DISPLAY_SIZE_HI Register
|
519 |
|
|
//------------------------------------------------
|
520 |
|
|
`ifdef WITH_DISPLAY_SIZE_HI
|
521 |
|
|
reg [`SPIX_HI_MSB:0] display_size_hi;
|
522 |
|
|
|
523 |
|
|
wire display_size_hi_wr = reg_wr[DISPLAY_SIZE_HI];
|
524 |
|
|
|
525 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
526 |
|
|
if (puc_rst) display_size_hi <= {`SPIX_HI_MSB+1{1'h0}};
|
527 |
|
|
else if (display_size_hi_wr) display_size_hi <= per_din_i[`SPIX_HI_MSB:0];
|
528 |
|
|
|
529 |
|
|
wire [16:0] display_size_hi_tmp = {{16-`SPIX_HI_MSB{1'h0}}, display_size_hi};
|
530 |
|
|
wire [15:0] display_size_hi_rd = display_size_hi_tmp[15:0];
|
531 |
|
|
`endif
|
532 |
|
|
|
533 |
|
|
//------------------------------------------------
|
534 |
|
|
// DISPLAY_SIZE_LO Register
|
535 |
|
|
//------------------------------------------------
|
536 |
|
|
reg [`SPIX_LO_MSB:0] display_size_lo;
|
537 |
|
|
|
538 |
|
|
wire display_size_lo_wr = reg_wr[DISPLAY_SIZE_LO];
|
539 |
|
|
|
540 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
541 |
|
|
if (puc_rst) display_size_lo <= {{`SPIX_LO_MSB{1'h0}}, 1'b1};
|
542 |
|
|
else if (display_size_lo_wr) display_size_lo <= per_din_i[`SPIX_LO_MSB:0];
|
543 |
|
|
|
544 |
|
|
wire [16:0] display_size_lo_tmp = {{16-`SPIX_LO_MSB{1'h0}}, display_size_lo};
|
545 |
|
|
wire [15:0] display_size_lo_rd = display_size_lo_tmp[15:0];
|
546 |
|
|
|
547 |
|
|
`ifdef WITH_DISPLAY_SIZE_HI
|
548 |
|
|
assign display_size_o = {display_size_hi, display_size_lo};
|
549 |
|
|
`else
|
550 |
|
|
assign display_size_o = display_size_lo;
|
551 |
|
|
`endif
|
552 |
|
|
|
553 |
|
|
//------------------------------------------------
|
554 |
|
|
// DISPLAY_CFG Register
|
555 |
|
|
//------------------------------------------------
|
556 |
|
|
reg display_x_swap_o;
|
557 |
|
|
reg display_y_swap_o;
|
558 |
|
|
reg display_cl_swap_o;
|
559 |
|
|
|
560 |
|
|
wire display_cfg_wr = reg_wr[DISPLAY_CFG];
|
561 |
|
|
|
562 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
563 |
|
|
if (puc_rst)
|
564 |
|
|
begin
|
565 |
|
|
display_cl_swap_o <= 1'b0;
|
566 |
|
|
display_y_swap_o <= 1'b0;
|
567 |
|
|
display_x_swap_o <= 1'b0;
|
568 |
|
|
end
|
569 |
|
|
else if (display_cfg_wr)
|
570 |
|
|
begin
|
571 |
|
|
display_cl_swap_o <= per_din_i[0];
|
572 |
|
|
display_y_swap_o <= per_din_i[1];
|
573 |
|
|
display_x_swap_o <= per_din_i[2];
|
574 |
|
|
end
|
575 |
|
|
|
576 |
|
|
wire [15:0] display_cfg = {13'h0000,
|
577 |
|
|
display_x_swap_o,
|
578 |
|
|
display_y_swap_o,
|
579 |
|
|
display_cl_swap_o};
|
580 |
|
|
|
581 |
|
|
//------------------------------------------------
|
582 |
8 |
olivier.gi |
// DISPLAY_REFR_CNT Register
|
583 |
|
|
//------------------------------------------------
|
584 |
|
|
reg [15:0] display_refr_cnt;
|
585 |
|
|
|
586 |
|
|
wire display_refr_cnt_wr = reg_wr[DISPLAY_REFR_CNT];
|
587 |
|
|
wire display_refr_cnt_dec = gfx_irq_refr_done_set & (display_refr_cnt != 16'h0000);
|
588 |
|
|
|
589 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
590 |
|
|
if (puc_rst) display_refr_cnt <= 16'h0000;
|
591 |
|
|
else if (display_refr_cnt_wr) display_refr_cnt <= per_din_i;
|
592 |
|
|
else if (display_refr_cnt_dec) display_refr_cnt <= display_refr_cnt + 16'hFFFF; // -1
|
593 |
|
|
|
594 |
|
|
//------------------------------------------------
|
595 |
3 |
olivier.gi |
// LT24_CFG Register
|
596 |
|
|
//------------------------------------------------
|
597 |
|
|
reg [15:0] lt24_cfg;
|
598 |
|
|
|
599 |
|
|
wire lt24_cfg_wr = reg_wr[LT24_CFG];
|
600 |
|
|
|
601 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
602 |
|
|
if (puc_rst) lt24_cfg <= 16'h0000;
|
603 |
|
|
else if (lt24_cfg_wr) lt24_cfg <= per_din_i;
|
604 |
|
|
|
605 |
|
|
// Bitfield assignments
|
606 |
|
|
assign lt24_cfg_clk_o = lt24_cfg[6:4];
|
607 |
|
|
assign lt24_reset_n_o = ~lt24_cfg[1];
|
608 |
|
|
assign lt24_on_o = lt24_cfg[0];
|
609 |
|
|
|
610 |
|
|
//------------------------------------------------
|
611 |
|
|
// LT24_REFRESH Register
|
612 |
|
|
//------------------------------------------------
|
613 |
|
|
reg lt24_cmd_refr_o;
|
614 |
|
|
reg [11:0] lt24_cfg_refr_o;
|
615 |
|
|
|
616 |
|
|
wire lt24_refresh_wr = reg_wr[LT24_REFRESH];
|
617 |
|
|
wire lt24_cmd_refr_clr = lt24_done_evt_i & lt24_status_i[2] & (lt24_cfg_refr_o==8'h00); // Auto-clear in manual refresh mode when done
|
618 |
|
|
|
619 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
620 |
|
|
if (puc_rst) lt24_cmd_refr_o <= 1'h0;
|
621 |
|
|
else if (lt24_refresh_wr) lt24_cmd_refr_o <= per_din_i[0];
|
622 |
|
|
else if (lt24_cmd_refr_clr) lt24_cmd_refr_o <= 1'h0;
|
623 |
|
|
|
624 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
625 |
|
|
if (puc_rst) lt24_cfg_refr_o <= 12'h000;
|
626 |
|
|
else if (lt24_refresh_wr) lt24_cfg_refr_o <= per_din_i[15:4];
|
627 |
|
|
|
628 |
|
|
wire [15:0] lt24_refresh = {lt24_cfg_refr_o, 3'h0, lt24_cmd_refr_o};
|
629 |
|
|
|
630 |
|
|
//------------------------------------------------
|
631 |
|
|
// LT24_REFRESH Register
|
632 |
|
|
//------------------------------------------------
|
633 |
|
|
reg lt24_cfg_refr_sync_en_o;
|
634 |
|
|
reg [9:0] lt24_cfg_refr_sync_val_o;
|
635 |
|
|
|
636 |
|
|
wire lt24_refresh_sync_wr = reg_wr[LT24_REFRESH_SYNC];
|
637 |
|
|
|
638 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
639 |
|
|
if (puc_rst) lt24_cfg_refr_sync_en_o <= 1'h0;
|
640 |
|
|
else if (lt24_refresh_sync_wr) lt24_cfg_refr_sync_en_o <= per_din_i[15];
|
641 |
|
|
|
642 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
643 |
|
|
if (puc_rst) lt24_cfg_refr_sync_val_o <= 10'h000;
|
644 |
|
|
else if (lt24_refresh_sync_wr) lt24_cfg_refr_sync_val_o <= per_din_i[9:0];
|
645 |
|
|
|
646 |
|
|
wire [15:0] lt24_refresh_sync = {lt24_cfg_refr_sync_en_o, 5'h00, lt24_cfg_refr_sync_val_o};
|
647 |
|
|
|
648 |
|
|
|
649 |
|
|
//------------------------------------------------
|
650 |
|
|
// LT24_CMD Register
|
651 |
|
|
//------------------------------------------------
|
652 |
|
|
reg [15:0] lt24_cmd;
|
653 |
|
|
|
654 |
|
|
wire lt24_cmd_wr = reg_wr[LT24_CMD];
|
655 |
|
|
|
656 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
657 |
|
|
if (puc_rst) lt24_cmd <= 16'h0000;
|
658 |
|
|
else if (lt24_cmd_wr) lt24_cmd <= per_din_i;
|
659 |
|
|
|
660 |
|
|
assign lt24_cmd_val_o = lt24_cmd[7:0];
|
661 |
|
|
assign lt24_cmd_has_param_o = lt24_cmd[8];
|
662 |
|
|
|
663 |
|
|
//------------------------------------------------
|
664 |
|
|
// LT24_CMD_PARAM Register
|
665 |
|
|
//------------------------------------------------
|
666 |
|
|
reg [15:0] lt24_cmd_param_o;
|
667 |
|
|
|
668 |
|
|
wire lt24_cmd_param_wr = reg_wr[LT24_CMD_PARAM];
|
669 |
|
|
|
670 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
671 |
|
|
if (puc_rst) lt24_cmd_param_o <= 16'h0000;
|
672 |
|
|
else if (lt24_cmd_param_wr) lt24_cmd_param_o <= per_din_i;
|
673 |
|
|
|
674 |
|
|
reg lt24_cmd_param_rdy_o;
|
675 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
676 |
|
|
if (puc_rst) lt24_cmd_param_rdy_o <= 1'b0;
|
677 |
|
|
else lt24_cmd_param_rdy_o <= lt24_cmd_param_wr;
|
678 |
|
|
|
679 |
|
|
//------------------------------------------------
|
680 |
|
|
// LT24_CMD_DFILL Register
|
681 |
|
|
//------------------------------------------------
|
682 |
|
|
reg [15:0] lt24_cmd_dfill_o;
|
683 |
|
|
|
684 |
|
|
assign lt24_cmd_dfill_wr_o = reg_wr[LT24_CMD_DFILL];
|
685 |
|
|
|
686 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
687 |
|
|
if (puc_rst) lt24_cmd_dfill_o <= 16'h0000;
|
688 |
|
|
else if (lt24_cmd_dfill_wr_o) lt24_cmd_dfill_o <= per_din_i;
|
689 |
|
|
|
690 |
|
|
//------------------------------------------------
|
691 |
|
|
// LT24_STATUS Register
|
692 |
|
|
//------------------------------------------------
|
693 |
|
|
wire [15:0] lt24_status;
|
694 |
|
|
|
695 |
|
|
assign lt24_status[0] = lt24_status_i[0]; // FSM_BUSY
|
696 |
|
|
assign lt24_status[1] = lt24_status_i[1]; // WAIT_PARAM
|
697 |
|
|
assign lt24_status[2] = lt24_status_i[2]; // REFRESH_BUSY
|
698 |
|
|
assign lt24_status[3] = lt24_status_i[3]; // WAIT_FOR_SCANLINE
|
699 |
|
|
assign lt24_status[4] = lt24_status_i[4]; // DATA_FILL_BUSY
|
700 |
|
|
assign lt24_status[15:5] = 11'h000;
|
701 |
|
|
|
702 |
|
|
|
703 |
|
|
//------------------------------------------------
|
704 |
|
|
// LUT_RAM_ADDR Register
|
705 |
|
|
//------------------------------------------------
|
706 |
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
707 |
|
|
|
708 |
|
|
reg [7:0] lut_ram_addr;
|
709 |
|
|
wire [7:0] lut_ram_addr_inc;
|
710 |
|
|
wire lut_ram_addr_inc_wr;
|
711 |
|
|
|
712 |
|
|
wire lut_ram_addr_wr = reg_wr[LUT_RAM_ADDR];
|
713 |
|
|
|
714 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
715 |
|
|
if (puc_rst) lut_ram_addr <= 8'h00;
|
716 |
|
|
else if (lut_ram_addr_wr) lut_ram_addr <= per_din_i[7:0];
|
717 |
|
|
else if (lut_ram_addr_inc_wr) lut_ram_addr <= lut_ram_addr_inc;
|
718 |
|
|
|
719 |
|
|
assign lut_ram_addr_inc = lut_ram_addr + 8'h01;
|
720 |
|
|
wire [15:0] lut_ram_addr_rd = {8'h00, lut_ram_addr};
|
721 |
|
|
|
722 |
|
|
`ifdef WITH_EXTRA_LUT_BANK
|
723 |
|
|
assign lut_ram_addr_o = {lut_bank_select, lut_ram_addr};
|
724 |
|
|
`else
|
725 |
|
|
assign lut_ram_addr_o = lut_ram_addr;
|
726 |
|
|
`endif
|
727 |
|
|
|
728 |
|
|
`else
|
729 |
|
|
wire [15:0] lut_ram_addr_rd = 16'h0000;
|
730 |
|
|
`endif
|
731 |
|
|
|
732 |
|
|
//------------------------------------------------
|
733 |
|
|
// LUT_RAM_DATA Register
|
734 |
|
|
//------------------------------------------------
|
735 |
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
736 |
|
|
|
737 |
|
|
// Update the LUT_RAM_DATA register with regular register write access
|
738 |
|
|
wire lut_ram_data_wr = reg_wr[LUT_RAM_DATA];
|
739 |
|
|
wire lut_ram_data_rd = reg_rd[LUT_RAM_DATA];
|
740 |
|
|
reg lut_ram_dout_rdy;
|
741 |
|
|
|
742 |
|
|
// LUT-RAM data Register
|
743 |
|
|
reg [15:0] lut_ram_data;
|
744 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
745 |
|
|
if (puc_rst) lut_ram_data <= 16'h0000;
|
746 |
|
|
else if (lut_ram_data_wr) lut_ram_data <= per_din_i;
|
747 |
|
|
else if (lut_ram_dout_rdy) lut_ram_data <= lut_ram_dout_i;
|
748 |
|
|
|
749 |
|
|
// Increment the address after a write or read access to the LUT_RAM_DATA register
|
750 |
|
|
assign lut_ram_addr_inc_wr = lut_ram_data_wr | lut_ram_data_rd;
|
751 |
|
|
|
752 |
|
|
// Apply peripheral data bus % write strobe during VID_RAMx_DATA write access
|
753 |
|
|
assign lut_ram_din_o = per_din_i & {16{lut_ram_data_wr}};
|
754 |
|
|
assign lut_ram_wen_o = ~(|per_we_i & lut_ram_data_wr);
|
755 |
|
|
|
756 |
|
|
// Trigger a LUT-RAM read access immediately after:
|
757 |
|
|
// - a LUT-RAM_ADDR register write access
|
758 |
|
|
// - a LUT-RAM_DATA register read access
|
759 |
|
|
reg lut_ram_addr_wr_dly;
|
760 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
761 |
|
|
if (puc_rst) lut_ram_addr_wr_dly <= 1'b0;
|
762 |
|
|
else lut_ram_addr_wr_dly <= lut_ram_addr_wr;
|
763 |
|
|
|
764 |
|
|
reg lut_ram_data_rd_dly;
|
765 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
766 |
|
|
if (puc_rst) lut_ram_data_rd_dly <= 1'b0;
|
767 |
|
|
else lut_ram_data_rd_dly <= lut_ram_data_rd;
|
768 |
|
|
|
769 |
|
|
// Chip enable.
|
770 |
|
|
// Note: we perform a data read access:
|
771 |
|
|
// - one cycle after a VID_RAM_DATA register read access (so that the address has been incremented)
|
772 |
|
|
// - one cycle after a VID_RAM_ADDR register write
|
773 |
|
|
assign lut_ram_cen_o = ~(lut_ram_addr_wr_dly | lut_ram_data_rd_dly | // Read access
|
774 |
|
|
lut_ram_data_wr); // Write access
|
775 |
|
|
|
776 |
|
|
// Update the VRAM_DATA register one cycle after each memory access
|
777 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
778 |
|
|
if (puc_rst) lut_ram_dout_rdy <= 1'b0;
|
779 |
|
|
else lut_ram_dout_rdy <= ~lut_ram_cen_o;
|
780 |
|
|
|
781 |
|
|
`else
|
782 |
|
|
wire [15:0] lut_ram_data = 16'h0000;
|
783 |
|
|
`endif
|
784 |
|
|
|
785 |
|
|
//------------------------------------------------
|
786 |
|
|
// FRAME_SELECT Register
|
787 |
|
|
//------------------------------------------------
|
788 |
|
|
|
789 |
|
|
wire frame_select_wr = reg_wr[FRAME_SELECT];
|
790 |
|
|
|
791 |
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
792 |
|
|
reg refresh_sw_lut_enable;
|
793 |
|
|
|
794 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
795 |
|
|
if (puc_rst) refresh_sw_lut_enable <= 1'b0;
|
796 |
|
|
else if (frame_select_wr) refresh_sw_lut_enable <= per_din_i[2];
|
797 |
|
|
`else
|
798 |
|
|
wire refresh_sw_lut_enable = 1'b0;
|
799 |
|
|
`endif
|
800 |
|
|
|
801 |
|
|
`ifdef WITH_EXTRA_LUT_BANK
|
802 |
|
|
reg refresh_sw_lut_select;
|
803 |
|
|
|
804 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
805 |
|
|
if (puc_rst)
|
806 |
|
|
begin
|
807 |
|
|
refresh_sw_lut_select <= 1'b0;
|
808 |
|
|
lut_bank_select <= 1'b0;
|
809 |
|
|
end
|
810 |
|
|
else if (frame_select_wr)
|
811 |
|
|
begin
|
812 |
|
|
refresh_sw_lut_select <= per_din_i[3];
|
813 |
|
|
lut_bank_select <= per_din_i[15];
|
814 |
|
|
end
|
815 |
|
|
`else
|
816 |
|
|
assign refresh_sw_lut_select = 1'b0;
|
817 |
|
|
wire lut_bank_select = 1'b0;
|
818 |
|
|
`endif
|
819 |
|
|
wire [1:0] refresh_lut_select_o = {refresh_sw_lut_select, refresh_sw_lut_enable};
|
820 |
|
|
|
821 |
|
|
`ifdef WITH_FRAME1_POINTER
|
822 |
|
|
`ifdef WITH_FRAME2_POINTER
|
823 |
|
|
reg [1:0] refresh_frame_select;
|
824 |
|
|
reg [1:0] vid_ram0_frame_select;
|
825 |
|
|
reg [1:0] vid_ram1_frame_select;
|
826 |
|
|
|
827 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
828 |
|
|
if (puc_rst)
|
829 |
|
|
begin
|
830 |
|
|
refresh_frame_select <= 2'h0;
|
831 |
|
|
vid_ram0_frame_select <= 2'h0;
|
832 |
|
|
vid_ram1_frame_select <= 2'h0;
|
833 |
|
|
end
|
834 |
|
|
else if (frame_select_wr)
|
835 |
|
|
begin
|
836 |
|
|
refresh_frame_select <= per_din_i[1:0];
|
837 |
|
|
vid_ram0_frame_select <= per_din_i[5:4];
|
838 |
|
|
vid_ram1_frame_select <= per_din_i[7:6];
|
839 |
|
|
end
|
840 |
|
|
|
841 |
|
|
wire [15:0] frame_select = {lut_bank_select, 7'h00, vid_ram1_frame_select, vid_ram0_frame_select, refresh_lut_select_o, refresh_frame_select};
|
842 |
|
|
`else
|
843 |
|
|
reg refresh_frame_select;
|
844 |
|
|
reg vid_ram0_frame_select;
|
845 |
|
|
reg vid_ram1_frame_select;
|
846 |
|
|
|
847 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
848 |
|
|
if (puc_rst)
|
849 |
|
|
begin
|
850 |
|
|
refresh_frame_select <= 1'h0;
|
851 |
|
|
vid_ram0_frame_select <= 1'h0;
|
852 |
|
|
vid_ram1_frame_select <= 1'h0;
|
853 |
|
|
end
|
854 |
|
|
else if (frame_select_wr)
|
855 |
|
|
begin
|
856 |
|
|
refresh_frame_select <= per_din_i[0];
|
857 |
|
|
vid_ram0_frame_select <= per_din_i[4];
|
858 |
|
|
vid_ram1_frame_select <= per_din_i[6];
|
859 |
|
|
end
|
860 |
|
|
|
861 |
|
|
wire [15:0] frame_select = {lut_bank_select, 7'h00, 1'h0, vid_ram1_frame_select, 1'h0, vid_ram0_frame_select, refresh_lut_select_o, 1'h0, refresh_frame_select};
|
862 |
|
|
`endif
|
863 |
|
|
`else
|
864 |
|
|
wire [15:0] frame_select = {lut_bank_select, 11'h000, refresh_lut_select_o, 2'h0};
|
865 |
|
|
`endif
|
866 |
|
|
|
867 |
|
|
// Frame pointer selections
|
868 |
|
|
`ifdef WITH_FRAME1_POINTER
|
869 |
|
|
assign refresh_frame_addr_o = (refresh_frame_select==0) ? frame0_ptr :
|
870 |
|
|
`ifdef WITH_FRAME2_POINTER
|
871 |
|
|
(refresh_frame_select==1) ? frame1_ptr :
|
872 |
|
|
`ifdef WITH_FRAME3_POINTER
|
873 |
|
|
(refresh_frame_select==2) ? frame2_ptr :
|
874 |
|
|
frame3_ptr ;
|
875 |
|
|
`else
|
876 |
|
|
frame2_ptr ;
|
877 |
|
|
`endif
|
878 |
|
|
`else
|
879 |
|
|
frame1_ptr ;
|
880 |
|
|
`endif
|
881 |
|
|
|
882 |
|
|
assign vid_ram0_base_addr = (vid_ram0_frame_select==0) ? frame0_ptr :
|
883 |
|
|
`ifdef WITH_FRAME2_POINTER
|
884 |
|
|
(vid_ram0_frame_select==1) ? frame1_ptr :
|
885 |
|
|
`ifdef WITH_FRAME3_POINTER
|
886 |
|
|
(vid_ram0_frame_select==2) ? frame2_ptr :
|
887 |
|
|
frame3_ptr ;
|
888 |
|
|
`else
|
889 |
|
|
frame2_ptr ;
|
890 |
|
|
`endif
|
891 |
|
|
`else
|
892 |
|
|
frame1_ptr ;
|
893 |
|
|
`endif
|
894 |
|
|
|
895 |
|
|
assign vid_ram1_base_addr = (vid_ram1_frame_select==0) ? frame0_ptr :
|
896 |
|
|
`ifdef WITH_FRAME2_POINTER
|
897 |
|
|
(vid_ram1_frame_select==1) ? frame1_ptr :
|
898 |
|
|
`ifdef WITH_FRAME3_POINTER
|
899 |
|
|
(vid_ram1_frame_select==2) ? frame2_ptr :
|
900 |
|
|
frame3_ptr ;
|
901 |
|
|
`else
|
902 |
|
|
frame2_ptr ;
|
903 |
|
|
`endif
|
904 |
|
|
`else
|
905 |
|
|
frame1_ptr ;
|
906 |
|
|
`endif
|
907 |
|
|
|
908 |
|
|
`else
|
909 |
|
|
assign refresh_frame_addr_o = frame0_ptr;
|
910 |
|
|
assign vid_ram0_base_addr = frame0_ptr;
|
911 |
|
|
assign vid_ram1_base_addr = frame0_ptr;
|
912 |
|
|
`endif
|
913 |
|
|
|
914 |
|
|
//------------------------------------------------
|
915 |
|
|
// FRAME0_PTR_HI Register
|
916 |
|
|
//------------------------------------------------
|
917 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
918 |
|
|
reg [`APIX_HI_MSB:0] frame0_ptr_hi;
|
919 |
|
|
|
920 |
|
|
wire frame0_ptr_hi_wr = reg_wr[FRAME0_PTR_HI];
|
921 |
|
|
|
922 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
923 |
|
|
if (puc_rst) frame0_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
924 |
|
|
else if (frame0_ptr_hi_wr) frame0_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
|
925 |
|
|
|
926 |
|
|
wire [16:0] frame0_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame0_ptr_hi};
|
927 |
|
|
wire [15:0] frame0_ptr_hi_rd = frame0_ptr_hi_tmp[15:0];
|
928 |
|
|
`endif
|
929 |
|
|
|
930 |
|
|
//------------------------------------------------
|
931 |
|
|
// FRAME0_PTR_LO Register
|
932 |
|
|
//------------------------------------------------
|
933 |
|
|
reg [`APIX_LO_MSB:0] frame0_ptr_lo;
|
934 |
|
|
|
935 |
|
|
wire frame0_ptr_lo_wr = reg_wr[FRAME0_PTR_LO];
|
936 |
|
|
|
937 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
938 |
|
|
if (puc_rst) frame0_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
939 |
|
|
else if (frame0_ptr_lo_wr) frame0_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
|
940 |
|
|
|
941 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
942 |
|
|
assign frame0_ptr = {frame0_ptr_hi[`APIX_HI_MSB:0], frame0_ptr_lo};
|
943 |
|
|
wire [15:0] frame0_ptr_lo_rd = frame0_ptr_lo;
|
944 |
|
|
`else
|
945 |
|
|
assign frame0_ptr = {frame0_ptr_lo[`APIX_LO_MSB:0]};
|
946 |
|
|
wire [16:0] frame0_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame0_ptr_lo};
|
947 |
|
|
wire [15:0] frame0_ptr_lo_rd = frame0_ptr_lo_tmp[15:0];
|
948 |
|
|
`endif
|
949 |
|
|
|
950 |
|
|
//------------------------------------------------
|
951 |
|
|
// FRAME1_PTR_HI Register
|
952 |
|
|
//------------------------------------------------
|
953 |
|
|
`ifdef WITH_FRAME1_POINTER
|
954 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
955 |
|
|
reg [`APIX_HI_MSB:0] frame1_ptr_hi;
|
956 |
|
|
|
957 |
|
|
wire frame1_ptr_hi_wr = reg_wr[FRAME1_PTR_HI];
|
958 |
|
|
|
959 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
960 |
|
|
if (puc_rst) frame1_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
961 |
|
|
else if (frame1_ptr_hi_wr) frame1_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
|
962 |
|
|
|
963 |
|
|
wire [16:0] frame1_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame1_ptr_hi};
|
964 |
|
|
wire [15:0] frame1_ptr_hi_rd = frame1_ptr_hi_tmp[15:0];
|
965 |
|
|
`endif
|
966 |
|
|
`endif
|
967 |
|
|
|
968 |
|
|
//------------------------------------------------
|
969 |
|
|
// FRAME1_PTR_LO Register
|
970 |
|
|
//------------------------------------------------
|
971 |
|
|
`ifdef WITH_FRAME1_POINTER
|
972 |
|
|
reg [`APIX_LO_MSB:0] frame1_ptr_lo;
|
973 |
|
|
|
974 |
|
|
wire frame1_ptr_lo_wr = reg_wr[FRAME1_PTR_LO];
|
975 |
|
|
|
976 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
977 |
|
|
if (puc_rst) frame1_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
978 |
|
|
else if (frame1_ptr_lo_wr) frame1_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
|
979 |
|
|
|
980 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
981 |
|
|
assign frame1_ptr = {frame1_ptr_hi[`APIX_HI_MSB:0], frame1_ptr_lo};
|
982 |
|
|
wire [15:0] frame1_ptr_lo_rd = frame1_ptr_lo;
|
983 |
|
|
`else
|
984 |
|
|
assign frame1_ptr = {frame1_ptr_lo[`APIX_LO_MSB:0]};
|
985 |
|
|
wire [16:0] frame1_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame1_ptr_lo};
|
986 |
|
|
wire [15:0] frame1_ptr_lo_rd = frame1_ptr_lo_tmp[15:0];
|
987 |
|
|
`endif
|
988 |
|
|
`endif
|
989 |
|
|
|
990 |
|
|
//------------------------------------------------
|
991 |
|
|
// FRAME2_PTR_HI Register
|
992 |
|
|
//------------------------------------------------
|
993 |
|
|
`ifdef WITH_FRAME2_POINTER
|
994 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
995 |
|
|
reg [`APIX_HI_MSB:0] frame2_ptr_hi;
|
996 |
|
|
|
997 |
|
|
wire frame2_ptr_hi_wr = reg_wr[FRAME2_PTR_HI];
|
998 |
|
|
|
999 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
1000 |
|
|
if (puc_rst) frame2_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
1001 |
|
|
else if (frame2_ptr_hi_wr) frame2_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
|
1002 |
|
|
|
1003 |
|
|
wire [16:0] frame2_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame2_ptr_hi};
|
1004 |
|
|
wire [15:0] frame2_ptr_hi_rd = frame2_ptr_hi_tmp[15:0];
|
1005 |
|
|
`endif
|
1006 |
|
|
`endif
|
1007 |
|
|
|
1008 |
|
|
//------------------------------------------------
|
1009 |
|
|
// FRAME2_PTR_LO Register
|
1010 |
|
|
//------------------------------------------------
|
1011 |
|
|
`ifdef WITH_FRAME2_POINTER
|
1012 |
|
|
reg [`APIX_LO_MSB:0] frame2_ptr_lo;
|
1013 |
|
|
|
1014 |
|
|
wire frame2_ptr_lo_wr = reg_wr[FRAME2_PTR_LO];
|
1015 |
|
|
|
1016 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
1017 |
|
|
if (puc_rst) frame2_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
1018 |
|
|
else if (frame2_ptr_lo_wr) frame2_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
|
1019 |
|
|
|
1020 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
1021 |
|
|
assign frame2_ptr = {frame2_ptr_hi[`APIX_HI_MSB:0], frame2_ptr_lo};
|
1022 |
|
|
wire [15:0] frame2_ptr_lo_rd = frame2_ptr_lo;
|
1023 |
|
|
`else
|
1024 |
|
|
assign frame2_ptr = {frame2_ptr_lo[`APIX_LO_MSB:0]};
|
1025 |
|
|
wire [16:0] frame2_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame2_ptr_lo};
|
1026 |
|
|
wire [15:0] frame2_ptr_lo_rd = frame2_ptr_lo_tmp[15:0];
|
1027 |
|
|
`endif
|
1028 |
|
|
`endif
|
1029 |
|
|
|
1030 |
|
|
//------------------------------------------------
|
1031 |
|
|
// FRAME3_PTR_HI Register
|
1032 |
|
|
//------------------------------------------------
|
1033 |
|
|
`ifdef WITH_FRAME3_POINTER
|
1034 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
1035 |
|
|
reg [`APIX_HI_MSB:0] frame3_ptr_hi;
|
1036 |
|
|
|
1037 |
|
|
wire frame3_ptr_hi_wr = reg_wr[FRAME3_PTR_HI];
|
1038 |
|
|
|
1039 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
1040 |
|
|
if (puc_rst) frame3_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
1041 |
|
|
else if (frame3_ptr_hi_wr) frame3_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
|
1042 |
|
|
|
1043 |
|
|
wire [16:0] frame3_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}},frame3_ptr_hi};
|
1044 |
|
|
wire [15:0] frame3_ptr_hi_rd = frame3_ptr_hi_tmp[15:0];
|
1045 |
|
|
`endif
|
1046 |
|
|
`endif
|
1047 |
|
|
|
1048 |
|
|
//------------------------------------------------
|
1049 |
|
|
// FRAME3_PTR_LO Register
|
1050 |
|
|
//------------------------------------------------
|
1051 |
|
|
`ifdef WITH_FRAME3_POINTER
|
1052 |
|
|
reg [`APIX_LO_MSB:0] frame3_ptr_lo;
|
1053 |
|
|
|
1054 |
|
|
wire frame3_ptr_lo_wr = reg_wr[FRAME3_PTR_LO];
|
1055 |
|
|
|
1056 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
1057 |
|
|
if (puc_rst) frame3_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
1058 |
|
|
else if (frame3_ptr_lo_wr) frame3_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
|
1059 |
|
|
|
1060 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
1061 |
|
|
assign frame3_ptr = {frame3_ptr_hi[`APIX_HI_MSB:0], frame3_ptr_lo};
|
1062 |
|
|
wire [15:0] frame3_ptr_lo_rd = frame3_ptr_lo;
|
1063 |
|
|
`else
|
1064 |
|
|
assign frame3_ptr = {frame3_ptr_lo[`APIX_LO_MSB:0]};
|
1065 |
|
|
wire [16:0] frame3_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame3_ptr_lo};
|
1066 |
|
|
wire [15:0] frame3_ptr_lo_rd = frame3_ptr_lo_tmp[15:0];
|
1067 |
|
|
`endif
|
1068 |
|
|
`endif
|
1069 |
|
|
|
1070 |
|
|
//------------------------------------------------
|
1071 |
|
|
// VID_RAM0 Interface
|
1072 |
|
|
//------------------------------------------------
|
1073 |
|
|
wire [15:0] vid_ram0_cfg;
|
1074 |
|
|
wire [15:0] vid_ram0_width;
|
1075 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
1076 |
|
|
wire [15:0] vid_ram0_addr_hi;
|
1077 |
|
|
`endif
|
1078 |
|
|
wire [15:0] vid_ram0_addr_lo;
|
1079 |
|
|
wire [15:0] vid_ram0_data;
|
1080 |
|
|
|
1081 |
|
|
wire vid_ram0_we;
|
1082 |
|
|
wire vid_ram0_ce;
|
1083 |
|
|
wire [15:0] vid_ram0_din;
|
1084 |
|
|
wire [`APIX_MSB:0] vid_ram0_addr_nxt;
|
1085 |
|
|
wire vid_ram0_access;
|
1086 |
|
|
|
1087 |
|
|
ogfx_reg_vram_if ogfx_reg_vram0_if_inst (
|
1088 |
|
|
|
1089 |
|
|
// OUTPUTs
|
1090 |
|
|
.vid_ram_cfg_o ( vid_ram0_cfg ), // VID_RAM0_CFG Register
|
1091 |
|
|
.vid_ram_width_o ( vid_ram0_width ), // VID_RAM0_WIDTH Register
|
1092 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
1093 |
|
|
.vid_ram_addr_hi_o ( vid_ram0_addr_hi ), // VID_RAM0_ADDR_HI Register
|
1094 |
|
|
`endif
|
1095 |
|
|
.vid_ram_addr_lo_o ( vid_ram0_addr_lo ), // VID_RAM0_ADDR_LO Register
|
1096 |
|
|
.vid_ram_data_o ( vid_ram0_data ), // VID_RAM0_DATA Register
|
1097 |
|
|
|
1098 |
|
|
.vid_ram_we_o ( vid_ram0_we ), // Video-RAM Write strobe
|
1099 |
|
|
.vid_ram_ce_o ( vid_ram0_ce ), // Video-RAM Chip enable
|
1100 |
|
|
.vid_ram_din_o ( vid_ram0_din ), // Video-RAM Data input
|
1101 |
|
|
.vid_ram_addr_nxt_o ( vid_ram0_addr_nxt ), // Video-RAM Next address
|
1102 |
|
|
.vid_ram_access_o ( vid_ram0_access ), // Video-RAM Access
|
1103 |
|
|
|
1104 |
|
|
// INPUTs
|
1105 |
|
|
.mclk ( mclk ), // Main system clock
|
1106 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
1107 |
|
|
|
1108 |
|
|
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM0_CFG] ), // VID_RAM0_CFG Write strobe
|
1109 |
|
|
.vid_ram_width_wr_i ( reg_wr[VID_RAM0_WIDTH] ), // VID_RAM0_WIDTH Write strobe
|
1110 |
|
|
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM0_ADDR_HI] ), // VID_RAM0_ADDR_HI Write strobe
|
1111 |
|
|
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM0_ADDR_LO] ), // VID_RAM0_ADDR_LO Write strobe
|
1112 |
|
|
.vid_ram_data_wr_i ( reg_wr[VID_RAM0_DATA] ), // VID_RAM0_DATA Write strobe
|
1113 |
|
|
.vid_ram_data_rd_i ( reg_rd[VID_RAM0_DATA] ), // VID_RAM0_DATA Read strobe
|
1114 |
|
|
|
1115 |
|
|
.dbg_freeze_i ( dbg_freeze_i ), // Freeze auto-increment on read when CPU stopped
|
1116 |
|
|
.display_width_i ( display_width_o ), // Display width
|
1117 |
|
|
.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
|
1118 |
|
|
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
|
1119 |
|
|
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
|
1120 |
|
|
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
|
1121 |
|
|
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
|
1122 |
|
|
|
1123 |
|
|
.per_din_i ( per_din_i ), // Peripheral data input
|
1124 |
|
|
.vid_ram_base_addr_i ( vid_ram0_base_addr ), // Video-RAM base address
|
1125 |
|
|
.vid_ram_dout_i ( vid_ram_dout_i ) // Video-RAM data input
|
1126 |
|
|
);
|
1127 |
|
|
|
1128 |
|
|
//------------------------------------------------
|
1129 |
|
|
// VID_RAM1 Interface
|
1130 |
|
|
//------------------------------------------------
|
1131 |
|
|
wire [15:0] vid_ram1_cfg;
|
1132 |
|
|
wire [15:0] vid_ram1_width;
|
1133 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
1134 |
|
|
wire [15:0] vid_ram1_addr_hi;
|
1135 |
|
|
`endif
|
1136 |
|
|
wire [15:0] vid_ram1_addr_lo;
|
1137 |
|
|
wire [15:0] vid_ram1_data;
|
1138 |
|
|
|
1139 |
|
|
wire vid_ram1_we;
|
1140 |
|
|
wire vid_ram1_ce;
|
1141 |
|
|
wire [15:0] vid_ram1_din;
|
1142 |
|
|
wire [`APIX_MSB:0] vid_ram1_addr_nxt;
|
1143 |
|
|
wire vid_ram1_access;
|
1144 |
|
|
|
1145 |
|
|
ogfx_reg_vram_if ogfx_reg_vram1_if_inst (
|
1146 |
|
|
|
1147 |
|
|
// OUTPUTs
|
1148 |
|
|
.vid_ram_cfg_o ( vid_ram1_cfg ), // VID_RAM1_CFG Register
|
1149 |
|
|
.vid_ram_width_o ( vid_ram1_width ), // VID_RAM1_WIDTH Register
|
1150 |
|
|
`ifdef VRAM_BIGGER_4_KW
|
1151 |
|
|
.vid_ram_addr_hi_o ( vid_ram1_addr_hi ), // VID_RAM1_ADDR_HI Register
|
1152 |
|
|
`endif
|
1153 |
|
|
.vid_ram_addr_lo_o ( vid_ram1_addr_lo ), // VID_RAM1_ADDR_LO Register
|
1154 |
|
|
.vid_ram_data_o ( vid_ram1_data ), // VID_RAM1_DATA Register
|
1155 |
|
|
|
1156 |
|
|
.vid_ram_we_o ( vid_ram1_we ), // Video-RAM Write strobe
|
1157 |
|
|
.vid_ram_ce_o ( vid_ram1_ce ), // Video-RAM Chip enable
|
1158 |
|
|
.vid_ram_din_o ( vid_ram1_din ), // Video-RAM Data input
|
1159 |
|
|
.vid_ram_addr_nxt_o ( vid_ram1_addr_nxt ), // Video-RAM Next address
|
1160 |
|
|
.vid_ram_access_o ( vid_ram1_access ), // Video-RAM Access
|
1161 |
|
|
|
1162 |
|
|
// INPUTs
|
1163 |
|
|
.mclk ( mclk ), // Main system clock
|
1164 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
1165 |
|
|
|
1166 |
|
|
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM1_CFG] ), // VID_RAM1_CFG Write strobe
|
1167 |
|
|
.vid_ram_width_wr_i ( reg_wr[VID_RAM1_WIDTH] ), // VID_RAM1_WIDTH Write strobe
|
1168 |
|
|
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM1_ADDR_HI] ), // VID_RAM1_ADDR_HI Write strobe
|
1169 |
|
|
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM1_ADDR_LO] ), // VID_RAM1_ADDR_LO Write strobe
|
1170 |
|
|
.vid_ram_data_wr_i ( reg_wr[VID_RAM1_DATA] ), // VID_RAM1_DATA Write strobe
|
1171 |
|
|
.vid_ram_data_rd_i ( reg_rd[VID_RAM1_DATA] ), // VID_RAM1_DATA Read strobe
|
1172 |
|
|
|
1173 |
|
|
.dbg_freeze_i ( dbg_freeze_i ), // Freeze auto-increment on read when CPU stopped
|
1174 |
|
|
.display_width_i ( display_width_o ), // Display width
|
1175 |
|
|
.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
|
1176 |
|
|
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
|
1177 |
|
|
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
|
1178 |
|
|
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
|
1179 |
|
|
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
|
1180 |
|
|
|
1181 |
|
|
.per_din_i ( per_din_i ), // Peripheral data input
|
1182 |
|
|
.vid_ram_base_addr_i ( vid_ram1_base_addr ), // Video-RAM base address
|
1183 |
|
|
.vid_ram_dout_i ( vid_ram_dout_i ) // Video-RAM data input
|
1184 |
|
|
);
|
1185 |
|
|
|
1186 |
|
|
//------------------------------------------------
|
1187 |
|
|
// GPU Interface (GPU_CMD/GPU_STAT) Registers
|
1188 |
|
|
//------------------------------------------------
|
1189 |
|
|
|
1190 |
|
|
wire [3:0] gpu_stat_fifo_cnt;
|
1191 |
6 |
olivier.gi |
wire [3:0] gpu_stat_fifo_cnt_empty;
|
1192 |
3 |
olivier.gi |
wire gpu_stat_fifo_empty;
|
1193 |
|
|
wire gpu_stat_fifo_full;
|
1194 |
6 |
olivier.gi |
wire gpu_stat_fifo_full_less_2;
|
1195 |
|
|
wire gpu_stat_fifo_full_less_3;
|
1196 |
3 |
olivier.gi |
|
1197 |
|
|
ogfx_reg_fifo ogfx_reg_fifo_gpu_inst (
|
1198 |
|
|
|
1199 |
|
|
// OUTPUTs
|
1200 |
|
|
.fifo_cnt_o ( gpu_stat_fifo_cnt ), // Fifo counter
|
1201 |
|
|
.fifo_data_o ( gpu_data_o ), // Read data output
|
1202 |
|
|
.fifo_done_evt_o ( gpu_fifo_done_evt ), // Fifo has been emptied
|
1203 |
|
|
.fifo_empty_o ( gpu_stat_fifo_empty ), // Fifo is currentely empty
|
1204 |
6 |
olivier.gi |
.fifo_empty_cnt_o ( gpu_stat_fifo_cnt_empty ), // Fifo empty words counter
|
1205 |
3 |
olivier.gi |
.fifo_full_o ( gpu_stat_fifo_full ), // Fifo is currentely full
|
1206 |
|
|
.fifo_ovfl_evt_o ( gpu_fifo_ovfl_evt ), // Fifo overflow event
|
1207 |
|
|
|
1208 |
|
|
// INPUTs
|
1209 |
|
|
.mclk ( mclk ), // Main system clock
|
1210 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
1211 |
|
|
|
1212 |
|
|
.fifo_data_i ( per_din_i ), // Read data input
|
1213 |
|
|
.fifo_enable_i ( gpu_enable_o ), // Enable fifo (flushed when disabled)
|
1214 |
|
|
.fifo_pop_i ( gpu_get_data_i ), // Pop data from the fifo
|
1215 |
6 |
olivier.gi |
.fifo_push_i ( reg_wr[GPU_CMD_LO] |
|
1216 |
|
|
reg_wr[GPU_CMD_HI] ) // Push new data to the fifo
|
1217 |
3 |
olivier.gi |
);
|
1218 |
|
|
|
1219 |
|
|
assign gpu_data_avail_o = ~gpu_stat_fifo_empty;
|
1220 |
|
|
|
1221 |
6 |
olivier.gi |
wire gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
|
1222 |
3 |
olivier.gi |
|
1223 |
6 |
olivier.gi |
wire [15:0] gpu_stat = {gpu_busy, 2'b00, gpu_dma_busy_i,
|
1224 |
|
|
2'b00 , gpu_stat_fifo_full, gpu_stat_fifo_empty,
|
1225 |
|
|
gpu_stat_fifo_cnt, gpu_stat_fifo_cnt_empty};
|
1226 |
3 |
olivier.gi |
|
1227 |
6 |
olivier.gi |
|
1228 |
3 |
olivier.gi |
//============================================================================
|
1229 |
|
|
// 4) DATA OUTPUT GENERATION
|
1230 |
|
|
//============================================================================
|
1231 |
|
|
|
1232 |
|
|
// Data output mux
|
1233 |
|
|
wire [15:0] gfx_ctrl_read = gfx_ctrl & {16{reg_rd[GFX_CTRL ]}};
|
1234 |
|
|
wire [15:0] gfx_status_read = gfx_status & {16{reg_rd[GFX_STATUS ]}};
|
1235 |
|
|
wire [15:0] gfx_irq_read = gfx_irq & {16{reg_rd[GFX_IRQ ]}};
|
1236 |
|
|
|
1237 |
|
|
wire [15:0] display_width_read = display_width_rd & {16{reg_rd[DISPLAY_WIDTH ]}};
|
1238 |
|
|
wire [15:0] display_height_read = display_height_rd & {16{reg_rd[DISPLAY_HEIGHT ]}};
|
1239 |
6 |
olivier.gi |
wire [15:0] display_size_lo_read = display_size_lo_rd & {16{reg_rd[DISPLAY_SIZE_LO ]}};
|
1240 |
3 |
olivier.gi |
`ifdef WITH_DISPLAY_SIZE_HI
|
1241 |
|
|
wire [15:0] display_size_hi_read = display_size_hi_rd & {16{reg_rd[DISPLAY_SIZE_HI ]}};
|
1242 |
|
|
`endif
|
1243 |
|
|
wire [15:0] display_cfg_read = display_cfg & {16{reg_rd[DISPLAY_CFG ]}};
|
1244 |
8 |
olivier.gi |
wire [15:0] display_refr_cnt_read = display_refr_cnt & {16{reg_rd[DISPLAY_REFR_CNT ]}};
|
1245 |
3 |
olivier.gi |
|
1246 |
|
|
wire [15:0] lt24_cfg_read = lt24_cfg & {16{reg_rd[LT24_CFG ]}};
|
1247 |
|
|
wire [15:0] lt24_refresh_read = lt24_refresh & {16{reg_rd[LT24_REFRESH ]}};
|
1248 |
|
|
wire [15:0] lt24_refresh_sync_read = lt24_refresh_sync & {16{reg_rd[LT24_REFRESH_SYNC ]}};
|
1249 |
|
|
wire [15:0] lt24_cmd_read = lt24_cmd & {16{reg_rd[LT24_CMD ]}};
|
1250 |
|
|
wire [15:0] lt24_cmd_param_read = lt24_cmd_param_o & {16{reg_rd[LT24_CMD_PARAM ]}};
|
1251 |
|
|
wire [15:0] lt24_cmd_dfill_read = lt24_cmd_dfill_o & {16{reg_rd[LT24_CMD_DFILL ]}};
|
1252 |
|
|
wire [15:0] lt24_status_read = lt24_status & {16{reg_rd[LT24_STATUS ]}};
|
1253 |
|
|
|
1254 |
|
|
wire [15:0] lut_ram_addr_read = lut_ram_addr_rd & {16{reg_rd[LUT_RAM_ADDR ]}};
|
1255 |
|
|
wire [15:0] lut_ram_data_read = lut_ram_data & {16{reg_rd[LUT_RAM_DATA ]}};
|
1256 |
|
|
|
1257 |
|
|
wire [15:0] frame_select_read = frame_select & {16{reg_rd[FRAME_SELECT ]}};
|
1258 |
6 |
olivier.gi |
wire [15:0] frame0_ptr_lo_read = frame0_ptr_lo_rd & {16{reg_rd[FRAME0_PTR_LO ]}};
|
1259 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1260 |
|
|
wire [15:0] frame0_ptr_hi_read = frame0_ptr_hi_rd & {16{reg_rd[FRAME0_PTR_HI ]}};
|
1261 |
|
|
`endif
|
1262 |
|
|
`ifdef WITH_FRAME1_POINTER
|
1263 |
6 |
olivier.gi |
wire [15:0] frame1_ptr_lo_read = frame1_ptr_lo_rd & {16{reg_rd[FRAME1_PTR_LO ]}};
|
1264 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1265 |
|
|
wire [15:0] frame1_ptr_hi_read = frame1_ptr_hi_rd & {16{reg_rd[FRAME1_PTR_HI ]}};
|
1266 |
|
|
`endif
|
1267 |
|
|
`endif
|
1268 |
|
|
`ifdef WITH_FRAME2_POINTER
|
1269 |
6 |
olivier.gi |
wire [15:0] frame2_ptr_lo_read = frame2_ptr_lo_rd & {16{reg_rd[FRAME2_PTR_LO ]}};
|
1270 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1271 |
|
|
wire [15:0] frame2_ptr_hi_read = frame2_ptr_hi_rd & {16{reg_rd[FRAME2_PTR_HI ]}};
|
1272 |
|
|
`endif
|
1273 |
|
|
`endif
|
1274 |
|
|
`ifdef WITH_FRAME3_POINTER
|
1275 |
6 |
olivier.gi |
wire [15:0] frame3_ptr_lo_read = frame3_ptr_lo_rd & {16{reg_rd[FRAME3_PTR_LO ]}};
|
1276 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1277 |
|
|
wire [15:0] frame3_ptr_hi_read = frame3_ptr_hi_rd & {16{reg_rd[FRAME3_PTR_HI ]}};
|
1278 |
|
|
`endif
|
1279 |
|
|
`endif
|
1280 |
|
|
wire [15:0] vid_ram0_cfg_read = vid_ram0_cfg & {16{reg_rd[VID_RAM0_CFG ]}};
|
1281 |
|
|
wire [15:0] vid_ram0_width_read = vid_ram0_width & {16{reg_rd[VID_RAM0_WIDTH ]}};
|
1282 |
6 |
olivier.gi |
wire [15:0] vid_ram0_addr_lo_read = vid_ram0_addr_lo & {16{reg_rd[VID_RAM0_ADDR_LO ]}};
|
1283 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1284 |
|
|
wire [15:0] vid_ram0_addr_hi_read = vid_ram0_addr_hi & {16{reg_rd[VID_RAM0_ADDR_HI ]}};
|
1285 |
|
|
`endif
|
1286 |
|
|
wire [15:0] vid_ram0_data_read = vid_ram0_data & {16{reg_rd[VID_RAM0_DATA ]}};
|
1287 |
|
|
|
1288 |
|
|
wire [15:0] vid_ram1_cfg_read = vid_ram1_cfg & {16{reg_rd[VID_RAM1_CFG ]}};
|
1289 |
|
|
wire [15:0] vid_ram1_width_read = vid_ram1_width & {16{reg_rd[VID_RAM1_WIDTH ]}};
|
1290 |
6 |
olivier.gi |
wire [15:0] vid_ram1_addr_lo_read = vid_ram1_addr_lo & {16{reg_rd[VID_RAM1_ADDR_LO ]}};
|
1291 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1292 |
|
|
wire [15:0] vid_ram1_addr_hi_read = vid_ram1_addr_hi & {16{reg_rd[VID_RAM1_ADDR_HI ]}};
|
1293 |
|
|
`endif
|
1294 |
|
|
wire [15:0] vid_ram1_data_read = vid_ram1_data & {16{reg_rd[VID_RAM1_DATA ]}};
|
1295 |
6 |
olivier.gi |
wire [15:0] gpu_cmd_lo_read = 16'h0000 & {16{reg_rd[GPU_CMD_LO ]}};
|
1296 |
|
|
wire [15:0] gpu_cmd_hi_read = 16'h0000 & {16{reg_rd[GPU_CMD_HI ]}};
|
1297 |
3 |
olivier.gi |
wire [15:0] gpu_stat_read = gpu_stat & {16{reg_rd[GPU_STAT ]}};
|
1298 |
|
|
|
1299 |
|
|
|
1300 |
|
|
wire [15:0] per_dout_o = gfx_ctrl_read |
|
1301 |
|
|
gfx_status_read |
|
1302 |
|
|
gfx_irq_read |
|
1303 |
|
|
|
1304 |
|
|
display_width_read |
|
1305 |
|
|
display_height_read |
|
1306 |
6 |
olivier.gi |
display_size_lo_read |
|
1307 |
3 |
olivier.gi |
`ifdef WITH_DISPLAY_SIZE_HI
|
1308 |
|
|
display_size_hi_read |
|
1309 |
|
|
`endif
|
1310 |
|
|
display_cfg_read |
|
1311 |
8 |
olivier.gi |
display_refr_cnt_read |
|
1312 |
3 |
olivier.gi |
|
1313 |
|
|
lt24_cfg_read |
|
1314 |
|
|
lt24_refresh_read |
|
1315 |
|
|
lt24_refresh_sync_read |
|
1316 |
|
|
lt24_cmd_read |
|
1317 |
|
|
lt24_cmd_param_read |
|
1318 |
|
|
lt24_cmd_dfill_read |
|
1319 |
|
|
lt24_status_read |
|
1320 |
|
|
|
1321 |
|
|
lut_ram_addr_read |
|
1322 |
|
|
lut_ram_data_read |
|
1323 |
|
|
|
1324 |
|
|
frame_select_read |
|
1325 |
6 |
olivier.gi |
frame0_ptr_lo_read |
|
1326 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1327 |
|
|
frame0_ptr_hi_read |
|
1328 |
|
|
`endif
|
1329 |
|
|
`ifdef WITH_FRAME1_POINTER
|
1330 |
6 |
olivier.gi |
frame1_ptr_lo_read |
|
1331 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1332 |
|
|
frame1_ptr_hi_read |
|
1333 |
|
|
`endif
|
1334 |
|
|
`endif
|
1335 |
|
|
`ifdef WITH_FRAME2_POINTER
|
1336 |
6 |
olivier.gi |
frame2_ptr_lo_read |
|
1337 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1338 |
|
|
frame2_ptr_hi_read |
|
1339 |
|
|
`endif
|
1340 |
|
|
`endif
|
1341 |
|
|
`ifdef WITH_FRAME3_POINTER
|
1342 |
6 |
olivier.gi |
frame3_ptr_lo_read |
|
1343 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1344 |
|
|
frame3_ptr_hi_read |
|
1345 |
|
|
`endif
|
1346 |
|
|
`endif
|
1347 |
|
|
vid_ram0_cfg_read |
|
1348 |
|
|
vid_ram0_width_read |
|
1349 |
6 |
olivier.gi |
vid_ram0_addr_lo_read |
|
1350 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1351 |
|
|
vid_ram0_addr_hi_read |
|
1352 |
|
|
`endif
|
1353 |
|
|
vid_ram0_data_read |
|
1354 |
|
|
|
1355 |
|
|
vid_ram1_cfg_read |
|
1356 |
|
|
vid_ram1_width_read |
|
1357 |
6 |
olivier.gi |
vid_ram1_addr_lo_read |
|
1358 |
3 |
olivier.gi |
`ifdef VRAM_BIGGER_4_KW
|
1359 |
|
|
vid_ram1_addr_hi_read |
|
1360 |
|
|
`endif
|
1361 |
|
|
vid_ram1_data_read |
|
1362 |
6 |
olivier.gi |
gpu_cmd_lo_read |
|
1363 |
|
|
gpu_cmd_hi_read |
|
1364 |
3 |
olivier.gi |
gpu_stat_read;
|
1365 |
|
|
|
1366 |
|
|
|
1367 |
|
|
//============================================================================
|
1368 |
|
|
// 5) VIDEO MEMORY INTERFACE
|
1369 |
|
|
//============================================================================
|
1370 |
|
|
|
1371 |
|
|
// Write access strobe
|
1372 |
6 |
olivier.gi |
assign vid_ram_wen_o = ~(vid_ram0_we | vid_ram1_we );
|
1373 |
3 |
olivier.gi |
|
1374 |
|
|
// Chip enable.
|
1375 |
6 |
olivier.gi |
assign vid_ram_cen_o = ~(vid_ram0_ce | vid_ram1_ce );
|
1376 |
3 |
olivier.gi |
|
1377 |
|
|
// Data to be written
|
1378 |
6 |
olivier.gi |
assign vid_ram_din_o = (vid_ram0_din | vid_ram1_din );
|
1379 |
3 |
olivier.gi |
|
1380 |
|
|
// Detect memory accesses for ADDR update
|
1381 |
6 |
olivier.gi |
wire vid_ram_access = (vid_ram0_access | vid_ram1_access );
|
1382 |
3 |
olivier.gi |
|
1383 |
|
|
// Next Address
|
1384 |
|
|
wire [`APIX_MSB:0] vid_ram_addr_nxt = (vid_ram0_addr_nxt | vid_ram1_addr_nxt);
|
1385 |
|
|
|
1386 |
|
|
// Align according to graphic mode
|
1387 |
|
|
wire [`VRAM_MSB:0] vid_ram_addr_align = ({`VRAM_AWIDTH{gfx_mode_1_bpp }} & vid_ram_addr_nxt[`APIX_MSB-0:4]) |
|
1388 |
|
|
({`VRAM_AWIDTH{gfx_mode_2_bpp }} & vid_ram_addr_nxt[`APIX_MSB-1:3]) |
|
1389 |
|
|
({`VRAM_AWIDTH{gfx_mode_4_bpp }} & vid_ram_addr_nxt[`APIX_MSB-2:2]) |
|
1390 |
|
|
({`VRAM_AWIDTH{gfx_mode_8_bpp }} & vid_ram_addr_nxt[`APIX_MSB-3:1]) |
|
1391 |
|
|
({`VRAM_AWIDTH{gfx_mode_16_bpp}} & vid_ram_addr_nxt[`APIX_MSB-4:0]) ;
|
1392 |
|
|
|
1393 |
|
|
// Generate Video RAM address
|
1394 |
|
|
reg [`VRAM_MSB:0] vid_ram_addr_o;
|
1395 |
|
|
always @ (posedge mclk or posedge puc_rst)
|
1396 |
|
|
if (puc_rst) vid_ram_addr_o <= {`VRAM_AWIDTH{1'b0}};
|
1397 |
|
|
else if (vid_ram_access) vid_ram_addr_o <= vid_ram_addr_align;
|
1398 |
|
|
|
1399 |
|
|
|
1400 |
|
|
endmodule // ogfx_reg
|
1401 |
|
|
|
1402 |
|
|
`ifdef OGFX_NO_INCLUDE
|
1403 |
|
|
`else
|
1404 |
|
|
`include "openGFX430_undefines.v"
|
1405 |
|
|
`endif
|