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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: openhmc_counter48
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*
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*/
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`default_nettype none
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module openhmc_counter48 #(
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parameter DATASIZE = 16 // width of the counter, must be <=48 bits!
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) (
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input wire clk,
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input wire res_n,
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input wire increment,
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input wire load_enable,
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output wire [DATASIZE-1:0] value
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);
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reg [DATASIZE-1:0] value_reg;
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reg load_enable_reg;
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assign value = value_reg;
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) `else
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always @(posedge clk) `endif
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begin
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if(!res_n) begin
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value_reg <= {DATASIZE{1'b0}};
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load_enable_reg <= 1'b0;
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end else begin
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load_enable_reg <= load_enable;
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case ({load_enable_reg,increment})
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2'b00:
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value_reg <= value_reg;
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2'b01:
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value_reg <= (value_reg + 1'b1);
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2'b10:
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value_reg <= {DATASIZE{1'b0}};
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2'b11:
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value_reg <= {DATASIZE{1'b0}} + 1'b1;
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endcase
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end
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end
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endmodule
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`default_nettype wire
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