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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: openhmc_counter48_wrapper_xilinx
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*/
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`default_nettype none
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module openhmc_counter48_wrapper_xilinx #(
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parameter DATASIZE = 48, // width of the counter, must be <=48 bits!
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parameter INC_SIZE = 1, // must be <= 18bits
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parameter PIPELINED = 1
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) (
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input wire clk,
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input wire res_n,
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input wire [INC_SIZE-1:0] inc_value,
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output wire [DATASIZE-1:0] value
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);
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`ifdef SIMULATION
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initial
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begin
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if (DATASIZE > 48)
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begin
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$display ("unsupported DATASIZE parameter in counter48.\nMax value is 48, actual value is %2d", DATASIZE);
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$stop;
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end
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end
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`endif
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wire [47:0] value_w;
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DSP48E1 #(
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.ACASCREG(0), // Number of pipeline registers between A/ACIN input and ACOUT output,
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// 0, 1, or 2
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.ADREG(PIPELINED), // Number of pipeline registers on pre-adder output, 0 or 1
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.ALUMODEREG(PIPELINED), // Number of pipeline registers on ALUMODE input, 0 or 1
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.AREG(0), // Number of pipeline registers on the A input, 0, 1 or 2
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.AUTORESET_PATDET("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH
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.A_INPUT("DIRECT"), // Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port)
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.BCASCREG(PIPELINED), // Number of pipeline registers between B/BCIN input and BCOUT output,
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// 0, 1, or 2
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.BREG(PIPELINED), // Number of pipeline registers on the B input, 0, 1 or 2
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.B_INPUT("DIRECT"), // Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port)
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.CARRYINREG(1), // Number of pipeline registers for the CARRYIN input, 0 or 1
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.CARRYINSELREG(1), // Number of pipeline registers for the CARRYINSEL input, 0 or 1
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.CREG(0), // Number of pipeline registers on the C input, 0 or 1
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.DREG(0), // Number of pipeline registers on the D input, 0 or 1
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.INMODEREG(1), // Number of pipeline registers on INMODE input, 0 or 1
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.MASK(48'h3fffffffffff), // 48-bit Mask value for pattern detect
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.MREG(0), // Number of multiplier pipeline registers, 0 or 1
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.OPMODEREG(1), // Number of pipeline registers on OPMODE input, 0 or 1
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.PATTERN(48'h000000000000), // 48-bit Pattern match for pattern detect
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.PREG(1), // Number of pipeline registers on the P output, 0 or 1
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.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
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.SEL_PATTERN("PATTERN"), // Select pattern value between the "PATTERN" value or the value on the
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// "C" port
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.USE_DPORT("FALSE"), // Select D port usage, TRUE or FALSE
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.USE_MULT("NONE"), // Select multiplier usage, "MULTIPLY", "DYNAMIC", or "NONE" (no multiplier)
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.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect, "PATDET", "NO_PATDET"
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.USE_SIMD("ONE48") // SIMD selection, "ONE48", "TWO24", "FOUR12"
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) DSP48E1_inst (
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// Cascade: 30-bit (each) Cascade
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.ACOUT(), // 30-bit A port cascade output
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.BCOUT(), // 18-bit B port cascade output
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.CARRYCASCOUT(), // 1-bit cascade carry output
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.MULTSIGNOUT(), // 1-bit multiplier sign cascade output
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.PCOUT(), // 48-bit cascade output
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// Control: 1-bit (each) Control
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.OVERFLOW(), // 1-bit overflow in add/acc output
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.PATTERNBDETECT(), // 1-bit active high pattern bar detect output
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.PATTERNDETECT(), // 1-bit active high pattern detect output
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.UNDERFLOW(), // 1-bit active high underflow in add/acc output
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// Data: 4-bit (each) Data
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.CARRYOUT(), // 4-bit carry output
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.P(value_w), // 48-bit output
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// Cascade: 30-bit (each) Cascade
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.ACIN(30'b0), // 30-bit A cascade data input
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.BCIN(18'b0), // 18-bit B cascade input
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.CARRYCASCIN(1'b0), // 1-bit cascade carry input
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.MULTSIGNIN(1'b0), // 1-bit multiplier sign input
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.PCIN(48'b0), // 48-bit P cascade input
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// Control: 4-bit (each) Control
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.ALUMODE(4'b0000), // 4-bit ALU control input
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.CARRYINSEL(3'b000), // 3-bit carry select input
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.CEINMODE(1'b0), // 1-bit active high clock enable input for INMODE registers
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.CLK(clk), // 1-bit Clock input
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.INMODE(5'b00000), // 5-bit INMODE control input
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.OPMODE({1'b0, 1'b1, 1'b0, 4'b0011}), // 7-bit operation mode input
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.RSTINMODE(!res_n), // 1-bit reset input for INMODE pipeline registers
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// Data: 30-bit (each) Data
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.A(30'b0), // 30-bit A data input
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.B({{18-INC_SIZE{1'b0}}, inc_value}), // 18-bit B data input
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.C(48'h0), // 48-bit C data input
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.CARRYIN(1'b0), // 1-bit carry input signal
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.D(25'b0), // 25-bit D data input
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// Reset/Clock Enable: 1-bit (each) Reset/Clock Enable
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.CEA1(1'b0), // 1-bit active high clock enable input for 1st stage A registers
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.CEA2(1'b0), // 1-bit active high clock enable input for 2nd stage A registers
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.CEAD(1'b0), // 1-bit active high clock enable input for pre-adder output registers
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.CEALUMODE(1'b1), // 1-bit active high clock enable input for ALUMODE registers
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.CEB1(1'b0), // 1-bit active high clock enable input for 1st stage B registers
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.CEB2(1'b1), // 1-bit active high clock enable input for 2nd stage B registers
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.CEC(1'b0), // 1-bit active high clock enable input for C registers
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.CECARRYIN(1'b0), // 1-bit active high clock enable input for CARRYIN register
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.CECTRL(1'b1), // 1-bit active high clock enable input for OPMODE and carry registers
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.CED(1'b0), // 1-bit active high clock enable input for D registers
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.CEM(1'b0), // 1-bit active high clock enable input for multiplier registers
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.CEP(1'b1), // 1-bit active high clock enable input for P registers
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.RSTA(1'b0), // 1-bit reset input for A pipeline registers
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.RSTALLCARRYIN(1'b0), // 1-bit reset input for carry pipeline registers
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.RSTALUMODE(1'b0), // 1-bit reset input for ALUMODE pipeline registers
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.RSTB(!res_n), // 1-bit reset input for B pipeline registers
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.RSTC(1'b0), // 1-bit reset input for C pipeline registers
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.RSTCTRL(!res_n), // 1-bit reset input for OPMODE pipeline registers
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.RSTD(1'b0), // 1-bit reset input for D pipeline registers
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.RSTM(1'b0), // 1-bit reset input for multiplier registers
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.RSTP(!res_n) // 1-bit reset input for P pipeline registers
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);
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generate
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if(PIPELINED==1) begin
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reg [DATASIZE-1:0] value_temp;
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always @(posedge clk) begin
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value_temp <= value_w[DATASIZE-1:0];
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end
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assign value=value_temp;
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end else begin
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assign value = value_w[DATASIZE-1:0];
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end
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endgenerate
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endmodule
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`default_nettype wire
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