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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: openhmc_sync_fifo_reg_stage
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*
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*/
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`default_nettype none
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module openhmc_sync_fifo_reg_stage #(parameter DWIDTH = 8)(
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input wire clk,
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input wire res_n,
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input wire [DWIDTH-1:0] d_in,
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input wire [DWIDTH-1:0] d_in_p,
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input wire p_full, // full signal from the previous stage
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input wire n_full, // full signal from the next stage
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input wire si,
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input wire so,
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output reg full, // full = '1' -> this stage has a valid entry
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output reg [DWIDTH-1:0] d_out
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);
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//=====================================================================================================
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//-----------------------------------------------------------------------------------------------------
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//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------------------
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//=====================================================================================================
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wire en, muxi;
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assign en = (si & so & full) // so and si, shift through
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| (si & ~so & ~full && n_full) // shift in new value
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| (~si & so & p_full); // shift through
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assign muxi = (si & ~so) | (si & so & ~p_full & full);
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//=====================================================================================================
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//-----------------------------------------------------------------------------------------------------
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//---------LOGIC STARTS HERE---------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------------------
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//=====================================================================================================
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always @ (posedge clk or negedge res_n) begin
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if (!res_n) begin
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full <= 1'b0;
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d_out <= {DWIDTH{1'b0}};
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end else begin
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if (en) begin
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if (muxi) begin
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d_out <= d_in; // enter new value when enabled
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end else begin
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d_out <= d_in_p; // shift through
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end
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end
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full <= (full & si) // stay full while si to other stage
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| (full & ~si & ~so) // hold full
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| (~si & so & p_full) // keep full as long as prev stage is full
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| (si & ~so & n_full); // fill this stage by si
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end
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end
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endmodule
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`default_nettype wire
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