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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: openhmc_srl_fifo_16
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*
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*/
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`default_nettype none
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module openhmc_srl_fifo_16 #(
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`ifdef CAG_ASSERTIONS
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parameter DISABLE_EMPTY_ASSERT = 0,
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parameter DISABLE_FULL_ASSERT = 0,
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`endif
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parameter DWIDTH = 8
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) (
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input wire clk,
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input wire res_n,
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input wire [DWIDTH-1:0] d_in,
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input wire shift_in,
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input wire shift_out,
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output wire [DWIDTH-1:0]d_out,
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output reg full,
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output reg empty,
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output reg almost_full,
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output reg almost_empty
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);
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reg [3:0] count;
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wire shift_out_notempty;
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wire shift_in_notfull;
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genvar i;
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assign shift_out_notempty = (shift_out && !empty);
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assign shift_in_notfull = (shift_in && !full);
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generate
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for (i=0; i < DWIDTH; i=i+1)
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begin: generate_SRL16
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SRL16E #(.INIT(16'h0000)) SRL16_I (
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.Q(d_out[i]), // SRL data output
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.A0(count[0]), // Select[0] input
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.A1(count[1]), // Select[1] input
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.A2(count[2]), // Select[2] input
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.A3(count[3]), // Select[3] input
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.CLK(clk),
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.D(d_in[i]), // SRL data input
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.CE(shift_in_notfull)
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);
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end
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endgenerate
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) `else
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always @(posedge clk) `endif
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begin
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if (!res_n)
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begin
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count <= 4'b0;
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full <= 1'b0;
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almost_full <= 1'b0;
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empty <= 1'b1;
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almost_empty <= 1'b1;
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end
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else
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begin
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case ({shift_in_notfull, shift_out_notempty})
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2'b00: ; // nothing to do
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2'b01:
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begin
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if (|count)
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count <= count - 1'b1;
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empty <= !(|count);
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almost_empty <= (count <= 1);
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full <= 1'b0;
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almost_full <= (count > (4'd15 - 1));
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end
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2'b10:
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begin
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if (!empty)
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count <= count + 1'b1;
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empty <= 1'b0;
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almost_empty <= empty;
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full <= (count > 4'd13);
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almost_full <= (count > (4'd13 - 1));
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end
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2'b11: ;
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endcase
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end
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end
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`ifdef CAG_COVERAGE
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full_cov: cover property (@(posedge clk) disable iff(!res_n) (full == 1'b1));
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almost_full_cov: cover property (@(posedge clk) disable iff(!res_n) (almost_full == 1'b1));
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empty_cov: cover property (@(posedge clk) disable iff(!res_n) (empty == 1'b1));
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almost_empty_cov: cover property (@(posedge clk) disable iff(!res_n) (almost_empty == 1'b1));
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`endif // CAG_COVERAGE
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`ifdef CAG_ASSERTIONS
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final
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begin
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if (DISABLE_FULL_ASSERT == 0)
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begin
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full_set_assert: assert (!full);
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almost_full_set_assert: assert (!almost_full);
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end
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if (DISABLE_EMPTY_ASSERT == 0)
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begin
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almost_empty_not_set_assert: assert (almost_empty);
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empty_not_set_assert: assert (empty);
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end
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end
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`endif // CAG_ASSERTIONS
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endmodule
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`default_nettype wire
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