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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: openhmc_ram
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*
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*/
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`default_nettype none
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module openhmc_ram #(
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parameter DATASIZE = 78, // Memory data word width
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parameter ADDRSIZE = 9, // Number of memory address bits
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juko |
parameter PIPELINED = 0
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juko |
) (
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//----------------------------------
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//----SYSTEM INTERFACE
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//----------------------------------
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input wire clk,
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//----------------------------------
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//----Signals
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//----------------------------------
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input wire wen,
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input wire [DATASIZE-1:0] wdata,
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input wire [ADDRSIZE-1:0] waddr,
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input wire ren,
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input wire [ADDRSIZE-1:0] raddr,
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output wire [DATASIZE-1:0] rdata
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);
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//=====================================================================================================
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//-----------------------------------------------------------------------------------------------------
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//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------------------
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//=====================================================================================================
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wire [DATASIZE-1:0] rdata_ram;
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generate
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if (PIPELINED == 0)
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begin
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assign rdata = rdata_ram;
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end
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else
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begin
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reg [DATASIZE-1:0] rdata_dly;
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reg ren_dly;
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assign rdata = rdata_dly;
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always @(posedge clk)
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begin
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ren_dly <= ren;
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if (ren_dly)
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rdata_dly <= rdata_ram;
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end
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end
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endgenerate
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reg [DATASIZE-1:0] MEM [0:(2**ADDRSIZE)-1];
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juko |
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reg [DATASIZE-1:0] data_out;
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assign rdata_ram = data_out;
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always @(posedge clk)
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begin
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if (wen)
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MEM[waddr] <= wdata;
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end
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always @(posedge clk)
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begin
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if (ren)
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data_out <= MEM[raddr];
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end
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endmodule
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`default_nettype wire
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