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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: rx_descrambler
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*
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* Scrambler Logic (HMC Spec version 1.0)
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* This module implements a parallel scrambler based on the
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* polynomial 1+ x^(-14) + x^(-15).
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*
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* Such Scrambler is typically shown as a 15 bit Linear Feedback Shift Register
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* (LFSR) with bits shifting from register 1 on the left to register 15 on the
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* right, with register 14 and 15 combining to shift into register 1.
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* The HMC Serializer outputs data[0] first from parallel tx data[n:0],
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* so if data[n:0] is to be bitwise scrambled with LFSR[n:0], we need the LFSR
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* to shift from n -> 0, the opposite direction from the typical illustration.
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* This implementation shifts data from LFSR[14] on the left to LFSR[0] on the
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* right, with LFSR[1] and [0] combining to shift into LFSR[14]. This way
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* LFSR[14:0] can bitwise scramble data[14:0] and be compatible with serializ-
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* ation that shifts out on the data[0] side.
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* Put otherwise: Polynomial 1+ x^(-14) + x^(-15) is equiv to
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* x^15 + x^1 + x^0
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*
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* This parallelized version calculates the next DWIDTH steps of values for
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* the LFSR. These bits are used to scramble the parallel input, and to
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* choose the next value of lfsr (lfsr_steps[DWIDTH-1]).
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*
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* This is the descrambler. It is self-seeding. When lock is asserted it has
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* successfully found the correct value for the LFSR. It is only implemented
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* for DWIDTH > 14.
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*
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* Since we know that scrambled zeros are being translated, we can calculate
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* what the seed will be in the next timestep. In order to simplify the
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* calculation, we assume that the top bit is a one. That has the happy side-
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* effect of letting us know that the seed didn't get stuck at all zeros.
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*
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* After the scrambler is locked, the input word may need to be aligned. The
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* bit_slip input allows the scrambler to shift one bit with the serializer
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* to keep the scrambler in sync.
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*/
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`default_nettype none
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module rx_descrambler #(
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parameter DWIDTH=16,
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parameter BITSLIP_SHIFT_RIGHT=1
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)
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(
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input wire clk,
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input wire res_n,
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input wire bit_slip,
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input wire can_lock,
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output reg locked,
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input wire [DWIDTH-1:0] data_in,
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output reg [DWIDTH-1:0] data_out
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);
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reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
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wire [14:0] lfsr_slipped; // Temporary lfsr for bitslip
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wire [14:0] lfsr_steps [DWIDTH-1:0]; // LFSR values for serial time steps
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wire [14:0] calculated_seed;
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wire [DWIDTH-1:0] data_out_tmp;
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generate
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if(BITSLIP_SHIFT_RIGHT==1) begin
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assign lfsr_slipped = { (lfsr_steps[DWIDTH-1][1] ^ lfsr_steps[DWIDTH-1][0]) , lfsr_steps[DWIDTH-1][14:1] };
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end else begin
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assign lfsr_slipped = { lfsr_steps[DWIDTH-1][13:0], (lfsr_steps[DWIDTH-1][14] ^ lfsr_steps[DWIDTH-1][0])};
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end
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endgenerate
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`ifdef SIMULATION
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initial begin
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lfsr <= 15'h0;
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end
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`endif
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// SEQUENTIAL PROCESS
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk) begin `endif
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`ifdef RESET_ALL
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if(!res_n) begin
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data_out <= {DWIDTH {1'b0}};
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lfsr <= 15'h0;
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end else
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`endif
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begin
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data_out <= data_out_tmp;
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if (!locked) begin
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lfsr <= calculated_seed;
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end else begin
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if (bit_slip) begin
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lfsr <= lfsr_slipped;
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end else begin
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lfsr <= lfsr_steps[DWIDTH-1];
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end
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end
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end
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if(!res_n) begin
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locked <= 1'b0;
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end else begin
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if (!locked) begin
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if (calculated_seed == lfsr_steps[DWIDTH-1]) begin
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locked <= 1'b1;
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end
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end
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if(!can_lock) begin
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locked <= 1'b0;
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end
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end
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end // serial shift right with left input
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// SCRAMBLE
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genvar j;
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generate
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localparam OFFSET = DWIDTH-15; // It breaks here if DWIDTH < 15
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assign calculated_seed[14] = 1'b1; // Guess the top bit is 1
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// data_in is the past state of the LFSR, so we can figure out
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// the current value using a loop.
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for(j = 0; j < 14; j = j + 1) begin : seed_calc
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assign calculated_seed[j] = data_in[j+OFFSET] ^ data_in[j+OFFSET+1];
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end
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assign data_out_tmp [0] = data_in[0] ^ lfsr[0]; // single bit scrambled
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assign lfsr_steps[0] = { (lfsr[1] ^ lfsr[0]) , lfsr[14:1] }; // lfsr at next bit clock
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for(j = 1; j < DWIDTH; j = j + 1) begin : scrambler_gen
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assign data_out_tmp[j] = data_in[j] ^ lfsr_steps[j-1][0];
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assign lfsr_steps[j] = { (lfsr_steps[j-1][1] ^ lfsr_steps[j-1][0]) , lfsr_steps[j-1][14:1] };
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end
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endgenerate
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endmodule
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`default_nettype wire
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