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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: rx_link
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*
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*/
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`default_nettype none
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module rx_link #(
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parameter LOG_FPW = 2,
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parameter FPW = 4,
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parameter DWIDTH = FPW*128,
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parameter LOG_NUM_LANES = 3,
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parameter NUM_LANES = 2**LOG_NUM_LANES,
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parameter HMC_PTR_SIZE = 8,
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parameter HMC_RF_RWIDTH = 64,
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//Configure functionality
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parameter LOG_MAX_RTC = 8,
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parameter CTRL_LANE_POLARITY = 1,
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parameter CTRL_LANE_REVERSAL = 1,
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parameter BITSLIP_SHIFT_RIGHT= 1
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) (
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//----------------------------------
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//----SYSTEM INTERFACE
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//----------------------------------
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input wire clk,
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input wire res_n,
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//----------------------------------
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//----TO HMC PHY
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//----------------------------------
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input wire [DWIDTH-1:0] phy_scrambled_data_in,
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output reg [NUM_LANES-1:0] init_bit_slip, //bit slip per lane
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//----------------------------------
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//----TO RX HTAX FIFO
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//----------------------------------
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output reg [DWIDTH-1:0] d_out_fifo_data,
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input wire d_out_fifo_full,
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input wire d_out_fifo_a_full,
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output reg d_out_fifo_shift_in,
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output reg [4*FPW-1:0] d_out_fifo_ctrl,
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//----------------------------------
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//----TO TX Block
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//----------------------------------
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output reg tx_link_retry,
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output reg tx_error_abort_mode,
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output reg tx_error_abort_mode_cleared,
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output reg [7:0] tx_hmc_frp,
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output reg [7:0] tx_rrp,
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output reg [7:0] tx_returned_tokens,
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output reg [LOG_FPW:0] tx_hmc_tokens_to_return,
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output reg [LOG_FPW:0] tx_hmc_poisoned_tokens_to_return,
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//----------------------------------
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//----RF
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//----------------------------------
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//Monitoring 1-cycle set to increment
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output reg [HMC_RF_RWIDTH-1:0] rf_cnt_poisoned,
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output reg [HMC_RF_RWIDTH-1:0] rf_cnt_rsp,
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//Status
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output reg [1:0] rf_link_status,
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output reg [2:0] rf_hmc_init_status,
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input wire rf_tx_sends_ts1,
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input wire rf_hmc_sleep,
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//Init Status
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output wire [NUM_LANES-1:0] rf_descrambler_part_aligned,
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output wire [NUM_LANES-1:0] rf_descrambler_aligned,
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output wire rf_all_descramblers_aligned,
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//Control
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input wire [5:0] rf_bit_slip_time,
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input wire rf_hmc_init_cont_set,
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output reg [NUM_LANES-1:0] rf_lane_polarity,
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input wire rf_scrambler_disable,
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output reg rf_lane_reversal_detected,
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output reg [NUM_LANES-1:0] rf_descramblers_locked,
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input wire [4:0] rf_irtry_received_threshold
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);
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`include "hmc_field_functions.h"
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//=====================================================================================================
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//-----------------------------------------------------------------------------------------------------
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//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------------------
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//=====================================================================================================
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//------------------------------------------------------------------------------------Some general things
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//Link state
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localparam HMC_DOWN = 3'b000;
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localparam HMC_NULL = 3'b001;
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localparam HMC_TS1 = 3'b010;
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localparam HMC_UP = 3'b100;
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//Commands
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localparam CMD_IRTRY = 3'b011;
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localparam CMD_FLOW = 3'b000;
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localparam CMD_RSP = 3'b111;
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localparam CMD_RSP_ERROR = 6'b111110;
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//Other helpful defines
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localparam WIDTH_PER_LANE = (DWIDTH/NUM_LANES);
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//16 bits is a ts1, so the init seq number is incremented according to the lane size
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localparam INIT_SEQ_INC_PER_CYCLE = WIDTH_PER_LANE/16;
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//MISC
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integer i_f; //counts to FPW
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integer i_l; //counts to NUM_LANES
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integer i_c; //counts to CYCLES_TO_COMPLETE_FULL_PACKET
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genvar f; //Counts to FPW
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genvar n; //Counts to NUM_LANES
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genvar w; //Counts to WIDTH_PER_LANE
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//------------------------------------------------------------------------------------DESCRAMBLER AND DATA ORDERING
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reg [NUM_LANES-1:0] init_descrambler_part_aligned;
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reg [NUM_LANES-1:0] init_descrambler_aligned;
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assign rf_descrambler_part_aligned = init_descrambler_part_aligned;
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assign rf_descrambler_aligned = init_descrambler_aligned;
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//DATA and REORDERING
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reg [WIDTH_PER_LANE-1:0] init_data_per_lane [NUM_LANES-1:0];
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wire [DWIDTH-1:0] init_d_in;
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wire [128-1:0] init_d_in_flit [FPW-1:0];
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wire [WIDTH_PER_LANE-1:0] descrambled_data_per_lane [NUM_LANES-1:0];
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wire [DWIDTH-1:0] d_in;
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wire [128-1:0] d_in_flit [FPW-1:0];
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//Valid FLIT sources. A FLIT is valid when it is not NULL
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wire [FPW-1:0] valid_flit_src; //bit0 = flit0, ...
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wire [FPW-1:0] init_valid_flit_src; //bit0 = flit0, ...
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generate
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//-- Apply lane reversal if detected
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for(n = 0; n < NUM_LANES; n = n + 1) begin : apply_lane_reversal
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for(w = 0; w < WIDTH_PER_LANE; w = w + 1) begin
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if(CTRL_LANE_REVERSAL==1)begin
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assign d_in[w*NUM_LANES+n] = rf_lane_reversal_detected ? descrambled_data_per_lane[NUM_LANES-1-n][w] : descrambled_data_per_lane[n][w];
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assign init_d_in[w*NUM_LANES+n] = rf_lane_reversal_detected ? init_data_per_lane[NUM_LANES-1-n][w] : init_data_per_lane[n][w];
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end else begin
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assign d_in[w*NUM_LANES+n] = descrambled_data_per_lane[n][w];
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assign init_d_in[w*NUM_LANES+n] = init_data_per_lane[n][w];
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end
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end
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end
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for(f = 0; f < FPW; f = f + 1) begin : reorder_input_data
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//-- Reorder the descrambled data to FLITs
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assign d_in_flit[f] = d_in[128-1+(f*128):f*128];
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assign init_d_in_flit[f] = init_d_in[128-1+(f*128):f*128];
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//-- Generate valid flit positions for the init sequence
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assign valid_flit_src[f] = (|d_in_flit[f] == 1'b0) ? 1'b0 : 1'b1;
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assign init_valid_flit_src[f] = (|init_d_in_flit[f] == 1'b0) ? 1'b0 : 1'b1;
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end
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endgenerate
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//------------------------------------------------------------------------------------INIT
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localparam LINK_DOWN = 2'b00;
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localparam LINK_INIT = 2'b01;
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localparam LINK_UP = 2'b10;
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reg [5:0] init_bit_slip_cnt;
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reg [4:0] init_wait_time;
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wire [NUM_LANES-1:0] init_descrambler_locked; //locked from the descrambler
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wire link_is_up;
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reg [3:0] init_tmp_seq;
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reg init_prbs_seen;
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assign link_is_up = rf_link_status[1];
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assign rf_all_descramblers_aligned = &init_descrambler_aligned;
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//--------------TS1 recognition
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localparam ts1_independent_portion = {4'hF,4'h0};
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localparam ts1_lanex_portion = {4'h5};
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localparam ts1_lane7or15_portion = 4'hc;
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localparam ts1_lane0_portion = 4'h3;
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localparam ts1_per_cycle_and_lane = DWIDTH/NUM_LANES/16;
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wire [NUM_LANES-1:0] init_lane_has_correct_ts1;
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wire [ts1_per_cycle_and_lane-1:0] init_lane_has_correct_ts1_vec [NUM_LANES-1:0];
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genvar t;
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generate
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//Make sure that the lanes have valid ts1 sequences throughout the entire data stream
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for(n=0;n<NUM_LANES;n=n+1) begin : lane_has_correct_ts1_gen
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assign init_lane_has_correct_ts1[n] = &init_lane_has_correct_ts1_vec[n];
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for(t=0;t<ts1_per_cycle_and_lane;t=t+1) begin
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if(n==0 || n==NUM_LANES-1) begin
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assign init_lane_has_correct_ts1_vec[n][t] = (init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lane7or15_portion})
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||
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(init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lane0_portion});
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end else begin
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assign init_lane_has_correct_ts1_vec[n][t] = (init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lanex_portion});
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end
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end
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end
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endgenerate
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//--------------Align the lanes, scan for the ts1 seq
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reg [LOG_NUM_LANES-1:0] init_lane_cnt;
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wire [3:0] init_seq_diff;
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//If one of the descramblers is already partially aligned search for other lanes with their ts1 sequence number close this lane.
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assign init_seq_diff = |init_descrambler_part_aligned ?
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(BITSLIP_SHIFT_RIGHT==1 ? (init_data_per_lane[init_lane_cnt][3:0] - init_tmp_seq)
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: init_tmp_seq - init_data_per_lane[init_lane_cnt][3:0])
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: 0;
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//------------------------------------------------------------------------------------Input Stage: Scan for Packets, Headers, Tails ...
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reg [DWIDTH-1:0] data2crc;
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reg [FPW-1:0] data2crc_hdr;
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reg [FPW-1:0] data2crc_tail;
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reg [FPW-1:0] data2crc_valid;
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wire [(FPW*4)-1:0] data2crc_lng;
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reg [3:0] data2crc_lng_per_flit [FPW-1:0];
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reg [3:0] data2crc_payload_remain;
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reg [FPW-1:0] data2crc_hdr_comb;
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reg [FPW-1:0] data2crc_tail_comb;
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reg [FPW-1:0] data2crc_valid_comb;
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reg [3:0] data2crc_lng_per_flit_comb [FPW-1:0];
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reg [3:0] data2crc_payload_remain_comb;
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generate
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for(f = 0; f < (FPW); f = f + 1) begin
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assign data2crc_lng[(f*4)+4-1:(f*4)] = data2crc_lng_per_flit[f];
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end
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endgenerate
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//------------------------------------------------------------------------------------CRC
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wire [DWIDTH-1:0] crc_d_out_data;
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wire [128-1:0] crc_d_out_flit [FPW-1:0];
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wire [FPW-1:0] crc_d_out_flit_is_hdr;
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wire [FPW-1:0] crc_d_out_flit_is_tail;
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wire [FPW-1:0] crc_d_out_flit_is_valid;
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wire [FPW-1:0] crc_d_out_flit_is_error;
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wire [FPW-1:0] crc_d_out_flit_is_poisoned;
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wire [FPW-1:0] crc_d_out_flit_has_rtc;
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wire [FPW-1:0] crc_d_out_flit_is_flow;
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generate
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for(f=0;f<FPW;f=f+1) begin : reorder_crc_output
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assign crc_d_out_flit[f] = crc_d_out_data[128-1+(f*128):f*128];
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end
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endgenerate
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//------------------------------------------------------------------------------------LNG and DLN stage
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reg [128-1:0] flit_after_lng_check [FPW-1:0];
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reg [FPW-1:0] flit_after_lng_check_is_hdr;
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reg [FPW-1:0] flit_after_lng_check_is_tail;
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reg [FPW-1:0] flit_after_lng_check_is_valid;
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reg [FPW-1:0] flit_after_lng_check_is_error;
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|
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reg [FPW-1:0] flit_after_lng_check_is_poisoned;
|
300 |
|
|
reg [FPW-1:0] flit_after_lng_check_is_flow;
|
301 |
|
|
reg [FPW-1:0] flit_after_lng_check_has_rtc;
|
302 |
|
|
|
303 |
|
|
//------------------------------------------------------------------------------------Start TX retry Stage
|
304 |
|
|
reg [128-1:0] flit_after_retry_stage [FPW-1:0];
|
305 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_hdr;
|
306 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_tail;
|
307 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_valid;
|
308 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_valid_mask_msb;
|
309 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_valid_mask_lsb;
|
310 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_error;
|
311 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_poisoned;
|
312 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_flow;
|
313 |
|
|
reg [FPW-1:0] flit_after_retry_stage_has_rtc;
|
314 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_start_retry;
|
315 |
|
|
reg [FPW-1:0] flit_after_retry_stage_is_start_retry_comb;
|
316 |
|
|
|
317 |
|
|
//------------------------------------------------------------------------------------SeqStage and Seqnum
|
318 |
|
|
reg [128-1:0] flit_after_seq_check [FPW-1:0];
|
319 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_hdr;
|
320 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_tail;
|
321 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_valid;
|
322 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_error;
|
323 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_error_comb;
|
324 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_poisoned;
|
325 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_flow;
|
326 |
|
|
reg [FPW-1:0] flit_after_seq_check_has_rtc;
|
327 |
|
|
reg [FPW-1:0] flit_after_seq_check_is_start_retry;
|
328 |
|
|
|
329 |
|
|
reg [2:0] next_seqnum;
|
330 |
|
|
reg [2:0] next_seqnum_comb; //use param instead
|
331 |
|
|
reg [2:0] first_seq_after_error;
|
332 |
|
|
|
333 |
|
|
//------------------------------------------------------------------------------------Invalidation Stage
|
334 |
|
|
localparam CYCLES_TO_COMPLETE_FULL_PACKET = (FPW == 2) ? 5 :
|
335 |
|
|
(FPW == 4) ? 3 : //Assuming Max Pkt size = 9 FLITs
|
336 |
|
|
(FPW == 6) ? 3 :
|
337 |
|
|
(FPW == 8) ? 2 :
|
338 |
|
|
1;
|
339 |
|
|
|
340 |
|
|
//Regs to retrieve the pkt length, assign the length to correspoding tail. The packet will be invalidated then
|
341 |
|
|
reg [3:0] lng_per_tail [FPW-1:0] ;
|
342 |
|
|
reg [3:0] lng_per_tail_comb [FPW-1:0] ;
|
343 |
|
|
reg [3:0] lng_temp;
|
344 |
|
|
reg [3:0] lng_comb;
|
345 |
|
|
//Signal that an error was detected. Invalid all FLITs after
|
346 |
|
|
reg error_detected;
|
347 |
|
|
|
348 |
|
|
//Assign FLITs to word, necessary for the invalidation stage pipeline
|
349 |
|
|
wire [DWIDTH-1:0] flit_after_seq_check_word;
|
350 |
|
|
generate
|
351 |
|
|
for(f = 0; f < (FPW); f = f + 1) begin : reorder_flits_after_seq_to_word
|
352 |
|
|
assign flit_after_seq_check_word[(f*128)+128-1:(f*128)] = flit_after_seq_check[f];
|
353 |
|
|
end
|
354 |
|
|
endgenerate
|
355 |
|
|
|
356 |
|
|
reg [DWIDTH-1:0] flit_in_invalidation_data [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
357 |
|
|
reg [FPW-1:0] flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
358 |
|
|
reg [FPW-1:0] flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
359 |
|
|
reg [FPW-1:0] flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
360 |
|
|
reg [FPW-1:0] flit_in_invalidation_mask_error;
|
361 |
|
|
reg [FPW-1:0] flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
362 |
|
|
reg [FPW-1:0] flit_in_invalidation0_is_poisoned_comb;
|
363 |
|
|
reg [FPW-1:0] flit_in_invalidation_is_flow [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
364 |
|
|
reg [FPW-1:0] flit_in_invalidation_has_rtc [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
365 |
|
|
reg [FPW-1:0] flit_in_invalidation_is_start_retry[CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
|
366 |
|
|
|
367 |
|
|
//------------------------------------------------------------------------------------Checked FLITs
|
368 |
|
|
wire [128-1:0] checked_flit [FPW-1:0];
|
369 |
|
|
wire [FPW-1:0] checked_flit_is_poisoned;
|
370 |
|
|
wire [FPW-1:0] checked_flit_is_valid;
|
371 |
|
|
wire [FPW-1:0] checked_flit_is_hdr;
|
372 |
|
|
wire [FPW-1:0] checked_flit_is_tail;
|
373 |
|
|
wire [FPW-1:0] checked_flit_has_rtc;
|
374 |
|
|
wire [FPW-1:0] checked_flit_is_flow;
|
375 |
|
|
wire [FPW-1:0] checked_flit_is_start_retry;
|
376 |
|
|
|
377 |
|
|
assign checked_flit_is_hdr = flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
378 |
|
|
assign checked_flit_is_tail = flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
379 |
|
|
assign checked_flit_is_valid = flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1] ;
|
380 |
|
|
assign checked_flit_is_poisoned = flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
381 |
|
|
assign checked_flit_is_flow = flit_in_invalidation_is_flow [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
382 |
|
|
assign checked_flit_has_rtc = flit_in_invalidation_has_rtc [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
383 |
|
|
assign checked_flit_is_start_retry = flit_in_invalidation_is_start_retry[CYCLES_TO_COMPLETE_FULL_PACKET-1];
|
384 |
|
|
|
385 |
|
|
generate
|
386 |
|
|
for(f = 0; f < (FPW); f = f + 1) begin : reorder_invalidation_word_back_to_flits
|
387 |
|
|
assign checked_flit[f] = flit_in_invalidation_data[CYCLES_TO_COMPLETE_FULL_PACKET-1][128-1+(f*128):f*128];
|
388 |
|
|
end
|
389 |
|
|
endgenerate
|
390 |
|
|
|
391 |
|
|
//------------------------------------------------------------------------------------Counter
|
392 |
|
|
reg [LOG_FPW:0] rf_cnt_poisoned_comb;
|
393 |
|
|
reg [LOG_FPW:0] rf_cnt_rsp_comb;
|
394 |
|
|
|
395 |
|
|
//------------------------------------------------------------------------------------Input Buffer
|
396 |
|
|
reg [LOG_FPW:0] tokens_out_of_fifo_sum_comb;
|
397 |
|
|
reg [LOG_FPW:0] tokens_poisoned;
|
398 |
|
|
reg [7:0] rtc_sum_comb; //for 8 FLIT config, maximum 8*31 tokens will be returned per cycle
|
399 |
|
|
|
400 |
|
|
reg [128-1:0] input_buffer_d_in_flit [FPW-1:0];
|
401 |
|
|
reg [FPW-1:0] input_buffer_valid;
|
402 |
|
|
reg [FPW-1:0] input_buffer_is_hdr;
|
403 |
|
|
reg [FPW-1:0] input_buffer_is_tail;
|
404 |
|
|
reg [FPW-1:0] input_buffer_is_error_rsp;
|
405 |
|
|
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_in;
|
406 |
|
|
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_out;
|
407 |
|
|
wire input_buffer_empty;
|
408 |
|
|
reg input_buffer_shift_in;
|
409 |
|
|
wire input_buffer_shift_out;
|
410 |
|
|
assign input_buffer_shift_out = ~(input_buffer_empty || d_out_fifo_a_full);
|
411 |
|
|
|
412 |
|
|
generate
|
413 |
|
|
for(f = 0; f < (FPW); f = f + 1) begin : assign_flits_to_input_buffer_to_a_single_reg
|
414 |
|
|
assign input_buffer_d_in[f*128+128-1:f*128] = input_buffer_d_in_flit[f];
|
415 |
|
|
assign input_buffer_d_in[DWIDTH+f] = input_buffer_valid[f];
|
416 |
|
|
assign input_buffer_d_in[DWIDTH+f+FPW] = input_buffer_is_hdr[f];
|
417 |
|
|
assign input_buffer_d_in[DWIDTH+f+(2*FPW)] = input_buffer_is_tail[f];
|
418 |
|
|
assign input_buffer_d_in[DWIDTH+f+(3*FPW)] = input_buffer_is_error_rsp[f];
|
419 |
|
|
end
|
420 |
|
|
endgenerate
|
421 |
|
|
|
422 |
|
|
//------------------------------------------------------------------------------------LINK RETRY
|
423 |
|
|
reg [5:0] irtry_start_retry_cnt;
|
424 |
|
|
reg [5:0] irtry_clear_error_cnt;
|
425 |
|
|
reg [5:0] irtry_start_retry_cnt_comb;
|
426 |
|
|
reg [5:0] irtry_clear_error_cnt_comb;
|
427 |
|
|
reg irtry_clear_trig;
|
428 |
|
|
reg irtry_clear_trig_comb;
|
429 |
|
|
|
430 |
|
|
//=====================================================================================================
|
431 |
|
|
//-----------------------------------------------------------------------------------------------------
|
432 |
|
|
//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------
|
433 |
|
|
//-----------------------------------------------------------------------------------------------------
|
434 |
|
|
//=====================================================================================================
|
435 |
|
|
|
436 |
|
|
//========================================================================================================================================
|
437 |
|
|
//------------------------------------------------------------------INIT
|
438 |
|
|
//========================================================================================================================================
|
439 |
|
|
always @(posedge clk) begin
|
440 |
|
|
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
|
441 |
|
|
init_data_per_lane[i_l] <= descrambled_data_per_lane[i_l];
|
442 |
|
|
end
|
443 |
|
|
end
|
444 |
|
|
|
445 |
|
|
`ifdef ASYNC_RES
|
446 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
447 |
|
|
always @(posedge clk) begin `endif
|
448 |
|
|
if(!res_n) begin
|
449 |
|
|
//----Misc
|
450 |
|
|
init_descrambler_aligned <= {NUM_LANES{1'b0}};
|
451 |
|
|
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
|
452 |
|
|
init_bit_slip <= {NUM_LANES{1'b0}};
|
453 |
|
|
init_bit_slip_cnt <= 6'h0;
|
454 |
|
|
init_wait_time <= 5'h0;
|
455 |
|
|
init_tmp_seq <= 4'h0;
|
456 |
|
|
init_lane_cnt <= {LOG_NUM_LANES{1'b0}};
|
457 |
|
|
init_prbs_seen <= 1'b0;
|
458 |
|
|
rf_hmc_init_status <= HMC_DOWN;
|
459 |
|
|
rf_link_status <= LINK_DOWN;
|
460 |
|
|
rf_lane_polarity <= {NUM_LANES{1'b0}};
|
461 |
|
|
rf_lane_reversal_detected <= 1'b0;
|
462 |
|
|
rf_descramblers_locked <= {NUM_LANES{1'b0}};
|
463 |
|
|
end
|
464 |
|
|
else begin
|
465 |
|
|
|
466 |
|
|
rf_descramblers_locked <= init_descrambler_locked;
|
467 |
|
|
init_bit_slip <= {NUM_LANES{1'b0}};
|
468 |
|
|
|
469 |
|
|
|
470 |
|
|
if(rf_hmc_sleep || !rf_hmc_init_cont_set) begin
|
471 |
|
|
rf_link_status <= LINK_DOWN;
|
472 |
|
|
end else if(rf_link_status == LINK_DOWN) begin
|
473 |
|
|
//Begin (Re-)Init
|
474 |
|
|
init_descrambler_aligned <= {NUM_LANES{1'b0}};
|
475 |
|
|
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
|
476 |
|
|
init_wait_time <= 5'h1f;
|
477 |
|
|
init_tmp_seq <= 4'h0;
|
478 |
|
|
init_lane_cnt <= {LOG_NUM_LANES{1'b0}};
|
479 |
|
|
init_prbs_seen <= 1'b0;
|
480 |
|
|
rf_hmc_init_status <= HMC_DOWN;
|
481 |
|
|
rf_link_status <= LINK_INIT;
|
482 |
|
|
rf_lane_polarity <= {NUM_LANES{1'b0}};
|
483 |
|
|
rf_lane_reversal_detected <= 1'b0;
|
484 |
|
|
rf_descramblers_locked <= {NUM_LANES{1'b0}};
|
485 |
|
|
end
|
486 |
|
|
|
487 |
|
|
//Detect Lane polarity when HMC is sending first NULLs
|
488 |
|
|
if(&rf_descramblers_locked && rf_link_status == LINK_INIT) begin
|
489 |
|
|
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
|
490 |
|
|
if(init_data_per_lane[i_l] == {WIDTH_PER_LANE{1'b1}})begin
|
491 |
|
|
rf_lane_polarity[i_l] <= 1'b1;
|
492 |
|
|
end
|
493 |
|
|
end
|
494 |
|
|
end
|
495 |
|
|
|
496 |
|
|
if(rf_hmc_init_status == HMC_DOWN) begin
|
497 |
|
|
if(|init_valid_flit_src) begin
|
498 |
|
|
init_prbs_seen <= 1'b1;
|
499 |
|
|
end
|
500 |
|
|
if(!init_valid_flit_src && init_prbs_seen && &rf_descramblers_locked) begin
|
501 |
|
|
rf_hmc_init_status <= HMC_NULL;
|
502 |
|
|
end
|
503 |
|
|
end
|
504 |
|
|
|
505 |
|
|
//When TX block sends ts1, start init process
|
506 |
|
|
if(rf_tx_sends_ts1 && &init_valid_flit_src) begin
|
507 |
|
|
rf_hmc_init_status <= HMC_TS1;
|
508 |
|
|
end
|
509 |
|
|
|
510 |
|
|
if(rf_hmc_init_status==HMC_TS1) begin
|
511 |
|
|
// -------------------------------------------------------------------------TS1 AND DESCRAMBLER SYNCHRONIZATION
|
512 |
|
|
if(!rf_all_descramblers_aligned) begin // repeat this until all descramblers are aligned !!
|
513 |
|
|
|
514 |
|
|
if(|init_wait_time == 1'b0)begin
|
515 |
|
|
|
516 |
|
|
init_tmp_seq <= init_tmp_seq + INIT_SEQ_INC_PER_CYCLE;
|
517 |
|
|
|
518 |
|
|
if(|init_bit_slip_cnt == 1'b0)begin
|
519 |
|
|
|
520 |
|
|
init_lane_cnt <= init_lane_cnt + 1;
|
521 |
|
|
|
522 |
|
|
if(!init_descrambler_part_aligned[init_lane_cnt])begin
|
523 |
|
|
init_bit_slip[init_lane_cnt] <= ~init_lane_has_correct_ts1[init_lane_cnt];
|
524 |
|
|
//if the current lane is more advanced than the current reference lane, set this lane as new reference
|
525 |
|
|
if(init_seq_diff < 2 && init_lane_has_correct_ts1[init_lane_cnt]) begin
|
526 |
|
|
init_tmp_seq <= init_data_per_lane[init_lane_cnt][3:0] + INIT_SEQ_INC_PER_CYCLE;
|
527 |
|
|
end
|
528 |
|
|
end
|
529 |
|
|
|
530 |
|
|
if(&init_descrambler_part_aligned) begin
|
531 |
|
|
if(|init_seq_diff==1'b0 && init_lane_has_correct_ts1[init_lane_cnt])begin
|
532 |
|
|
init_descrambler_aligned[init_lane_cnt] <= 1'b1;
|
533 |
|
|
end else begin
|
534 |
|
|
init_bit_slip[init_lane_cnt] <= 1'b1;
|
535 |
|
|
end
|
536 |
|
|
end else begin
|
537 |
|
|
init_descrambler_part_aligned[init_lane_cnt] <= init_lane_has_correct_ts1[init_lane_cnt];
|
538 |
|
|
end
|
539 |
|
|
|
540 |
|
|
if(init_lane_cnt == NUM_LANES-1)begin
|
541 |
|
|
init_bit_slip_cnt <= rf_bit_slip_time;
|
542 |
|
|
end
|
543 |
|
|
|
544 |
|
|
end else begin
|
545 |
|
|
init_bit_slip_cnt <= init_bit_slip_cnt -1;
|
546 |
|
|
end
|
547 |
|
|
|
548 |
|
|
end else begin
|
549 |
|
|
init_wait_time <= init_wait_time -1;
|
550 |
|
|
end
|
551 |
|
|
// -------------------------------------------------------------------------SECOND NULL SEQUENCE
|
552 |
|
|
end else begin // now that all is synchronized continue with NULL and TRET
|
553 |
|
|
|
554 |
|
|
//lane reversal detected, reverse the input stream lane by lane
|
555 |
|
|
if(init_data_per_lane[0][7:4] == ts1_lane7or15_portion)begin
|
556 |
|
|
rf_lane_reversal_detected <= 1'b1;
|
557 |
|
|
end
|
558 |
|
|
|
559 |
|
|
//when received NULLs again, init done (initial TRETs are treated as normal packets)
|
560 |
|
|
if(|init_valid_flit_src == 1'b0)begin
|
561 |
|
|
rf_link_status <= LINK_UP;
|
562 |
|
|
rf_hmc_init_status <= HMC_UP;
|
563 |
|
|
end
|
564 |
|
|
end
|
565 |
|
|
end
|
566 |
|
|
end
|
567 |
|
|
end
|
568 |
|
|
|
569 |
|
|
//========================================================================================================================================
|
570 |
|
|
//------------------------------------------------------------------Packet Processing
|
571 |
|
|
//========================================================================================================================================
|
572 |
|
|
//==================================================================================
|
573 |
|
|
//---------------------------------Detect HDR,Tail,Valid Flits and provide to CRC logic
|
574 |
|
|
//==================================================================================
|
575 |
|
|
always @(*) begin
|
576 |
|
|
//Use the remaining payload from last cycle
|
577 |
|
|
data2crc_payload_remain_comb = data2crc_payload_remain;
|
578 |
|
|
|
579 |
|
|
data2crc_hdr_comb = {FPW{1'b0}};
|
580 |
|
|
data2crc_tail_comb = {FPW{1'b0}};
|
581 |
|
|
data2crc_valid_comb = {FPW{1'b0}};
|
582 |
|
|
|
583 |
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
584 |
|
|
|
585 |
|
|
data2crc_lng_per_flit_comb[i_f] = {128{1'b0}};
|
586 |
|
|
|
587 |
|
|
if(data2crc_payload_remain_comb ==4'h1) begin
|
588 |
|
|
data2crc_tail_comb[i_f] = 1'b1;
|
589 |
|
|
end
|
590 |
|
|
|
591 |
|
|
if(data2crc_payload_remain_comb) begin
|
592 |
|
|
data2crc_valid_comb[i_f] = 1'b1;
|
593 |
|
|
data2crc_payload_remain_comb = data2crc_payload_remain_comb - 1;
|
594 |
|
|
end else if(valid_flit_src[i_f])begin
|
595 |
|
|
|
596 |
|
|
data2crc_hdr_comb[i_f] = 1'b1;
|
597 |
|
|
data2crc_valid_comb[i_f] = 1'b1;
|
598 |
|
|
|
599 |
|
|
if(lng(d_in_flit[i_f]) < 2 || lng(d_in_flit[i_f]) > 9) begin
|
600 |
|
|
//Treat false lng values as single FLIT packets which will force error abort mode
|
601 |
|
|
data2crc_tail_comb[i_f] = 1'b1;
|
602 |
|
|
data2crc_lng_per_flit_comb[i_f] = 1;
|
603 |
|
|
end else begin
|
604 |
|
|
data2crc_payload_remain_comb = lng(d_in_flit[i_f]) -1;
|
605 |
|
|
data2crc_lng_per_flit_comb[i_f] = lng(d_in_flit[i_f]);
|
606 |
|
|
end
|
607 |
|
|
end
|
608 |
|
|
|
609 |
|
|
end
|
610 |
|
|
end
|
611 |
|
|
|
612 |
|
|
//Register the combinational logic from previous stage
|
613 |
|
|
`ifdef ASYNC_RES
|
614 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
615 |
|
|
always @(posedge clk) begin `endif
|
616 |
|
|
if(!res_n) begin
|
617 |
|
|
|
618 |
|
|
data2crc_hdr <= {FPW{1'b0}};
|
619 |
|
|
data2crc_tail <= {FPW{1'b0}};
|
620 |
|
|
data2crc_valid <= {FPW{1'b0}};
|
621 |
|
|
|
622 |
|
|
data2crc_payload_remain <= {4{1'b0}};
|
623 |
|
|
|
624 |
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
625 |
|
|
data2crc_lng_per_flit[i_f] <= {128{1'b0}};
|
626 |
|
|
end
|
627 |
|
|
|
628 |
|
|
data2crc <= {DWIDTH{1'b0}};
|
629 |
|
|
|
630 |
|
|
end else begin
|
631 |
|
|
if(link_is_up) begin
|
632 |
|
|
data2crc_hdr <= data2crc_hdr_comb;
|
633 |
|
|
data2crc_tail <= data2crc_tail_comb;
|
634 |
|
|
data2crc_valid <= data2crc_valid_comb;
|
635 |
|
|
end
|
636 |
|
|
|
637 |
|
|
data2crc_payload_remain <= data2crc_payload_remain_comb;
|
638 |
|
|
|
639 |
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
|
640 |
|
|
data2crc_lng_per_flit[i_f] <= data2crc_lng_per_flit_comb[i_f];
|
641 |
|
|
end
|
642 |
|
|
|
643 |
|
|
data2crc <= d_in;
|
644 |
|
|
|
645 |
|
|
end
|
646 |
|
|
end
|
647 |
|
|
|
648 |
|
|
//==================================================================================
|
649 |
|
|
//---------------------------------LNG/DLN check
|
650 |
|
|
//==================================================================================
|
651 |
|
|
`ifdef ASYNC_RES
|
652 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
653 |
|
|
always @(posedge clk) begin `endif
|
654 |
|
|
if(!res_n) begin
|
655 |
|
|
|
656 |
|
|
flit_after_lng_check_is_hdr <= {FPW{1'b0}};
|
657 |
|
|
flit_after_lng_check_is_tail <= {FPW{1'b0}};
|
658 |
|
|
flit_after_lng_check_is_valid <= {FPW{1'b0}};
|
659 |
|
|
flit_after_lng_check_is_poisoned <= {FPW{1'b0}};
|
660 |
|
|
flit_after_lng_check_is_flow <= {FPW{1'b0}};
|
661 |
|
|
flit_after_lng_check_has_rtc <= {FPW{1'b0}};
|
662 |
|
|
flit_after_lng_check_is_error <= {FPW{1'b0}};
|
663 |
|
|
|
664 |
|
|
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
|
665 |
|
|
flit_after_lng_check[i_f] <= {128{1'b0}};
|
666 |
|
|
end
|
667 |
|
|
|
668 |
|
|
end else begin
|
669 |
|
|
flit_after_lng_check_is_hdr <= crc_d_out_flit_is_hdr;
|
670 |
|
|
flit_after_lng_check_is_tail <= crc_d_out_flit_is_tail;
|
671 |
|
|
flit_after_lng_check_is_valid <= crc_d_out_flit_is_valid;
|
672 |
|
|
flit_after_lng_check_is_poisoned <= crc_d_out_flit_is_poisoned;
|
673 |
|
|
flit_after_lng_check_is_flow <= crc_d_out_flit_is_flow;
|
674 |
|
|
flit_after_lng_check_has_rtc <= crc_d_out_flit_has_rtc;
|
675 |
|
|
flit_after_lng_check_is_error <= crc_d_out_flit_is_error;
|
676 |
|
|
|
677 |
|
|
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
|
678 |
|
|
flit_after_lng_check[i_f] <= crc_d_out_flit[i_f];
|
679 |
|
|
end
|
680 |
|
|
|
681 |
|
|
//perform lng/dln check
|
682 |
|
|
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
|
683 |
|
|
if(crc_d_out_flit_is_hdr[i_f] && (lng(crc_d_out_flit[i_f]) != dln(crc_d_out_flit[i_f]))) begin
|
684 |
|
|
flit_after_lng_check_is_error[i_f] <= 1'b1;
|
685 |
|
|
end
|
686 |
|
|
end
|
687 |
|
|
end
|
688 |
|
|
end
|
689 |
|
|
|
690 |
|
|
//====================================================================
|
691 |
|
|
//---------------------------------Start Retry Stage
|
692 |
|
|
//====================================================================
|
693 |
|
|
//-- Count all types of IRTRY packets
|
694 |
|
|
always @(*) begin
|
695 |
|
|
|
696 |
|
|
//Set the lower bit mask for the next stage: Mask out all error FLITs
|
697 |
|
|
flit_after_retry_stage_is_valid_mask_lsb = {FPW{1'b1}};
|
698 |
|
|
for(i_f = FPW-1; i_f >=0; i_f = i_f - 1) begin
|
699 |
|
|
if(flit_after_lng_check_is_error[i_f])begin
|
700 |
|
|
//Pass the tail in case it is an crc error so that the corresponding FLITs of the packet can be invalidated
|
701 |
|
|
//but mask out single flit packets!
|
702 |
|
|
flit_after_retry_stage_is_valid_mask_lsb = {FPW{1'b1}} >> (FPW-i_f-(flit_after_lng_check_is_tail[i_f] & !flit_after_lng_check_is_hdr[i_f]));
|
703 |
|
|
end
|
704 |
|
|
end
|
705 |
|
|
|
706 |
|
|
//Next up, count both types of irtry packets and set the mask accordingly for irtry start packets in error abort mode and the
|
707 |
|
|
//final clear abort FLIT that reaches the threshold
|
708 |
|
|
|
709 |
|
|
flit_after_retry_stage_is_start_retry_comb = {FPW{1'b0}};
|
710 |
|
|
|
711 |
|
|
if( (tx_error_abort_mode && !irtry_clear_trig) ||
|
712 |
|
|
|(flit_after_retry_stage_is_error) ||
|
713 |
|
|
|(flit_after_seq_check_is_error)
|
714 |
|
|
)begin
|
715 |
|
|
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b0}};
|
716 |
|
|
end else begin
|
717 |
|
|
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b1}};
|
718 |
|
|
end
|
719 |
|
|
|
720 |
|
|
irtry_clear_trig_comb = 1'b0;
|
721 |
|
|
|
722 |
|
|
irtry_clear_error_cnt_comb = irtry_clear_error_cnt;
|
723 |
|
|
irtry_start_retry_cnt_comb = irtry_start_retry_cnt;
|
724 |
|
|
|
725 |
|
|
|
726 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
727 |
|
|
|
728 |
|
|
if( flit_after_lng_check_is_flow[i_f] &&
|
729 |
|
|
cmd(flit_after_lng_check[i_f]) == {CMD_FLOW,CMD_IRTRY} &&
|
730 |
|
|
!flit_after_lng_check_is_error[i_f]
|
731 |
|
|
) begin
|
732 |
|
|
|
733 |
|
|
if(irtry_start_retry_flag(flit_after_lng_check[i_f])) begin
|
734 |
|
|
//it's a start tx retry pkt
|
735 |
|
|
irtry_start_retry_cnt_comb = irtry_start_retry_cnt_comb + 6'h1;
|
736 |
|
|
irtry_clear_error_cnt_comb = 6'h0;
|
737 |
|
|
end else begin
|
738 |
|
|
//must be clear error pkt
|
739 |
|
|
irtry_clear_error_cnt_comb = irtry_clear_error_cnt_comb + 6'h1;
|
740 |
|
|
irtry_start_retry_cnt_comb = 6'h0;
|
741 |
|
|
end
|
742 |
|
|
|
743 |
|
|
if(irtry_start_retry_cnt_comb == rf_irtry_received_threshold) begin
|
744 |
|
|
//The start retry packet that reaches the trehold is treated as valid and will trigger tx retry
|
745 |
|
|
flit_after_retry_stage_is_valid_mask_msb[i_f] = 1'b1;
|
746 |
|
|
flit_after_retry_stage_is_start_retry_comb[i_f] = 1'b1;
|
747 |
|
|
end
|
748 |
|
|
|
749 |
|
|
//Clear error abort when threshold reached, allow following FLITs to be valid
|
750 |
|
|
if(irtry_clear_error_cnt_comb == rf_irtry_received_threshold) begin
|
751 |
|
|
irtry_clear_trig_comb = 1'b1;
|
752 |
|
|
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b1}} << (i_f);
|
753 |
|
|
end
|
754 |
|
|
|
755 |
|
|
end else begin
|
756 |
|
|
//Reset both counters when received a non-irtry packet
|
757 |
|
|
irtry_start_retry_cnt_comb = 6'h0;
|
758 |
|
|
irtry_clear_error_cnt_comb = 6'h0;
|
759 |
|
|
end
|
760 |
|
|
end
|
761 |
|
|
end
|
762 |
|
|
|
763 |
|
|
//Save the temporary counts to be re-used in the next cycle and register the clear trigger
|
764 |
|
|
`ifdef ASYNC_RES
|
765 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
766 |
|
|
always @(posedge clk) begin `endif
|
767 |
|
|
if(!res_n) begin
|
768 |
|
|
irtry_clear_trig <= 1'b0;
|
769 |
|
|
|
770 |
|
|
irtry_clear_error_cnt <= {6{1'b0}};
|
771 |
|
|
irtry_start_retry_cnt <= {6{1'b0}};
|
772 |
|
|
|
773 |
|
|
end else begin
|
774 |
|
|
irtry_clear_trig <= irtry_clear_trig_comb;
|
775 |
|
|
|
776 |
|
|
irtry_clear_error_cnt <= irtry_clear_error_cnt_comb;
|
777 |
|
|
irtry_start_retry_cnt <= irtry_start_retry_cnt_comb;
|
778 |
|
|
end
|
779 |
|
|
end
|
780 |
|
|
|
781 |
|
|
//Propagate data and apply the valid masks
|
782 |
|
|
`ifdef ASYNC_RES
|
783 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
784 |
|
|
always @(posedge clk) begin `endif
|
785 |
|
|
if(!res_n) begin
|
786 |
|
|
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
|
787 |
|
|
flit_after_retry_stage[i_f] <= {128{1'b0}};
|
788 |
|
|
end
|
789 |
|
|
flit_after_retry_stage_is_hdr <= {FPW{1'b0}};
|
790 |
|
|
flit_after_retry_stage_is_tail <= {FPW{1'b0}};
|
791 |
|
|
flit_after_retry_stage_is_poisoned <= {FPW{1'b0}};
|
792 |
|
|
flit_after_retry_stage_is_flow <= {FPW{1'b0}};
|
793 |
|
|
flit_after_retry_stage_has_rtc <= {FPW{1'b0}};
|
794 |
|
|
flit_after_retry_stage_is_error <= {FPW{1'b0}};
|
795 |
|
|
flit_after_retry_stage_is_valid <= {FPW{1'b0}};
|
796 |
|
|
flit_after_retry_stage_is_start_retry <= 1'b0;
|
797 |
|
|
end else begin
|
798 |
|
|
|
799 |
|
|
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
|
800 |
|
|
flit_after_retry_stage[i_f] <= flit_after_lng_check[i_f];
|
801 |
|
|
end
|
802 |
|
|
flit_after_retry_stage_is_hdr <= flit_after_lng_check_is_hdr;
|
803 |
|
|
flit_after_retry_stage_is_tail <= flit_after_lng_check_is_tail;
|
804 |
|
|
flit_after_retry_stage_is_poisoned <= flit_after_lng_check_is_poisoned &
|
805 |
|
|
flit_after_retry_stage_is_valid_mask_msb &
|
806 |
|
|
flit_after_retry_stage_is_valid_mask_lsb;
|
807 |
|
|
flit_after_retry_stage_is_flow <= flit_after_lng_check_is_flow;
|
808 |
|
|
flit_after_retry_stage_has_rtc <= flit_after_lng_check_has_rtc;
|
809 |
|
|
flit_after_retry_stage_is_error <= flit_after_lng_check_is_error;
|
810 |
|
|
flit_after_retry_stage_is_valid <= flit_after_lng_check_is_valid &
|
811 |
|
|
flit_after_retry_stage_is_valid_mask_msb &
|
812 |
|
|
flit_after_retry_stage_is_valid_mask_lsb;
|
813 |
|
|
flit_after_retry_stage_is_start_retry <= flit_after_retry_stage_is_start_retry_comb;
|
814 |
|
|
end
|
815 |
|
|
end
|
816 |
|
|
|
817 |
|
|
//-------------------------------------------Error abort mode
|
818 |
|
|
`ifdef ASYNC_RES
|
819 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
820 |
|
|
always @(posedge clk) begin `endif
|
821 |
|
|
if(!res_n) begin
|
822 |
|
|
|
823 |
|
|
//TX signaling
|
824 |
|
|
tx_error_abort_mode <= 1'b0;
|
825 |
|
|
tx_error_abort_mode_cleared <= 1'b0;
|
826 |
|
|
|
827 |
|
|
end else begin
|
828 |
|
|
|
829 |
|
|
tx_error_abort_mode_cleared <= 1'b0;
|
830 |
|
|
|
831 |
|
|
if(irtry_clear_trig) begin
|
832 |
|
|
tx_error_abort_mode <= 1'b0;
|
833 |
|
|
tx_error_abort_mode_cleared <= 1'b1;
|
834 |
|
|
end
|
835 |
|
|
|
836 |
|
|
//Set error abort mode again if error detected
|
837 |
|
|
if(|flit_after_lng_check_is_error || flit_after_seq_check_is_error)begin
|
838 |
|
|
tx_error_abort_mode <= 1'b1;
|
839 |
|
|
end
|
840 |
|
|
|
841 |
|
|
end
|
842 |
|
|
end
|
843 |
|
|
|
844 |
|
|
//==================================================================================
|
845 |
|
|
//---------------------------------SEQ check
|
846 |
|
|
//==================================================================================
|
847 |
|
|
//Check the seqnum FLIT by FLIT. Assign the last received seqnum when error abort mode is cleared
|
848 |
|
|
//!Lots of logic levels for 8FLIT config
|
849 |
|
|
always @(*) begin
|
850 |
|
|
|
851 |
|
|
next_seqnum_comb = 3'h0;
|
852 |
|
|
flit_after_seq_check_is_error_comb = {FPW{1'b0}};
|
853 |
|
|
|
854 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
855 |
|
|
if(flit_after_retry_stage_has_rtc[i_f]) begin
|
856 |
|
|
//All packets that have an RTC also have a valid seqnum
|
857 |
|
|
if(seq(flit_after_retry_stage[i_f]) == next_seqnum + next_seqnum_comb) begin
|
858 |
|
|
next_seqnum_comb = next_seqnum_comb + 3'h1;
|
859 |
|
|
end else begin
|
860 |
|
|
flit_after_seq_check_is_error_comb[i_f] = 1'b1;
|
861 |
|
|
end
|
862 |
|
|
end
|
863 |
|
|
end
|
864 |
|
|
end
|
865 |
|
|
|
866 |
|
|
`ifdef ASYNC_RES
|
867 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
868 |
|
|
always @(posedge clk) begin `endif
|
869 |
|
|
if(!res_n) begin
|
870 |
|
|
|
871 |
|
|
//We expect the first packet to have the seqnum 1
|
872 |
|
|
next_seqnum <= 3'h1;
|
873 |
|
|
|
874 |
|
|
flit_after_seq_check_is_hdr <= {FPW{1'b0}};
|
875 |
|
|
flit_after_seq_check_is_tail <= {FPW{1'b0}};
|
876 |
|
|
flit_after_seq_check_is_valid <= {FPW{1'b0}};
|
877 |
|
|
flit_after_seq_check_is_poisoned <= {FPW{1'b0}};
|
878 |
|
|
flit_after_seq_check_is_flow <= {FPW{1'b0}};
|
879 |
|
|
flit_after_seq_check_has_rtc <= {FPW{1'b0}};
|
880 |
|
|
flit_after_seq_check_is_error <= {FPW{1'b0}};
|
881 |
|
|
flit_after_seq_check_is_start_retry <= {FPW{1'b0}};
|
882 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
883 |
|
|
flit_after_seq_check[i_f] <= {128{1'b0}};
|
884 |
|
|
end
|
885 |
|
|
|
886 |
|
|
end else begin
|
887 |
|
|
|
888 |
|
|
//Set the expected sequence number to the first one after error abort mode was cleared
|
889 |
|
|
//otherwise apply the last seqnum + combinatioanl offset
|
890 |
|
|
if(irtry_clear_trig_comb) begin
|
891 |
|
|
next_seqnum <= first_seq_after_error + next_seqnum_comb;
|
892 |
|
|
end else begin
|
893 |
|
|
next_seqnum <= next_seqnum + next_seqnum_comb;
|
894 |
|
|
end
|
895 |
|
|
|
896 |
|
|
//propage data to next stage and include any error bits that were detected during sequence number check
|
897 |
|
|
flit_after_seq_check_is_hdr <= flit_after_retry_stage_is_hdr;
|
898 |
|
|
flit_after_seq_check_is_tail <= flit_after_retry_stage_is_tail;
|
899 |
|
|
flit_after_seq_check_is_valid <= flit_after_retry_stage_is_valid;
|
900 |
|
|
flit_after_seq_check_is_poisoned <= flit_after_retry_stage_is_poisoned;
|
901 |
|
|
flit_after_seq_check_is_flow <= flit_after_retry_stage_is_flow;
|
902 |
|
|
flit_after_seq_check_has_rtc <= flit_after_retry_stage_has_rtc;
|
903 |
|
|
flit_after_seq_check_is_error <= flit_after_retry_stage_is_error |
|
904 |
|
|
flit_after_seq_check_is_error_comb;
|
905 |
|
|
flit_after_seq_check_is_start_retry <= flit_after_retry_stage_is_start_retry;
|
906 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
907 |
|
|
flit_after_seq_check[i_f] <= flit_after_retry_stage[i_f];
|
908 |
|
|
end
|
909 |
|
|
|
910 |
|
|
end
|
911 |
|
|
end
|
912 |
|
|
|
913 |
|
|
//==================================================================================
|
914 |
|
|
//---------------------------------Retrieve the lengths to invalide FLITs
|
915 |
|
|
//==================================================================================
|
916 |
|
|
always @(*) begin
|
917 |
|
|
//Retrieve the length from the header and assign it to the tail. This information will be used in the
|
918 |
|
|
//invalidation stage to mask out FLITs that belong to the faulty packet
|
919 |
|
|
|
920 |
|
|
lng_comb = lng_temp;
|
921 |
|
|
|
922 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
923 |
|
|
|
924 |
|
|
if(flit_after_retry_stage_is_hdr[i_f]) begin
|
925 |
|
|
if( lng(flit_after_retry_stage[i_f]) < 2 ||
|
926 |
|
|
lng(flit_after_retry_stage[i_f]) > 9
|
927 |
|
|
) begin
|
928 |
|
|
lng_comb = 1;
|
929 |
|
|
end else begin
|
930 |
|
|
lng_comb = lng(flit_after_retry_stage[i_f]);
|
931 |
|
|
end
|
932 |
|
|
end
|
933 |
|
|
|
934 |
|
|
if(flit_after_retry_stage_is_tail[i_f]) begin
|
935 |
|
|
lng_per_tail_comb[i_f] = lng_comb;
|
936 |
|
|
end else begin
|
937 |
|
|
lng_per_tail_comb[i_f] = {4{1'b0}};
|
938 |
|
|
end
|
939 |
|
|
|
940 |
|
|
end
|
941 |
|
|
end
|
942 |
|
|
|
943 |
|
|
//Register combinational values
|
944 |
|
|
`ifdef ASYNC_RES
|
945 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
946 |
|
|
always @(posedge clk) begin `endif
|
947 |
|
|
if(!res_n) begin
|
948 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
949 |
|
|
lng_per_tail[i_f] <= 0;
|
950 |
|
|
end
|
951 |
|
|
lng_temp <= {4{1'b0}};
|
952 |
|
|
end else begin
|
953 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
954 |
|
|
lng_per_tail[i_f] <= lng_per_tail_comb[i_f];
|
955 |
|
|
end
|
956 |
|
|
lng_temp <= lng_comb;
|
957 |
|
|
end
|
958 |
|
|
end
|
959 |
|
|
|
960 |
|
|
//==================================================================================
|
961 |
|
|
//---------------------------------FLIT Invalidation Stage
|
962 |
|
|
//==================================================================================
|
963 |
|
|
//Constant propagation for some parts of the invalidation stage
|
964 |
|
|
`ifdef ASYNC_RES
|
965 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
966 |
|
|
always @(posedge clk) begin `endif
|
967 |
|
|
if(!res_n) begin
|
968 |
|
|
|
969 |
|
|
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET); i_c=i_c+1) begin
|
970 |
|
|
flit_in_invalidation_data[i_c] <= {DWIDTH{1'b0}};
|
971 |
|
|
flit_in_invalidation_is_hdr[i_c] <= {FPW{1'b0}};
|
972 |
|
|
flit_in_invalidation_is_tail[i_c] <= {FPW{1'b0}};
|
973 |
|
|
flit_in_invalidation_is_flow[i_c] <= {FPW{1'b0}};
|
974 |
|
|
flit_in_invalidation_has_rtc[i_c] <= {FPW{1'b0}};
|
975 |
|
|
flit_in_invalidation_is_start_retry[i_c] <= {FPW{1'b0}};
|
976 |
|
|
end
|
977 |
|
|
end else begin
|
978 |
|
|
flit_in_invalidation_data[0] <= flit_after_seq_check_word;
|
979 |
|
|
flit_in_invalidation_is_hdr[0] <= flit_after_seq_check_is_hdr;
|
980 |
|
|
flit_in_invalidation_is_tail[0] <= flit_after_seq_check_is_tail;
|
981 |
|
|
flit_in_invalidation_is_flow[0] <= flit_after_seq_check_is_flow;
|
982 |
|
|
flit_in_invalidation_has_rtc[0] <= flit_after_seq_check_has_rtc;
|
983 |
|
|
flit_in_invalidation_is_start_retry[0] <= flit_after_seq_check_is_start_retry;
|
984 |
|
|
|
985 |
|
|
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c=i_c+1) begin
|
986 |
|
|
flit_in_invalidation_data[i_c+1] <= flit_in_invalidation_data[i_c];
|
987 |
|
|
flit_in_invalidation_is_hdr[i_c+1] <= flit_in_invalidation_is_hdr[i_c];
|
988 |
|
|
flit_in_invalidation_is_tail[i_c+1] <= flit_in_invalidation_is_tail[i_c];
|
989 |
|
|
flit_in_invalidation_is_flow[i_c+1] <= flit_in_invalidation_is_flow[i_c];
|
990 |
|
|
flit_in_invalidation_has_rtc[i_c+1] <= flit_in_invalidation_has_rtc[i_c];
|
991 |
|
|
flit_in_invalidation_is_start_retry[i_c+1] <= flit_in_invalidation_is_start_retry[i_c];
|
992 |
|
|
end
|
993 |
|
|
end
|
994 |
|
|
end
|
995 |
|
|
|
996 |
|
|
//Mark all poisoned FLITs
|
997 |
|
|
always @(*) begin
|
998 |
|
|
flit_in_invalidation0_is_poisoned_comb = {FPW{1'b0}};
|
999 |
|
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
1000 |
|
|
if(flit_after_seq_check_is_poisoned[i_f])begin
|
1001 |
|
|
flit_in_invalidation0_is_poisoned_comb =flit_in_invalidation0_is_poisoned_comb |
|
1002 |
|
|
(({FPW{1'b1}} >> (FPW-i_f-1)) & ~({FPW{1'b1}} >> lng_per_tail[i_f]+(FPW-i_f-1)));
|
1003 |
|
|
end
|
1004 |
|
|
end
|
1005 |
|
|
end
|
1006 |
|
|
`ifdef ASYNC_RES
|
1007 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1008 |
|
|
always @(posedge clk) begin `endif
|
1009 |
|
|
if(!res_n) begin
|
1010 |
|
|
|
1011 |
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
|
1012 |
|
|
flit_in_invalidation_is_poisoned[i_c] <= 0;
|
1013 |
|
|
end
|
1014 |
|
|
|
1015 |
|
|
end else begin
|
1016 |
|
|
flit_in_invalidation_is_poisoned[0] <= flit_in_invalidation0_is_poisoned_comb;
|
1017 |
|
|
|
1018 |
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
1019 |
|
|
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c];
|
1020 |
|
|
end
|
1021 |
|
|
|
1022 |
|
|
//If there is a poisoned packet mark all FLITs as such
|
1023 |
|
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
1024 |
|
|
if(flit_after_seq_check_is_poisoned[i_f]) begin
|
1025 |
|
|
|
1026 |
|
|
// flit_in_invalidation_is_poisoned[0] <= ({FPW{1'b1}} >> (FPW-i_f-1)) & ~({FPW{1'b1}} >> lng_per_tail[i_f]+(FPW-i_f-1));
|
1027 |
|
|
|
1028 |
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
1029 |
|
|
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
|
1030 |
|
|
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c] | ~({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
|
1031 |
|
|
end
|
1032 |
|
|
end
|
1033 |
|
|
|
1034 |
|
|
end
|
1035 |
|
|
end
|
1036 |
|
|
end
|
1037 |
|
|
end
|
1038 |
|
|
|
1039 |
|
|
|
1040 |
|
|
//Invalidate FLITs that belong to errorenous packets
|
1041 |
|
|
`ifdef ASYNC_RES
|
1042 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1043 |
|
|
always @(posedge clk) begin `endif
|
1044 |
|
|
if(!res_n) begin
|
1045 |
|
|
|
1046 |
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
|
1047 |
|
|
flit_in_invalidation_is_valid[i_c] <= 0;
|
1048 |
|
|
end
|
1049 |
|
|
error_detected <= 0;
|
1050 |
|
|
flit_in_invalidation_mask_error <= {FPW{1'b1}};
|
1051 |
|
|
|
1052 |
|
|
end else begin
|
1053 |
|
|
|
1054 |
|
|
//Reset the masks for invalidation stages
|
1055 |
|
|
flit_in_invalidation_mask_error <= {FPW{1'b1}};
|
1056 |
|
|
|
1057 |
|
|
if(irtry_clear_trig) begin
|
1058 |
|
|
error_detected <= 0;
|
1059 |
|
|
end
|
1060 |
|
|
|
1061 |
|
|
//Propate invalidation stages but apply error and poisoned masks to the second stage
|
1062 |
|
|
for(i_c = 1; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
1063 |
|
|
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c];
|
1064 |
|
|
end
|
1065 |
|
|
flit_in_invalidation_is_valid[1] <= flit_in_invalidation_is_valid[0] & flit_in_invalidation_mask_error;
|
1066 |
|
|
|
1067 |
|
|
if(error_detected) begin
|
1068 |
|
|
//There is no valid FLIT when an error was detected
|
1069 |
|
|
flit_in_invalidation_is_valid[0] <= {FPW{1'b0}};
|
1070 |
|
|
end else begin
|
1071 |
|
|
//First apply valids from previous stage
|
1072 |
|
|
flit_in_invalidation_is_valid[0] <= flit_after_seq_check_is_valid;
|
1073 |
|
|
|
1074 |
|
|
//At least one FLIT contained an error in its tail. Leave all FLITs before the error untouched
|
1075 |
|
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
1076 |
|
|
if(flit_after_seq_check_is_error[i_f] && flit_after_seq_check_is_tail[i_f]) begin
|
1077 |
|
|
error_detected <= 1'b1;
|
1078 |
|
|
flit_in_invalidation_mask_error <= {FPW{1'b1}} >> (FPW-i_f-1+lng_per_tail[i_f]);
|
1079 |
|
|
end
|
1080 |
|
|
end
|
1081 |
|
|
|
1082 |
|
|
//Now use the length of the packet to invalidate FLITs that may reside in the next stages already
|
1083 |
|
|
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
|
1084 |
|
|
if(flit_after_seq_check_is_error[i_f] && flit_after_seq_check_is_tail[i_f]) begin
|
1085 |
|
|
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
|
1086 |
|
|
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
|
1087 |
|
|
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c] &
|
1088 |
|
|
({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
|
1089 |
|
|
end
|
1090 |
|
|
end
|
1091 |
|
|
end
|
1092 |
|
|
end
|
1093 |
|
|
end
|
1094 |
|
|
|
1095 |
|
|
end
|
1096 |
|
|
end
|
1097 |
|
|
|
1098 |
|
|
//====================================================================
|
1099 |
|
|
//---------------------------------FRP/RRP/RTC
|
1100 |
|
|
//====================================================================
|
1101 |
|
|
//Count Tokens that were returned
|
1102 |
|
|
always @(*) begin
|
1103 |
|
|
rtc_sum_comb = {8{1'b0}};
|
1104 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
1105 |
|
|
if(checked_flit_has_rtc[i_f])begin
|
1106 |
|
|
rtc_sum_comb = rtc_sum_comb + rtc(checked_flit[i_f]);
|
1107 |
|
|
end
|
1108 |
|
|
end
|
1109 |
|
|
end
|
1110 |
|
|
|
1111 |
|
|
//Extract FRP/RRP + last seq (which is necessary to check packets after error_abort_mode is cleared)
|
1112 |
|
|
`ifdef ASYNC_RES
|
1113 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1114 |
|
|
always @(posedge clk) begin `endif
|
1115 |
|
|
if(!res_n) begin
|
1116 |
|
|
|
1117 |
|
|
tx_hmc_frp <= {8{1'b0}};
|
1118 |
|
|
tx_rrp <= {8{1'b0}};
|
1119 |
|
|
tx_returned_tokens <= {8{1'b0}};
|
1120 |
|
|
first_seq_after_error <= 3'h1;
|
1121 |
|
|
|
1122 |
|
|
tx_link_retry <= 1'b0;
|
1123 |
|
|
|
1124 |
|
|
end else begin
|
1125 |
|
|
//Return tokens
|
1126 |
|
|
tx_returned_tokens <= rtc_sum_comb;
|
1127 |
|
|
|
1128 |
|
|
//Process FLITs and extract frp/seq/rrp if applicable
|
1129 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
1130 |
|
|
|
1131 |
|
|
if(checked_flit_is_tail[i_f] || checked_flit_is_start_retry[i_f]) begin
|
1132 |
|
|
tx_rrp <= rrp(checked_flit[i_f]);
|
1133 |
|
|
|
1134 |
|
|
if(checked_flit_has_rtc[i_f])begin
|
1135 |
|
|
tx_hmc_frp <= frp(checked_flit[i_f]);
|
1136 |
|
|
first_seq_after_error <= seq(checked_flit[i_f]) + 3'h1;
|
1137 |
|
|
end
|
1138 |
|
|
end
|
1139 |
|
|
end
|
1140 |
|
|
|
1141 |
|
|
//-------------------------------------------TX retry
|
1142 |
|
|
tx_link_retry <= 1'b0;
|
1143 |
|
|
|
1144 |
|
|
if(|checked_flit_is_start_retry)begin
|
1145 |
|
|
tx_link_retry <= 1'b1;
|
1146 |
|
|
end
|
1147 |
|
|
|
1148 |
|
|
end
|
1149 |
|
|
end
|
1150 |
|
|
|
1151 |
|
|
//==================================================================================
|
1152 |
|
|
//---------------------------------Fill the input buffer with all response packets
|
1153 |
|
|
//==================================================================================
|
1154 |
|
|
`ifdef ASYNC_RES
|
1155 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1156 |
|
|
always @(posedge clk) begin `endif
|
1157 |
|
|
if(!res_n) begin
|
1158 |
|
|
|
1159 |
|
|
input_buffer_shift_in <= 1'b0;
|
1160 |
|
|
input_buffer_valid <= {FPW{1'b0}};
|
1161 |
|
|
input_buffer_is_hdr <= {FPW{1'b0}};
|
1162 |
|
|
input_buffer_is_tail <= {FPW{1'b0}};
|
1163 |
|
|
input_buffer_is_error_rsp <= {FPW{1'b0}};
|
1164 |
|
|
|
1165 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
1166 |
|
|
input_buffer_d_in_flit[i_f] <= {128{1'b0}};
|
1167 |
|
|
end
|
1168 |
|
|
|
1169 |
|
|
end else begin
|
1170 |
|
|
|
1171 |
|
|
input_buffer_shift_in <= 1'b0;
|
1172 |
|
|
input_buffer_is_error_rsp <= {FPW{1'b0}};
|
1173 |
|
|
|
1174 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
1175 |
|
|
input_buffer_d_in_flit[i_f] <= {128{1'b0}};
|
1176 |
|
|
|
1177 |
|
|
//Flow and poisoned packets are not forwarded
|
1178 |
|
|
if(checked_flit_is_valid[i_f]) begin
|
1179 |
|
|
if(!checked_flit_is_flow[i_f] && !checked_flit_is_poisoned[i_f])begin
|
1180 |
|
|
input_buffer_d_in_flit[i_f] <= checked_flit[i_f];
|
1181 |
|
|
end
|
1182 |
|
|
if(checked_flit_is_hdr[i_f] && (cmd(checked_flit[i_f])==CMD_RSP_ERROR)) begin
|
1183 |
|
|
input_buffer_is_error_rsp[i_f] <= 1'b1;
|
1184 |
|
|
end
|
1185 |
|
|
end
|
1186 |
|
|
end
|
1187 |
|
|
|
1188 |
|
|
//Mask out any flow or poisoned packets
|
1189 |
|
|
input_buffer_valid <= checked_flit_is_valid &
|
1190 |
|
|
~checked_flit_is_flow &
|
1191 |
|
|
~checked_flit_is_poisoned;
|
1192 |
|
|
input_buffer_is_hdr <= checked_flit_is_hdr &
|
1193 |
|
|
~checked_flit_is_flow &
|
1194 |
|
|
~checked_flit_is_poisoned;
|
1195 |
|
|
input_buffer_is_tail <= checked_flit_is_tail &
|
1196 |
|
|
~checked_flit_is_flow &
|
1197 |
|
|
~checked_flit_is_poisoned;
|
1198 |
|
|
|
1199 |
|
|
//If there is still a valid packet remaining after applying the mask
|
1200 |
|
|
if(|(checked_flit_is_valid & ~checked_flit_is_flow & ~checked_flit_is_poisoned))begin
|
1201 |
|
|
input_buffer_shift_in <= 1'b1;
|
1202 |
|
|
end
|
1203 |
|
|
|
1204 |
|
|
end
|
1205 |
|
|
end
|
1206 |
|
|
|
1207 |
|
|
always @(*) begin
|
1208 |
|
|
tokens_poisoned = {LOG_FPW+1{1'b0}};
|
1209 |
|
|
|
1210 |
|
|
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
|
1211 |
|
|
tokens_poisoned = tokens_poisoned + checked_flit_is_poisoned[i_f];
|
1212 |
|
|
end
|
1213 |
|
|
end
|
1214 |
|
|
|
1215 |
|
|
`ifdef ASYNC_RES
|
1216 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1217 |
|
|
always @(posedge clk) begin `endif
|
1218 |
|
|
if(!res_n) begin
|
1219 |
|
|
tx_hmc_poisoned_tokens_to_return <= {LOG_FPW+1{1'b0}};
|
1220 |
|
|
end else begin
|
1221 |
|
|
tx_hmc_poisoned_tokens_to_return <= tokens_poisoned;
|
1222 |
|
|
end
|
1223 |
|
|
end
|
1224 |
|
|
|
1225 |
|
|
//==================================================================================
|
1226 |
|
|
//---------------------------------Count responses and poisoned packets
|
1227 |
|
|
//==================================================================================
|
1228 |
|
|
always @(*) begin
|
1229 |
|
|
rf_cnt_poisoned_comb = {LOG_FPW+1{1'b0}};
|
1230 |
|
|
rf_cnt_rsp_comb = {LOG_FPW+1{1'b0}};
|
1231 |
|
|
|
1232 |
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
1233 |
|
|
if(checked_flit_is_poisoned[i_f] && checked_flit_is_hdr[i_f])begin
|
1234 |
|
|
rf_cnt_poisoned_comb = rf_cnt_poisoned_comb + {{LOG_FPW{1'b0}},1'b1};
|
1235 |
|
|
end
|
1236 |
|
|
if(input_buffer_is_tail[i_f] && !input_buffer_is_error_rsp[i_f])begin
|
1237 |
|
|
//if its a tail but not error response
|
1238 |
|
|
rf_cnt_rsp_comb = rf_cnt_rsp_comb + {{LOG_FPW{1'b0}},1'b1};
|
1239 |
|
|
end
|
1240 |
|
|
end
|
1241 |
|
|
end
|
1242 |
|
|
|
1243 |
|
|
`ifdef ASYNC_RES
|
1244 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1245 |
|
|
always @(posedge clk) begin `endif
|
1246 |
|
|
if(!res_n) begin
|
1247 |
|
|
rf_cnt_poisoned <= {HMC_RF_RWIDTH{1'b0}};
|
1248 |
|
|
rf_cnt_rsp <= {HMC_RF_RWIDTH{1'b0}};
|
1249 |
|
|
end else begin
|
1250 |
|
|
rf_cnt_poisoned <= rf_cnt_poisoned + {{HMC_RF_RWIDTH-LOG_FPW-1{1'b0}},rf_cnt_poisoned_comb};
|
1251 |
|
|
rf_cnt_rsp <= rf_cnt_rsp + {{HMC_RF_RWIDTH-LOG_FPW-1{1'b0}},rf_cnt_rsp_comb};
|
1252 |
|
|
end
|
1253 |
|
|
end
|
1254 |
|
|
|
1255 |
|
|
//==================================================================================
|
1256 |
|
|
//---------------------------------Shift response packets into the output fifo, return a token for each processed FLIT
|
1257 |
|
|
//==================================================================================
|
1258 |
|
|
always @(*) begin
|
1259 |
|
|
tokens_out_of_fifo_sum_comb = {LOG_FPW+1{1'b0}};
|
1260 |
|
|
|
1261 |
|
|
if(input_buffer_shift_out)begin
|
1262 |
|
|
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
|
1263 |
|
|
tokens_out_of_fifo_sum_comb = tokens_out_of_fifo_sum_comb +
|
1264 |
|
|
(input_buffer_d_out[DWIDTH+i_f] &&
|
1265 |
|
|
!input_buffer_d_out[DWIDTH+i_f+(3*FPW)]); //increment if there's a valid FLIT, but not an error response
|
1266 |
|
|
end
|
1267 |
|
|
end
|
1268 |
|
|
end
|
1269 |
|
|
|
1270 |
|
|
`ifdef ASYNC_RES
|
1271 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1272 |
|
|
always @(posedge clk) begin `endif
|
1273 |
|
|
if(!res_n) begin
|
1274 |
|
|
tx_hmc_tokens_to_return <= {LOG_FPW+1{1'b0}};
|
1275 |
|
|
end else begin
|
1276 |
|
|
tx_hmc_tokens_to_return <= tokens_out_of_fifo_sum_comb;
|
1277 |
|
|
end
|
1278 |
|
|
end
|
1279 |
|
|
|
1280 |
|
|
`ifdef ASYNC_RES
|
1281 |
|
|
always @(posedge clk or negedge res_n) begin `else
|
1282 |
|
|
always @(posedge clk) begin `endif
|
1283 |
|
|
if(!res_n) begin
|
1284 |
|
|
//----FIFO
|
1285 |
|
|
d_out_fifo_shift_in <= 1'b0;
|
1286 |
|
|
d_out_fifo_ctrl <= {4*FPW{1'b0}};
|
1287 |
|
|
d_out_fifo_data <= {DWIDTH{1'b0}};
|
1288 |
|
|
|
1289 |
|
|
end else begin
|
1290 |
|
|
d_out_fifo_shift_in <= 1'b0;
|
1291 |
|
|
d_out_fifo_ctrl <= {4*FPW{1'b0}};
|
1292 |
|
|
|
1293 |
|
|
|
1294 |
|
|
if(input_buffer_shift_out)begin
|
1295 |
|
|
d_out_fifo_data <= input_buffer_d_out[DWIDTH-1:0];
|
1296 |
|
|
d_out_fifo_shift_in <= 1'b1;
|
1297 |
|
|
d_out_fifo_ctrl <= input_buffer_d_out[DWIDTH+(4*FPW)-1:DWIDTH];
|
1298 |
|
|
end
|
1299 |
|
|
end
|
1300 |
|
|
end
|
1301 |
|
|
|
1302 |
|
|
|
1303 |
|
|
|
1304 |
|
|
//=====================================================================================================
|
1305 |
|
|
//-----------------------------------------------------------------------------------------------------
|
1306 |
|
|
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
|
1307 |
|
|
//-----------------------------------------------------------------------------------------------------
|
1308 |
|
|
//=====================================================================================================
|
1309 |
|
|
|
1310 |
|
|
wire res_n_lanes;
|
1311 |
|
|
assign res_n_lanes = ((rf_link_status == LINK_DOWN) || !rf_hmc_init_cont_set) ? 1'b0 : 1'b1;
|
1312 |
|
|
|
1313 |
|
|
//Lane Init
|
1314 |
|
|
genvar i;
|
1315 |
|
|
generate
|
1316 |
|
|
for(i=0;i<NUM_LANES;i=i+1)begin : lane_gen
|
1317 |
|
|
rx_lane_logic #(
|
1318 |
|
|
.DWIDTH(DWIDTH),
|
1319 |
|
|
.NUM_LANES(NUM_LANES),
|
1320 |
|
|
.CTRL_LANE_POLARITY(CTRL_LANE_POLARITY),
|
1321 |
|
|
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
|
1322 |
|
|
) rx_lane_I (
|
1323 |
|
|
.clk(clk),
|
1324 |
|
|
.res_n(res_n_lanes),
|
1325 |
|
|
.bit_slip(init_bit_slip[i]),
|
1326 |
|
|
.descrambler_locked(init_descrambler_locked[i]),
|
1327 |
|
|
.descrambler_disable(rf_scrambler_disable),
|
1328 |
|
|
.lane_polarity(rf_lane_polarity[i]),
|
1329 |
|
|
.scrambled_data_in(phy_scrambled_data_in[i*WIDTH_PER_LANE+WIDTH_PER_LANE-1:i*WIDTH_PER_LANE]),
|
1330 |
|
|
.descrambled_data_out(descrambled_data_per_lane[i])
|
1331 |
|
|
);
|
1332 |
|
|
end
|
1333 |
|
|
endgenerate
|
1334 |
|
|
|
1335 |
|
|
//HMC CRC Logic
|
1336 |
|
|
rx_crc_compare #(
|
1337 |
|
|
.DWIDTH(DWIDTH),
|
1338 |
|
|
.FPW(FPW),
|
1339 |
|
|
.LOG_FPW(LOG_FPW)
|
1340 |
|
|
)
|
1341 |
|
|
rx_crc_compare
|
1342 |
|
|
(
|
1343 |
|
|
.clk(clk),
|
1344 |
|
|
.res_n(res_n),
|
1345 |
|
|
//input
|
1346 |
|
|
.d_in_data(data2crc),
|
1347 |
|
|
.d_in_hdr(data2crc_hdr),
|
1348 |
|
|
.d_in_tail(data2crc_tail),
|
1349 |
|
|
.d_in_valid(data2crc_valid),
|
1350 |
|
|
.d_in_lng(data2crc_lng),
|
1351 |
|
|
//output
|
1352 |
|
|
.d_out_data(crc_d_out_data),
|
1353 |
|
|
.d_out_hdr(crc_d_out_flit_is_hdr),
|
1354 |
|
|
.d_out_tail(crc_d_out_flit_is_tail),
|
1355 |
|
|
.d_out_valid(crc_d_out_flit_is_valid),
|
1356 |
|
|
.d_out_error(crc_d_out_flit_is_error),
|
1357 |
|
|
.d_out_poisoned(crc_d_out_flit_is_poisoned),
|
1358 |
|
|
.d_out_rtc(crc_d_out_flit_has_rtc),
|
1359 |
|
|
.d_out_flow(crc_d_out_flit_is_flow)
|
1360 |
|
|
);
|
1361 |
|
|
|
1362 |
|
|
//Buffer Fifo - Depth = Max Tokens
|
1363 |
|
|
openhmc_sync_fifo #(
|
1364 |
|
|
.DATASIZE(DWIDTH+(4*FPW)), //+4*FPW for header/tail/valid/error response information -> AXI-4 TUSER signal
|
1365 |
|
|
.ADDRSIZE(LOG_MAX_RTC)
|
1366 |
|
|
) input_buffer_I(
|
1367 |
|
|
.clk(clk),
|
1368 |
|
|
.res_n(res_n),
|
1369 |
|
|
.d_in(input_buffer_d_in),
|
1370 |
|
|
.shift_in(input_buffer_shift_in),
|
1371 |
|
|
.d_out(input_buffer_d_out),
|
1372 |
|
|
.shift_out(input_buffer_shift_out),
|
1373 |
|
|
.next_stage_full(1'b1), // Dont touch!
|
1374 |
|
|
.empty(input_buffer_empty)
|
1375 |
|
|
);
|
1376 |
|
|
|
1377 |
|
|
endmodule
|
1378 |
|
|
`default_nettype wire
|