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/*

 *                              .--------------. .----------------. .------------.

 *                             | .------------. | .--------------. | .----------. |

 *                             | | ____  ____ | | | ____    ____ | | |   ______ | |

 *                             | ||_   ||   _|| | ||_   \  /   _|| | | .' ___  || |

 *       ___  _ __   ___ _ __  | |  | |__| |  | | |  |   \/   |  | | |/ .'   \_|| |

 *      / _ \| '_ \ / _ \ '_ \ | |  |  __  |  | | |  | |\  /| |  | | || |       | |

 *       (_) | |_) |  __/ | | || | _| |  | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |

 *      \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |

 *           | |               | |            | | |              | | |          | |

 *           |_|               | '------------' | '--------------' | '----------' |

 *                              '--------------' '----------------' '------------'

 *

 *  openHMC - An Open Source Hybrid Memory Cube Controller

 *  (C) Copyright 2014 Computer Architecture Group - University of Heidelberg

 *  www.ziti.uni-heidelberg.de

 *  B6, 26

 *  68159 Mannheim

 *  Germany

 *

 *  Contact: openhmc@ziti.uni-heidelberg.de

 *  http://ra.ziti.uni-heidelberg.de/openhmc

 *

 *   This source file is free software: you can redistribute it and/or modify

 *   it under the terms of the GNU Lesser General Public License as published by

 *   the Free Software Foundation, either version 3 of the License, or

 *   (at your option) any later version.

 *

 *   This source file is distributed in the hope that it will be useful,

 *   but WITHOUT ANY WARRANTY; without even the implied warranty of

 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *   GNU Lesser General Public License for more details.

 *

 *   You should have received a copy of the GNU Lesser General Public License

 *   along with this source file.  If not, see <http://www.gnu.org/licenses/>.

 *

 *

 *  Module name: rx_link

 *

 */

`default_nettype none

module rx_link #(

    parameter LOG_FPW              = 2,

    parameter FPW                  = 4,

    parameter DWIDTH               = FPW*128,

    parameter LOG_NUM_LANES        = 3,

    parameter NUM_LANES            = 2**LOG_NUM_LANES,

    parameter HMC_PTR_SIZE         = 8,

    parameter RF_COUNTER_SIZE      = 64,

    //Set Token Related

    parameter LOG_MAX_RX_TOKENS    = 8,

    parameter MAX_RTC_RET_LOG      = 8,

    //Control

    parameter XIL_CNT_PIPELINED    = 0,

    parameter CTRL_LANE_POLARITY   = 1,

    parameter RX_RELAX_INIT_TIMING = 1,

    parameter RX_BIT_SLIP_CNT_LOG  = 5,

    parameter DETECT_LANE_POLARITY = 1,

    parameter CTRL_LANE_REVERSAL   = 1,

    parameter BITSLIP_SHIFT_RIGHT  = 1,

    parameter OPEN_RSP_MODE        = 0

) (

    //----------------------------------

    //----SYSTEM INTERFACE

    //----------------------------------

    input   wire                        clk,

    input   wire                        res_n,

    input   wire                        run_rx,

    //----------------------------------

    //----TO HMC PHY

    //----------------------------------

    input   wire  [DWIDTH-1:0]          phy_scrambled_data_in,

    output  reg   [NUM_LANES-1:0]       phy_bit_slip,

    //----------------------------------

    //----TO RX HTAX FIFO

    //----------------------------------

    output  wire   [DWIDTH-1:0]         d_out_fifo_data,

    input   wire                        d_out_fifo_a_full,

    output  wire                        d_out_fifo_shift_in,

    output  wire   [4*FPW-1:0]          d_out_fifo_ctrl,

    //----------------------------------

    //----TO TX Block

    //----------------------------------

    output  reg                         tx_link_retry,

    output  reg                         tx_error_abort_mode,

    output  reg                         tx_error_abort_mode_cleared,

    output  reg   [7:0]                 tx_hmc_frp,

    output  reg   [7:0]                 tx_rrp,

    output  reg   [MAX_RTC_RET_LOG-1:0] tx_returned_tokens,

    output  wire  [LOG_FPW:0]           tx_hmc_tokens_to_return,

    output  wire  [LOG_FPW:0]           tx_hmc_poisoned_tokens_to_return,

    //----------------------------------

    //----RF

    //----------------------------------

    //Monitoring    1-cycle set to increment

    output  wire  [RF_COUNTER_SIZE-1:0] rf_cnt_poisoned,

    output  wire  [RF_COUNTER_SIZE-1:0] rf_cnt_rsp,

    //Status

    output  reg                         rf_link_up,

    output  reg   [2:0]                 rf_rx_init_status,

    input   wire                        rf_hmc_sleep,

    //Init Status

    output  wire  [NUM_LANES-1:0]       rf_descrambler_part_aligned,

    output  wire  [NUM_LANES-1:0]       rf_descrambler_aligned,

    output  wire                        rf_all_descramblers_aligned,

    //Control

    output  wire  [NUM_LANES-1:0]       rf_lane_polarity,

    input   wire                        rf_scrambler_disable,

    output  wire                        rf_lane_reversal_detected,

    output  reg   [NUM_LANES-1:0]       rf_descramblers_locked,

    input   wire  [4:0]                 rf_irtry_received_threshold

);

`include "hmc_field_functions.h"

//=====================================================================================================

//-----------------------------------------------------------------------------------------------------

//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------

//-----------------------------------------------------------------------------------------------------

//=====================================================================================================

//------------------------------------------------------------------------------------Some general things

//Link state -- Most likely will be encoded as one-hot FSM

localparam              HMC_DOWN            = 3'b000;

localparam              HMC_WAIT_FOR_NULL   = 3'b001;

localparam              HMC_NULL            = 3'b010;

localparam              HMC_TS1_PART_ALIGN  = 3'b011;

localparam              HMC_TS1_FIND_REF    = 3'b100;

localparam              HMC_TS1_ALIGN       = 3'b101;

localparam              HMC_NULL_NEXT       = 3'b110;

localparam              HMC_UP              = 3'b111;

//Commands

localparam              CMD_IRTRY           = 6'b000011;

localparam              CMD_RSP_ERROR       = 6'b111110;

//Other helpful defines

localparam              WIDTH_PER_LANE          = (DWIDTH/NUM_LANES);

//16 bits is a ts1, so the init seq number is incremented according to the lane size

localparam              INIT_SEQ_INC_PER_CYCLE  = WIDTH_PER_LANE/16;

//MISC

integer i_f;    //counts to FPW

integer i_l;    //counts to NUM_LANES

integer i_c;    //counts to CYCLES_TO_COMPLETE_FULL_PACKET

genvar f;   //Counts to FPW

genvar n;   //Counts to NUM_LANES

genvar w;   //Counts to WIDTH_PER_LANE

//------------------------------------------------------------------------------------DESCRAMBLER AND DATA ORDERING

reg [NUM_LANES-1:0]     init_descrambler_part_aligned;

reg [NUM_LANES-1:0]     init_descrambler_aligned;

assign                  rf_descrambler_part_aligned = init_descrambler_part_aligned;

assign                  rf_descrambler_aligned      = init_descrambler_aligned;

//DATA and REORDERING

wire [128-1:0]              init_d_in_flit              [FPW-1:0];

wire [WIDTH_PER_LANE-1:0]   descrambled_data_per_lane   [NUM_LANES-1:0];

reg  [WIDTH_PER_LANE-1:0]   descrambled_data_per_lane_dly   [NUM_LANES-1:0];

wire [DWIDTH-1:0]           d_in;

wire [DWIDTH-1:0]           d_in_dly;

wire [128-1:0]              d_in_flit                   [FPW-1:0];

//Valid FLIT sources. A FLIT is valid when it is not NULL

wire [FPW-1:0]              valid_flit_src;         //bit0 = flit0, ...

wire [FPW-1:0]              init_valid_flit_src;    //bit0 = flit0, ...

generate

    //-- Apply lane reversal if detected

    for(n = 0; n < NUM_LANES; n = n + 1) begin : apply_lane_reversal

        for(w = 0; w < WIDTH_PER_LANE; w = w + 1) begin

            if(CTRL_LANE_REVERSAL==1)begin

                assign d_in[w*NUM_LANES+n]      = rf_lane_reversal_detected ? descrambled_data_per_lane[NUM_LANES-1-n][w] : descrambled_data_per_lane[n][w];

                assign d_in_dly[w*NUM_LANES+n]  = rf_lane_reversal_detected ? descrambled_data_per_lane_dly[NUM_LANES-1-n][w] : descrambled_data_per_lane_dly[n][w];

            end else begin

                assign d_in[w*NUM_LANES+n]      = descrambled_data_per_lane[n][w];

                assign d_in_dly[w*NUM_LANES+n]  = descrambled_data_per_lane_dly[n][w];

            end

        end

    end

    for(f = 0; f < FPW; f = f + 1) begin : reorder_input_data

        //-- Reorder the descrambled data to FLITs

        assign d_in_flit[f]       = d_in[128-1+(f*128):f*128];

        assign init_d_in_flit[f]  = d_in_dly[128-1+(f*128):f*128];

        //-- Generate valid flit positions

        assign valid_flit_src[f]        = |d_in_flit[f][5:0];

        assign init_valid_flit_src[f]   = |init_d_in_flit[f];

    end

endgenerate

//------------------------------------------------------------------------------------INIT

localparam                  LINK_DOWN   = 1'b0;

localparam                  LINK_UP     = 1'b1;

reg [NUM_LANES-1:0]         init_bit_slip;

reg [NUM_LANES-1:0]         init_bit_slip_part;

reg [RX_BIT_SLIP_CNT_LOG-1:0]init_bit_slip_cnt;

wire[NUM_LANES-1:0]         init_descrambler_locked;           //locked from the descrambler

reg [3:0]                   init_tmp_seq;

assign                      rf_all_descramblers_aligned = &init_descrambler_aligned;

//--------------TS1 recognition

localparam                  TS1_INDEPENDENT_PORTION = {4'hF,4'h0};

localparam                  TS1_LANE0_PORTION       = 4'h3;         //Not used if RX_RELAX_INIT_TIMING==1

localparam                  TS1_LANEX_PORTION       = 4'h5;         //Not used if RX_RELAX_INIT_TIMING==1

localparam                  TS1_LANE7OR15_PORTION   = 4'hc;

localparam                  TS1_SEQS_PER_CYCLE_AND_LANE = DWIDTH/NUM_LANES/16;

wire    [NUM_LANES-1:0]                  init_lane_has_correct_ts1;

wire    [TS1_SEQS_PER_CYCLE_AND_LANE-1:0]init_lane_has_correct_ts1_vec   [NUM_LANES-1:0];

genvar t;

generate

    //Make sure that the lanes have valid ts1 sequences throughout the entire data stream

    for(n=0;n<NUM_LANES;n=n+1) begin : lane_has_correct_ts1_gen

        assign init_lane_has_correct_ts1[n] = &init_lane_has_correct_ts1_vec[n];

    end

    for(t=0;t<TS1_SEQS_PER_CYCLE_AND_LANE;t=t+1) begin : ts1_recognition_gen

        if(RX_RELAX_INIT_TIMING==1) begin

            for(n=0;n<NUM_LANES;n=n+1) begin

                assign init_lane_has_correct_ts1_vec[n][t] = (descrambled_data_per_lane[n][(t*16)+8+:8] == {TS1_INDEPENDENT_PORTION});

            end

        end else begin

            for(n=1;n<NUM_LANES-1;n=n+1) begin

                assign init_lane_has_correct_ts1_vec[n][t] = (descrambled_data_per_lane[n][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANEX_PORTION});

            end

            assign init_lane_has_correct_ts1_vec[0][t] = (descrambled_data_per_lane[0][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE0_PORTION})||

                (CTRL_LANE_REVERSAL==1 ? descrambled_data_per_lane[0][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE7OR15_PORTION} : 0);

            assign init_lane_has_correct_ts1_vec[NUM_LANES-1][t] = (descrambled_data_per_lane[NUM_LANES-1][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE7OR15_PORTION})||

                (CTRL_LANE_REVERSAL==1 ? descrambled_data_per_lane[NUM_LANES-1][(t*16)+4+:12] == {TS1_INDEPENDENT_PORTION,TS1_LANE0_PORTION} : 0);

        end

    end

endgenerate

//--------------Align the lanes, scan for the ts1 seq

wire [LOG_NUM_LANES-1:0] init_lane_cnt;

assign                   init_lane_cnt = init_bit_slip_cnt[LOG_NUM_LANES-1:0];

wire [3:0]               init_seq_diff;

//If one of the descramblers is already partially aligned search for other lanes with their ts1 sequence number close this lane. 

assign                   init_seq_diff = (BITSLIP_SHIFT_RIGHT==1 ? (descrambled_data_per_lane[init_lane_cnt][3:0] - init_tmp_seq)

                                         : init_tmp_seq - descrambled_data_per_lane[init_lane_cnt][3:0]);

//------------------------------------------------------------------------------------Input Stage: Scan for Packets, Headers, Tails ...

reg  [FPW-1:0]          data2crc_hdr;

reg  [FPW-1:0]          data2crc_tail;

reg  [FPW-1:0]          data2crc_valid;

wire [(FPW*4)-1:0]      data2crc_lng;

reg  [3:0]              data2crc_lng_per_flit [FPW-1:0];

reg  [3:0]              data2crc_payload_remain;

reg  [FPW-1:0]          data2crc_hdr_comb;

reg  [FPW-1:0]          data2crc_tail_comb;

reg  [FPW-1:0]          data2crc_valid_comb;

reg  [3:0]              data2crc_lng_per_flit_comb [FPW-1:0];

reg  [3:0]              data2crc_payload_remain_comb;

generate

        for(f = 0; f < (FPW); f = f + 1) begin : reorder_crc_input

            assign data2crc_lng[(f*4)+:4] = data2crc_lng_per_flit[f];

        end

endgenerate

//------------------------------------------------------------------------------------CRC

wire [DWIDTH-1:0]       crc_d_out_data;

wire [128-1:0]          crc_d_out_flit              [FPW-1:0];

wire [FPW-1:0]          crc_d_out_flit_is_hdr;

wire [FPW-1:0]          crc_d_out_flit_is_tail;

wire [FPW-1:0]          crc_d_out_flit_is_valid;

wire [FPW-1:0]          crc_d_out_flit_is_error;

wire [FPW-1:0]          crc_d_out_flit_is_poisoned;

wire [FPW-1:0]          crc_d_out_flit_has_rtc;

wire [FPW-1:0]          crc_d_out_flit_is_flow;

generate

        for(f=0;f<FPW;f=f+1) begin : reorder_crc_output

            assign crc_d_out_flit[f] = crc_d_out_data[128-1+(f*128):f*128];

        end

endgenerate

//------------------------------------------------------------------------------------Start TX retry Stage

reg     [128-1:0]       flit_after_irtry_stage                   [FPW-1:0];

reg     [FPW-1:0]       flit_after_irtry_stage_is_hdr;

reg     [FPW-1:0]       flit_after_irtry_stage_is_tail;

reg     [FPW-1:0]       flit_after_irtry_stage_is_valid;

reg     [FPW-1:0]       flit_after_irtry_stage_is_error;

reg     [FPW-1:0]       flit_after_irtry_stage_is_poisoned;

reg     [FPW-1:0]       flit_after_irtry_stage_has_rtc;

reg     [FPW-1:0]       flit_after_irtry_stage_is_start_retry;

reg     [FPW-1:0]       flit_after_irtry_stage_is_clear_error;

reg     [FPW-1:0]       flit_after_irtry_stage_is_start_retry_comb;

reg     [FPW-1:0]       flit_after_irtry_stage_is_clear_error_comb;

//------------------------------------------------------------------------------------SeqStage and Seqnum

reg     [128-1:0]       flit_after_seq_check                   [FPW-1:0];

reg     [FPW-1:0]       flit_after_seq_check_is_hdr;

reg     [FPW-1:0]       flit_after_seq_check_is_tail;

reg     [FPW-1:0]       flit_after_seq_check_is_valid;

reg     [FPW-1:0]       flit_after_seq_check_is_error;

reg     [FPW-1:0]       flit_after_seq_check_is_error_comb;

reg     [FPW-1:0]       flit_after_seq_check_is_poisoned;

reg     [FPW-1:0]       flit_after_seq_check_has_rtc;

reg     [FPW-1:0]       flit_after_seq_check_is_start_retry;

reg     [FPW-1:0]       flit_after_seq_check_is_clear_error;

reg     [2:0]           next_seqnum;

reg     [2:0]           next_seqnum_comb; //can be reduced to [1:0] for 2FLIT config

reg     [2:0]           first_seq_after_error;

//------------------------------------------------------------------------------------IRTRY packet count stage

reg     [128-1:0]       flit_after_mask_stage                   [FPW-1:0];

reg     [FPW-1:0]       flit_after_mask_stage_is_hdr;

reg     [FPW-1:0]       flit_after_mask_stage_is_tail;

reg     [FPW-1:0]       flit_after_mask_stage_is_valid;

reg     [FPW-1:0]       flit_after_mask_stage_is_valid_mask_lsb;

reg     [FPW-1:0]       flit_after_mask_stage_is_valid_mask_msb;

reg     [FPW-1:0]       flit_after_mask_stage_is_error;

reg     [FPW-1:0]       flit_after_mask_stage_is_poisoned;

reg     [FPW-1:0]       flit_after_mask_stage_is_start_retry;

reg     [FPW-1:0]       flit_after_mask_stage_has_rtc;

//Assign FLITs to word, necessary for the invalidation stage pipeline

wire   [DWIDTH-1:0]            flit_after_mask_stage_word;

generate

        for(f = 0; f < (FPW); f = f + 1) begin : reorder_flits_to_word

            assign flit_after_mask_stage_word[(f*128)+128-1:(f*128)] = flit_after_mask_stage[f];

        end

endgenerate

//------------------------------------------------------------------------------------Invalidation Stage

//Assuming Max Pkt size = 9 FLITs

localparam CYCLES_TO_COMPLETE_FULL_PACKET   =   (FPW == 2) ? 5 :

                                                (FPW == 4) ? 3 :

                                                (FPW == 6) ? 3 :

                                                2;

//Regs to retrieve the pkt length, assign the length to correspoding tail. The packet will be invalidated then

reg     [3:0]        lng_per_tail      [FPW-1:0] ;

reg     [3:0]        lng_per_tail_comb [FPW-1:0] ;

reg     [3:0]        lng_temp;

reg     [3:0]        lng_comb;

//Signal that an error was detected. Invalidate all FLITs after

reg                  error;

reg     [DWIDTH-1:0]    flit_in_invalidation_data          [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];

reg     [FPW-1:0]       flit_in_invalidation_is_hdr        [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];

reg     [FPW-1:0]       flit_in_invalidation_is_tail       [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];

reg     [FPW-1:0]       flit_in_invalidation_is_valid      [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];

reg     [FPW-1:0]       flit_in_invalidation_mask_error;

reg     [FPW-1:0]       flit_in_invalidation_is_poisoned   [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];

reg     [FPW-1:0]       flit_in_invalidation0_is_poisoned_comb;

//------------------------------------------------------------------------------------Checked FLITs

wire     [128-1:0]      checked_flit             [FPW-1:0];

wire     [FPW-1:0]      checked_flit_is_poisoned;

wire     [FPW-1:0]      checked_flit_is_valid;

wire     [FPW-1:0]      checked_flit_is_hdr;

wire     [FPW-1:0]      checked_flit_is_tail;

assign checked_flit_is_hdr         = flit_in_invalidation_is_hdr       [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid     [CYCLES_TO_COMPLETE_FULL_PACKET-1];

assign checked_flit_is_tail        = flit_in_invalidation_is_tail      [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid     [CYCLES_TO_COMPLETE_FULL_PACKET-1];

assign checked_flit_is_valid       = flit_in_invalidation_is_valid     [CYCLES_TO_COMPLETE_FULL_PACKET-1] ;

assign checked_flit_is_poisoned    = flit_in_invalidation_is_poisoned  [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid     [CYCLES_TO_COMPLETE_FULL_PACKET-1];

generate

        for(f = 0; f < (FPW); f = f + 1) begin : reorder_invalidation_word_back_to_flits

            assign checked_flit[f] = flit_in_invalidation_data[CYCLES_TO_COMPLETE_FULL_PACKET-1][128-1+(f*128):f*128];

        end

endgenerate

//------------------------------------------------------------------------------------Counter

reg [LOG_FPW:0]             rf_cnt_poisoned_comb;

reg [LOG_FPW:0]             rf_cnt_rsp_comb;

//------------------------------------------------------------------------------------Input Buffer

reg     [MAX_RTC_RET_LOG-1:0]rtc_sum_comb; //for 8 FLIT config, maximum 8*31 tokens will be returned per cycle

reg     [128-1:0]            input_buffer_d_in_flit    [FPW-1:0];

reg     [FPW-1:0]            input_buffer_is_valid;

reg     [FPW-1:0]            input_buffer_is_hdr;

reg     [FPW-1:0]            input_buffer_is_tail;

reg     [FPW-1:0]            input_buffer_is_error_rsp;

wire    [DWIDTH+(4*FPW)-1:0] input_buffer_d_in;

wire    [DWIDTH+(4*FPW)-1:0] input_buffer_d_out;

wire                         input_buffer_empty;

wire                         input_buffer_shift_in;

wire                         input_buffer_shift_out;

assign                       input_buffer_shift_out    =   ~(input_buffer_empty || d_out_fifo_a_full);

generate

        for(f = 0; f < (FPW); f = f + 1) begin : assign_flits_to_input_buffer_to_a_single_reg

            assign input_buffer_d_in[f*128+128-1:f*128] = input_buffer_d_in_flit[f];

            assign input_buffer_d_in[DWIDTH+f]          = input_buffer_is_valid[f];

            assign input_buffer_d_in[DWIDTH+f+FPW]      = input_buffer_is_hdr[f];

            assign input_buffer_d_in[DWIDTH+f+(2*FPW)]  = input_buffer_is_tail[f];

            assign input_buffer_d_in[DWIDTH+f+(3*FPW)]  = input_buffer_is_error_rsp[f];

        end

endgenerate

//------------------------------------------------------------------------------------LINK RETRY

reg  [4:0]     irtry_start_retry_cnt;

reg  [4:0]     irtry_clear_error_cnt;

reg  [4:0]     irtry_start_retry_cnt_comb;

reg  [4:0]     irtry_clear_error_cnt_comb;

reg            irtry_clear_trig;

//=====================================================================================================

//-----------------------------------------------------------------------------------------------------

//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------

//-----------------------------------------------------------------------------------------------------

//=====================================================================================================

//========================================================================================================================================

//------------------------------------------------------------------INIT

//========================================================================================================================================

generate

    if(CTRL_LANE_REVERSAL==1) begin : control_lane_reversal

        reg    init_lane_reversal_detected;

        assign rf_lane_reversal_detected = init_lane_reversal_detected;

        `ifdef ASYNC_RES

        always @(posedge clk or negedge res_n)  begin `else

        always @(posedge clk)  begin `endif

            if(!res_n) begin

                init_lane_reversal_detected   <= 1'b0;

            end else begin

                if(rf_rx_init_status==HMC_DOWN) begin

                    init_lane_reversal_detected   <= 1'b0;

                end

                if(rf_rx_init_status==HMC_TS1_ALIGN && rf_all_descramblers_aligned && (descrambled_data_per_lane[0][7:4] ==  TS1_LANE7OR15_PORTION)) begin

                    //lane reversal detected, reverse the input stream lane by lane

                    init_lane_reversal_detected   <= 1'b1;

                end

            end

        end

    end else begin

        assign rf_lane_reversal_detected = 1'b0;

    end

    if(DETECT_LANE_POLARITY==1) begin : detect_lane_reversal

        reg [NUM_LANES-1:0] init_lane_polarity;

        assign rf_lane_polarity = init_lane_polarity;

        `ifdef ASYNC_RES

        always @(posedge clk or negedge res_n)  begin `else

        always @(posedge clk)  begin `endif

            if(!res_n) begin

                init_lane_polarity        <= {NUM_LANES{1'b0}};

            end else begin

                if(rf_rx_init_status==HMC_DOWN) begin

                    init_lane_polarity    <= {NUM_LANES{1'b0}};

                end

                //Detect Lane polarity when HMC is sending first NULLs

                if(rf_rx_init_status==HMC_WAIT_FOR_NULL) begin

                    for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin

                        if(descrambled_data_per_lane[i_l] == {WIDTH_PER_LANE{1'b1}})begin

                            init_lane_polarity[i_l] <=  1'b1;

                        end

                    end

                end

            end

        end

    end else begin

        assign rf_lane_polarity = {NUM_LANES{1'b0}};

    end

endgenerate

`ifdef ASYNC_RES

always @(posedge clk or negedge res_n)  begin `else

always @(posedge clk)  begin `endif

    for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin

        `ifdef RESET_ALL

            if(!res_n) descrambled_data_per_lane_dly[i_l] <= {WIDTH_PER_LANE{1'b0}};

            else

        `endif

        descrambled_data_per_lane_dly[i_l] <= descrambled_data_per_lane[i_l];

    end

if(!res_n) begin

    //----Misc

    init_descrambler_aligned        <= {NUM_LANES{1'b0}};

    init_descrambler_part_aligned   <= {NUM_LANES{1'b0}};

    phy_bit_slip                    <= {NUM_LANES{1'b0}};

    init_bit_slip                   <= {NUM_LANES{1'b0}};

    init_bit_slip_part              <= {NUM_LANES{1'b0}};

    init_bit_slip_cnt               <= {RX_BIT_SLIP_CNT_LOG{1'b0}};

    init_tmp_seq                    <= 4'h0;

    rf_rx_init_status               <= HMC_DOWN;

    rf_link_up                      <= LINK_DOWN;

    rf_descramblers_locked          <= {NUM_LANES{1'b0}};

end

else begin

    rf_descramblers_locked  <= run_rx ? init_descrambler_locked : {NUM_LANES{1'b0}};

    init_bit_slip           <= {NUM_LANES{1'b0}};

    init_bit_slip_part      <= {NUM_LANES{1'b0}};

    phy_bit_slip            <= init_bit_slip | init_bit_slip_part;

    init_tmp_seq            <= init_tmp_seq + INIT_SEQ_INC_PER_CYCLE;

    init_bit_slip_cnt   <= init_bit_slip_cnt +1;

    case (rf_rx_init_status)

        HMC_DOWN: begin

            init_descrambler_aligned         <= {NUM_LANES{1'b0}};

            init_descrambler_part_aligned    <= {NUM_LANES{1'b0}};

            if(&rf_descramblers_locked) begin

                rf_rx_init_status <= HMC_WAIT_FOR_NULL;

            end

        end

        HMC_WAIT_FOR_NULL: begin

            if(|init_valid_flit_src == 1'b0) begin

                rf_rx_init_status <= HMC_NULL;

            end

        end

        HMC_NULL: begin

            if(&init_valid_flit_src) begin

                rf_rx_init_status      <= HMC_TS1_PART_ALIGN;

            end

        end

        HMC_TS1_PART_ALIGN: begin

            if(|init_bit_slip_cnt[RX_BIT_SLIP_CNT_LOG-1:LOG_NUM_LANES] == 1'b0)begin

                init_bit_slip_part[init_lane_cnt]                <= ~init_lane_has_correct_ts1[init_lane_cnt];

                init_descrambler_part_aligned[init_lane_cnt]     <= init_lane_has_correct_ts1[init_lane_cnt];

            end

            if(&init_descrambler_part_aligned/*=={NUM_LANES{1'b1}}*/) begin

                rf_rx_init_status   <= HMC_TS1_FIND_REF;

                init_tmp_seq        <= descrambled_data_per_lane[0][3:0] + INIT_SEQ_INC_PER_CYCLE;

                init_bit_slip_cnt   <= {RX_BIT_SLIP_CNT_LOG{1'b0}};

            end

        end