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[/] [openhmc/] [trunk/] [openHMC/] [rtl/] [hmc_controller/] [tx/] [tx_link.v] - Blame information for rev 15

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1 11 juko 
/*
2 
 *                              .--------------. .----------------. .------------.
3 
 *                             | .------------. | .--------------. | .----------. |
4 
 *                             | | ____  ____ | | | ____    ____ | | |   ______ | |
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 *                             | ||_   ||   _|| | ||_   \  /   _|| | | .' ___  || |
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 *       ___  _ __   ___ _ __  | |  | |__| |  | | |  |   \/   |  | | |/ .'   \_|| |
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 *      / _ \| '_ \ / _ \ '_ \ | |  |  __  |  | | |  | |\  /| |  | | || |       | |
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 *       (_) | |_) |  __/ | | || | _| |  | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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 *      \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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 *           | |               | |            | | |              | | |          | |
11 
 *           |_|               | '------------' | '--------------' | '----------' |
12 
 *                              '--------------' '----------------' '------------'
13 
 *
14 
 *  openHMC - An Open Source Hybrid Memory Cube Controller
15 
 *  (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
16 
 *  www.ziti.uni-heidelberg.de
17 
 *  B6, 26
18 
 *  68159 Mannheim
19 
 *  Germany
20 
 *
21 
 *  Contact: openhmc@ziti.uni-heidelberg.de
22 
 *  http://ra.ziti.uni-heidelberg.de/openhmc
23 
 *
24 
 *   This source file is free software: you can redistribute it and/or modify
25 
 *   it under the terms of the GNU Lesser General Public License as published by
26 
 *   the Free Software Foundation, either version 3 of the License, or
27 
 *   (at your option) any later version.
28 
 *
29 
 *   This source file is distributed in the hope that it will be useful,
30 
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
31 
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
32 
 *   GNU Lesser General Public License for more details.
33 
 *
34 
 *   You should have received a copy of the GNU Lesser General Public License
35 
 *   along with this source file.  If not, see <http://www.gnu.org/licenses/>.
36 
 *
37 
 *
38 
 *  Module name: tx_link
39 
 *
40 
 */
41 
 
42 
`default_nettype none
43 
 
44 
module tx_link #(
45 
    parameter LOG_FPW           = 2,
46 
    parameter FPW               = 4,
47 
    parameter DWIDTH            = FPW*128,
48 
    parameter NUM_LANES         = 8,
49 15 juko 
    parameter RF_COUNTER_SIZE   = 64,
50 11 juko 
    parameter HMC_RX_AC_COUPLED = 1,
51 15 juko 
    parameter MAX_RTC_RET_LOG   = 8,
52 
    parameter LOG_MAX_RX_TOKENS = 8,
53 
    parameter LOG_MAX_HMC_TOKENS= 10,
54 
    parameter LOG_IRTRY_TIMOUT  = 8,
55 
    parameter XIL_CNT_PIPELINED = 0,
56 11 juko 
    //Debug
57 15 juko 
    parameter DBG_RX_TOKEN_MON  = 1,
58 
    parameter OPEN_RSP_MODE     = 0
59 11 juko 
) (
60 
 
61 
    //----------------------------------
62 
    //----SYSTEM INTERFACE
63 
    //----------------------------------
64 
    input   wire                        clk,
65 
    input   wire                        res_n,
66 
 
67 
    //----------------------------------
68 
    //----TO HMC PHY
69 
    //----------------------------------
70 
    output  wire [DWIDTH-1:0]           phy_scrambled_data_out,
71 
 
72 
    //----------------------------------
73 
    //----HMC IF
74 
    //----------------------------------
75 15 juko 
    output  reg                         LXRXPS,
76 
    input   wire                        LXTXPS,
77 11 juko 
 
78 
    //----------------------------------
79 
    //----Input data
80 
    //----------------------------------
81 
    input   wire [DWIDTH-1:0]           d_in_data,
82 
    input   wire [FPW-1:0]              d_in_flit_is_hdr,
83 
    input   wire [FPW-1:0]              d_in_flit_is_tail,
84 
    input   wire [FPW-1:0]              d_in_flit_is_valid,
85 
    input   wire                        d_in_empty,
86 
    input   wire                        d_in_a_empty,
87 
    output  reg                         d_in_shift_out,
88 
 
89 
    //----------------------------------
90 
    //----RX Block
91 
    //----------------------------------
92 
    input   wire                        rx_force_tx_retry,
93 
    input   wire                        rx_error_abort_mode,
94 
    input   wire                        rx_error_abort_mode_cleared,
95 15 juko 
    input   wire [7:0]                  rx_hmc_frp,
96 
    input   wire [7:0]                  rx_rrp,
97 
    input   wire [MAX_RTC_RET_LOG-1:0]  rx_returned_tokens,
98 11 juko 
    input   wire [LOG_FPW:0]            rx_hmc_tokens_to_return,
99 
    input   wire [LOG_FPW:0]            rx_hmc_poisoned_tokens_to_return,
100 
 
101 
    //----------------------------------
102 
    //----RF
103 
    //----------------------------------
104 
    //Monitoring    1-cycle set to increment
105 
    output  reg                         rf_cnt_retry,
106 15 juko 
    output  wire [RF_COUNTER_SIZE-1:0]  rf_sent_p,
107 
    output  wire [RF_COUNTER_SIZE-1:0]  rf_sent_np,
108 
    output  wire [RF_COUNTER_SIZE-1:0]  rf_sent_r,
109 11 juko 
    output  reg                         rf_run_length_bit_flip,
110 
    output  reg                         rf_error_abort_not_cleared,
111 
 
112 
    //Status
113 
    input   wire                        rf_link_is_up,
114 
    input   wire                        rf_hmc_received_init_null,
115 
    input   wire                        rf_descramblers_aligned,
116 
    output  wire [1:0]                  rf_tx_init_status,
117 15 juko 
    output  reg  [LOG_MAX_HMC_TOKENS-1:0]rf_hmc_tokens_av,
118 
    output  wire [LOG_MAX_RX_TOKENS-1:0]rf_rx_tokens_av,
119 11 juko 
 
120 
    //Control
121 
    input   wire                        rf_hmc_sleep_requested,
122 15 juko 
    input   wire                        rf_warm_reset,
123 11 juko 
    input   wire                        rf_scrambler_disable,
124 15 juko 
    input   wire [LOG_MAX_RX_TOKENS-1:0]rf_rx_buffer_rtc,
125 11 juko 
    input   wire [4:0]                  rf_irtry_to_send,
126 15 juko 
    input   wire                        rf_run_length_enable
127 11 juko 
 
128 
);
129 
 
130 
`include "hmc_field_functions.h"
131 
 
132 
//=====================================================================================================
133 
//-----------------------------------------------------------------------------------------------------
134 
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
135 
//-----------------------------------------------------------------------------------------------------
136 
//=====================================================================================================
137 
//------------------------------------------------------------------------------------General Assignments
138 
localparam LANE_WIDTH       = (DWIDTH/NUM_LANES);
139 
 
140 
integer i_f;    //counts to FPW
141 
integer i_t;    //counts to number of TS1 packets in a word
142 
 
143 
//Packet command 3-MSB definition
144 
localparam PKT_WRITE        = 3'b001;
145 
localparam PKT_MISC_WRITE   = 3'b010;
146 
localparam PKT_READ         = 3'b110;
147 
localparam PKT_MODE_READ    = 3'b101;
148 
localparam PKT_P_WRITE      = 3'b011;
149 
localparam PKT_MISC_P_WRITE = 3'b100;
150 
 
151 15 juko 
localparam CMD_IRTRY        = 6'b000011;
152 
 
153 11 juko 
//------------------------------------------------------------------------------------Scrambler
154 
wire [14:0]             seed_lane   [NUM_LANES-1:0];
155 
 
156 
assign seed_lane[0]     = 15'h4D56;
157 
assign seed_lane[1]     = 15'h47FF;
158 
assign seed_lane[2]     = 15'h75B8;
159 
assign seed_lane[3]     = 15'h1E18;
160 
assign seed_lane[4]     = 15'h2E10;
161 
assign seed_lane[5]     = 15'h3EB2;
162 
assign seed_lane[6]     = 15'h4302;
163 
assign seed_lane[7]     = 15'h1380;
164 
 
165 
generate
166 
    if(NUM_LANES==16) begin : seed_gen_16x
167 
        assign seed_lane[8]     = 15'h3EB3;
168 
        assign seed_lane[9]     = 15'h2769;
169 
        assign seed_lane[10]    = 15'h4580;
170 
        assign seed_lane[11]    = 15'h5665;
171 
        assign seed_lane[12]    = 15'h6318;
172 
        assign seed_lane[13]    = 15'h6014;
173 
        assign seed_lane[14]    = 15'h077B;
174 
        assign seed_lane[15]    = 15'h261F;
175 
    end
176 
endgenerate
177 
 
178 15 juko 
wire [NUM_LANES-1:0]    bit_was_flipped;
179 11 juko 
 
180 
//------------------------------------------------------------------------------------FSM and States
181 15 juko 
reg [2:0]  state;
182 
reg [1:0]  init_state;
183 
localparam INIT_TX_NULL_1       = 2'b00;
184 
localparam INIT_TX_TS1          = 2'b01;
185 
localparam INIT_TX_NULL_2       = 2'b11;
186 
localparam INIT_DONE            = 2'b10;
187 11 juko 
 
188 15 juko 
localparam INIT                 = 3'b000;
189 
localparam IDLE                 = 3'b001;
190 
localparam TX                   = 3'b010;
191 
localparam HMC_RTRY             = 3'b011;
192 
localparam SLEEP                = 3'b100;
193 
localparam WAIT_FOR_HMC         = 3'b101;
194 
localparam LNK_RTRY             = 3'b110;
195 
localparam DEBUG                = 3'b111;
196 11 juko 
 
197 15 juko 
assign  rf_tx_init_status = init_state;
198 
 
199 11 juko 
reg     rtc_rx_initialize;
200 
 
201 
//------------------------------------------------------------------------------------DATA and ORDERING
202 
//reorder incoming data to FLITs
203 15 juko 
wire [127:0]   d_in_flit [FPW-1:0];
204 11 juko 
genvar  f;
205 
generate
206 
        for(f = 0; f < (FPW); f = f + 1) begin : reorder_input_data_to_flits
207 15 juko 
            assign d_in_flit[f] = d_in_data[127+(f*128):f*128];
208 11 juko 
        end
209 
endgenerate
210 
 
211 
//Create a mask and an input buffer that is necessary if packet transmission is interrupted and packets remain untransmitted
212 
reg                 d_in_use_buf;
213 15 juko 
reg  [127:0]        d_in_buf_flit          [FPW-2:0];
214 
reg  [FPW-2:0]      d_in_buf_flit_is_hdr;
215 
reg  [FPW-2:0]      d_in_buf_flit_is_valid;
216 11 juko 
 
217 
//Reorder the data per lane
218 
wire [DWIDTH-1:0]   data_rdy;
219 
wire [DWIDTH-1:0]   data_to_scrambler;
220 
 
221 
genvar l,n;
222 
generate
223 
    for(n = 0; n < NUM_LANES; n = n + 1) begin : reorder_data_to_lanes
224 
        for(l = 0; l < LANE_WIDTH; l = l + 1) begin
225 
            assign data_to_scrambler[l+n*LANE_WIDTH] = data_rdy[l*NUM_LANES+n];
226 
        end
227 
    end
228 
endgenerate
229 
 
230 
//------------------------------------------------------------------------------------Init Regs
231 15 juko 
localparam TS1_SEQ_INC_VAL_PER_CYCLE        = (NUM_LANES==8) ? FPW : (FPW/2);
232 
localparam LOG_CYCLES_NULL_TO_SEND          = (FPW == 2) ? 4 :
233 
                                              (FPW == 4) ? 3 :
234 
                                              (FPW == 6) ? 3 :
235 
                                              2;
236 11 juko 
 
237 
wire  [(NUM_LANES*4)-1:0]       ts1_seq_part_reordered      [TS1_SEQ_INC_VAL_PER_CYCLE-1:0];    //ts1 seq is 4 bits
238 
reg   [3:0]                     ts1_seq_nr_per_flit         [TS1_SEQ_INC_VAL_PER_CYCLE-1:0];
239 15 juko 
wire  [127:0]                   ts1_flit                    [FPW-1:0];
240 
reg   [LOG_CYCLES_NULL_TO_SEND-1:0] num_null_cycles_sent;
241 11 juko 
 
242 
generate
243 
    for(f = 0; f < TS1_SEQ_INC_VAL_PER_CYCLE; f = f + 1) begin : generate_lane_dependent_ts1_sequence
244 
 
245 
        for(n=0; n<4; n=n+1) begin
246 
            assign ts1_seq_part_reordered[f][(n*NUM_LANES)+NUM_LANES-1:(n*NUM_LANES)] = {NUM_LANES{ts1_seq_nr_per_flit[f][n]}};
247 
        end
248 
 
249 
        if(NUM_LANES==8) begin
250 
            assign ts1_flit[f] = {
251 
                32'hffffffff,32'h0,1'h1,7'h0,7'b1111111,1'h0,7'h0,1'h1,1'h0,7'b1111111,ts1_seq_part_reordered[f]
252 
            };
253 
        end else begin
254 15 juko 
            assign ts1_flit[f*2+1] = {
255 11 juko 
                64'hffffffffffffffff,64'h0
256 
            };
257 15 juko 
            assign ts1_flit[f*2] = {
258 
                16'h8000,16'hfffe,16'h0001,16'h7fff,ts1_seq_part_reordered[f]
259 11 juko 
            };
260 
        end
261 
 
262 
    end
263 
endgenerate
264 
//------------------------------------------------------------------------------------Counter variables
265 
reg  [LOG_FPW:0]    rf_sent_p_comb;
266 
reg  [LOG_FPW:0]    rf_sent_np_comb;
267 
reg  [LOG_FPW:0]    rf_sent_r_comb;
268 
 
269 15 juko 
//------------------------------------------------------------------------------------SEQ FRP RTC Stage
270 
reg  [127:0]        data2rtc_stage_flit     [FPW-1:0];
271 11 juko 
reg  [FPW-1:0]      data2rtc_stage_flit_is_hdr;
272 
reg  [FPW-1:0]      data2rtc_stage_flit_is_tail;
273 
reg  [FPW-1:0]      data2rtc_stage_flit_is_valid;
274 
reg                 data2rtc_stage_is_flow;
275 
reg                 data2rtc_stage_force_tx_retry;
276 
 
277 15 juko 
reg  [127:0]        data2seq_frp_stage_flit          [FPW-1:0];
278 
reg  [FPW-1:0]      data2seq_frp_stage_flit_is_hdr;
279 
reg  [FPW-1:0]      data2seq_frp_stage_flit_is_tail;
280 
reg  [FPW-1:0]      data2seq_frp_stage_flit_is_valid;
281 
reg                 data2seq_frp_stage_is_flow;
282 
reg                 data2seq_frp_stage_force_tx_retry;
283 
 
284 
//Information used to fill the retry buffer
285 
reg [LOG_FPW-1:0]   target_temp [FPW:0];
286 
reg [LOG_FPW-1:0]   next_target;
287 
reg [LOG_FPW-1:0]   target      [FPW-1:0];
288 
 
289 
reg [LOG_FPW:0]     tx_seqnum_inc;
290 
reg [2:0]           tx_seqnum_temp [FPW-1:0];
291 
 
292 11 juko 
//------------------------------------------------------------------------------------RETRY
293 
//HMC
294 15 juko 
//Number of cycles to wait until start HMC retry is issued again (when RX error abort is not cleared)
295 
reg  [LOG_IRTRY_TIMOUT-1:0] error_abort_mode_clr_cnt;
296 
reg                         force_hmc_retry;
297 
reg  [4:0]                  irtry_start_retry_cnt;
298 
reg  [4:0]                  irtry_clear_error_cnt;
299 
wire [63:0]                 irtry_hdr;
300 
assign                      irtry_hdr = {6'h0,34'h0,9'h0,4'h1,4'h1,1'h0,6'b000011};
301 11 juko 
 
302 
//------------------------------------------------------------------------------------Retry Buffer
303 
localparam RAM_ADDR_SIZE   =   (FPW == 2) ? 7 :
304 
                               (FPW == 4) ? 6 :
305 
                               (FPW == 6) ? 5 :
306 
                               (FPW == 8) ? 5 :
307 
                               1;
308 
 
309 15 juko 
reg  [127:0]                data2ram_flit           [FPW-1:0];
310 
reg  [127:0]                data2ram_flit_temp      [FPW-1:0];
311 
reg  [FPW-1:0]              data2ram_flit_is_hdr;
312 
reg  [FPW-1:0]              data2ram_flit_is_tail;
313 
reg  [FPW-1:0]              data2ram_flit_is_valid;
314 
reg                         data2ram_force_tx_retry;
315 
 
316 
//Header/Tail fields, and at the same time form the RAM read pointer
317 
reg  [RAM_ADDR_SIZE-1:0]    tx_frp_adr [FPW-1:0];
318 
reg  [2:0]                  tx_seqnum;
319 
 
320 
 
321 
reg [FPW-1:0]               ram_w_en ;
322 
reg                         ram_r_en;
323 11 juko 
wire [RAM_ADDR_SIZE-1:0]    ram_w_addr_next;
324 15 juko 
assign                      ram_w_addr_next = tx_frp_adr[0] + 1;
325 11 juko 
reg  [RAM_ADDR_SIZE-1:0]    ram_r_addr_temp;
326 
reg  [FPW-1:0]              ram_r_mask;
327 
wire [128+3-1:0]            ram_r_data              [FPW-1:0];
328 
reg  [128+3-1:0]            ram_w_data              [FPW-1:0];
329 
 
330 
wire  [RAM_ADDR_SIZE-1:0]   ram_r_addr;
331 15 juko 
assign                      ram_r_addr = rx_rrp[7:8-RAM_ADDR_SIZE];
332 11 juko 
 
333 
//Avoid overwriting not acknowleged FLITs in the retry buffer
334 
wire [RAM_ADDR_SIZE-1:0]    ram_result;
335 
assign                      ram_result          = ram_r_addr - ram_w_addr_next;
336 
 
337 15 juko 
//A safe value since ram_w_addr_next is calculated some cycles after packets were accepted
338 11 juko 
wire                        ram_full;
339 
assign                      ram_full = (ram_result<9 && ram_result>0) ? 1'b1 : 1'b0 ;
340 
 
341 
//Regs for TX Link retry handling
342 
reg                 tx_retry_finished;
343 
reg                 tx_retry_ongoing;
344 
reg                 tx_link_retry_request;  //Sample the retry request
345 
 
346 
//------------------------------------------------------------------------------------RRP Stage
347 15 juko 
reg  [127:0]        data2rrp_stage_flit           [FPW-1:0];
348 11 juko 
reg  [FPW-1:0]      data2rrp_stage_flit_is_hdr;
349 
reg  [FPW-1:0]      data2rrp_stage_flit_is_tail;
350 
reg  [FPW-1:0]      data2rrp_stage_flit_is_valid;
351 
 
352 15 juko 
`ifdef SIMULATION
353 
    //We dont want to crash a simulation run because PRETs are still travelling upon test completion, so we include a trigger to only send PRETs when necessary in simulation
354 
    //In hardware, PRETs will be sent whenever there is no valid FLIT on position 0 -> reduces the overall pointer return delay
355 
    reg  [7:0]  last_transmitted_rx_hmc_frp;
356 
`else
357 
    reg         send_prets;
358 
`endif
359 11 juko 
 
360 
//------------------------------------------------------------------------------------CRC
361 15 juko 
reg  [127:0]        data2crc_flit           [FPW-1:0];
362 11 juko 
wire [DWIDTH-1:0]   data2crc;
363 
reg  [FPW-1:0]      data2crc_flit_is_hdr;
364 
reg  [FPW-1:0]      data2crc_flit_is_tail;
365 
 
366 
generate
367 
    for(f = 0; f < (FPW); f = f + 1) begin : concatenate_flits_to_single_reg
368 15 juko 
        assign data2crc[(f*128)+127:(f*128)]  = data2crc_flit[f];
369 11 juko 
    end
370 
endgenerate
371 
 
372 
//------------------------------------------------------------------------------------FLOW PACKETS
373 
//TRET
374 
wire    [63:0]              tret_hdr;
375 15 juko 
assign                      tret_hdr        = {6'h0,34'h0,9'h0,4'h1,4'h1,1'h0,6'b000010};
376 11 juko 
//PRET
377 15 juko 
wire    [63:0]              pret_hdr;
378 
assign                      pret_hdr        = {6'h0,34'h0,9'h0,4'h1,4'h1,1'h0,6'b000001};
379 11 juko 
 
380 
//------------------------------------------------------------------------------------RTC HANDLING
381 
//Registers for the RTC field in request packets
382 
reg                         rtc_return;
383 
reg  [4:0]                  rtc_return_val;
384 
 
385 
//A safe value to not send more FLITs than the HMC can buffer
386 15 juko 
reg  [LOG_FPW-1:0]          num_flits_in_buf;
387 
reg  [LOG_FPW:0]            num_flits_transmitted;
388 
reg  [LOG_MAX_RX_TOKENS-1:0]remaining_tokens;
389 
localparam TOKENS_THRESHOLD=   (FPW == 2) ? 11 :
390 
                               (FPW == 4) ? 15 :
391 
                               (FPW == 6) ? 23 :
392 
                               (FPW == 8) ? 23 :
393 
                               1;
394 11 juko 
wire                        hmc_tokens_av;
395 15 juko 
assign                      hmc_tokens_av = ((rf_hmc_tokens_av+num_flits_in_buf+rx_returned_tokens) > TOKENS_THRESHOLD) ? 1'b1 : 1'b0;
396 11 juko 
 
397 
//Return a maximum of 31 tokens
398 
wire [4:0]                  outstanding_tokens_to_return;
399 15 juko 
assign                      outstanding_tokens_to_return   = (OPEN_RSP_MODE==0) ? (remaining_tokens > 31 ? 31 : remaining_tokens[4:0]) : 5'h0;
400 11 juko 
 
401 
//=====================================================================================================
402 
//-----------------------------------------------------------------------------------------------------
403 
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
404 
//-----------------------------------------------------------------------------------------------------
405 
//=====================================================================================================
406 
 
407 
//====================================================================
408 
//---------------------------------MISC
409 
//====================================================================
410 
`ifdef ASYNC_RES
411 
always @(posedge clk or negedge res_n)  begin `else
412 
always @(posedge clk)  begin `endif
413 
if(!res_n) begin
414 
    rf_run_length_bit_flip   <= 1'b0;
415 
end else begin
416 
    rf_run_length_bit_flip   <= |bit_was_flipped;
417 
end
418 
end
419 
 
420 
//====================================================================
421 
//---------------------------------Monitor Remaining Tokens in the RX input buffer, just a debug help
422 
//====================================================================
423 
//Track the remaining tokens in the rx input buffer. This is optional since the HMC must make sure not to send more tokens than RX can buffer, useful for debugging
424 
generate
425 15 juko 
if(DBG_RX_TOKEN_MON==1 && OPEN_RSP_MODE==0) begin : Tokens_in_RX_buf
426 11 juko 
 
427 
    reg  [6:0]                  sum_requested_tokens;       //Count the amount of tokens requested from the HMC
428 
    reg  [6:0]                  sum_requested_tokens_temp;  //Use this register for combinational logic
429 
 
430 
    always @(*)  begin
431 
        sum_requested_tokens_temp   = {7{1'b0}};
432 
 
433 
        for(i_f=0;i_f<FPW;i_f=i_f+1) begin
434 
 
435 
            if(data2rtc_stage_flit_is_hdr[i_f] && data2rtc_stage_flit_is_valid[i_f]) begin
436 
 
437 
                if(cmd_type(data2rtc_stage_flit[i_f]) == PKT_READ ||
438 
                   cmd_type(data2rtc_stage_flit[i_f]) == PKT_MODE_READ ) begin
439 
                    //it is either a data read or mode read
440 
                    sum_requested_tokens_temp    =  sum_requested_tokens_temp + num_requested_flits(data2rtc_stage_flit[i_f]);
441 
                end else if(    (cmd_type(data2rtc_stage_flit[i_f]) == PKT_WRITE) ||
442 
                                (cmd_type(data2rtc_stage_flit[i_f]) == PKT_MISC_WRITE) ) begin
443 
                    //it is not a posted transaction, so 1 token will be returned as response
444 
                    sum_requested_tokens_temp    = sum_requested_tokens_temp + 1;
445 
                end
446 
 
447 
            end
448 
        end
449 
    end
450 
 
451 
    `ifdef ASYNC_RES
452 
    always @(posedge clk or negedge res_n)  begin `else
453 
    always @(posedge clk)  begin `endif
454 
    if(!res_n) begin
455 
        sum_requested_tokens <= {7{1'b0}};
456 
    end else begin
457 
        sum_requested_tokens <= sum_requested_tokens_temp;
458 
    end
459 
    end
460 
 
461 
    //Monitor remaining tokens in the openHMC RX input buffer
462 15 juko 
    reg [LOG_MAX_RX_TOKENS-1:0] rx_tokens_av;
463 
    assign rf_rx_tokens_av = rx_tokens_av;
464 
 
465 11 juko 
    `ifdef ASYNC_RES
466 
    always @(posedge clk or negedge res_n)  begin `else
467 
    always @(posedge clk)  begin `endif
468 
    if(!res_n) begin
469 15 juko 
        rx_tokens_av     <= {LOG_MAX_RX_TOKENS{1'b0}};
470 11 juko 
    end else begin
471 15 juko 
        if(state==INIT_TX_NULL_1)begin
472 11 juko 
            //initialize token counts when HMC init is not done
473 15 juko 
            rx_tokens_av        <= rf_rx_buffer_rtc;
474 11 juko 
        end else begin
475 
            //calculate remaining tokens in RX buffers
476 15 juko 
            rx_tokens_av        <= rx_tokens_av + rx_hmc_tokens_to_return - sum_requested_tokens;
477 11 juko 
        end
478 
    end
479 
    end
480 15 juko 
 
481 11 juko 
end else begin
482 15 juko 
    assign rf_rx_tokens_av = {LOG_MAX_RX_TOKENS{1'b0}};
483 11 juko 
end
484 
endgenerate
485 
 
486 
//=======================================================================================================================
487 
//---------------------------------ALL OTHER LOGIC HERE
488 
//=======================================================================================================================
489 
`ifdef ASYNC_RES
490 
always @(posedge clk or negedge res_n)  begin `else
491 
always @(posedge clk)  begin `endif
492 15 juko 
    if(!res_n) begin
493 
 
494 
        //----Init Regs
495 
        for(i_t=0;i_t<TS1_SEQ_INC_VAL_PER_CYCLE;i_t=i_t+1) begin    //set
496 
            ts1_seq_nr_per_flit[i_t]<= i_t;
497 
        end
498 
        num_null_cycles_sent             <= {LOG_CYCLES_NULL_TO_SEND{1'b0}};
499 
 
500 
        //General
501 
        init_state                  <= INIT_TX_NULL_1;
502 
        rtc_rx_initialize           <= 1'b1;
503 
    end
504 
    else begin
505 
 
506 
        case(init_state)
507 
            //---------------------------------INIT. Refer to Initialization section in the specification
508 
 
509 
            INIT_TX_NULL_1: begin
510 
                //---init_state---
511 
                if(rf_hmc_received_init_null)begin
512 
                    init_state            <= INIT_TX_TS1;
513 
                end
514 
 
515 
            end
516 
 
517 
            INIT_TX_TS1: begin
518 
 
519 
                rtc_rx_initialize   <= 1'b0;
520 
                for(i_t=0;i_t<TS1_SEQ_INC_VAL_PER_CYCLE;i_t=i_t+1) begin
521 
                    ts1_seq_nr_per_flit[i_t]    <= ts1_seq_nr_per_flit[i_t] + TS1_SEQ_INC_VAL_PER_CYCLE;
522 
                end
523 
 
524 
                //---init_state---
525 
                if(rf_descramblers_aligned)begin
526 
                    init_state   <= INIT_TX_NULL_2;
527 
                end
528 
 
529 
            end
530 
 
531 
            INIT_TX_NULL_2: begin
532 
                //Issue at least 32 NULL FLITs before going active
533 
                if(&num_null_cycles_sent && rf_link_is_up) begin
534 
                        init_state <= INIT_DONE;
535 
                end
536 
                num_null_cycles_sent <= num_null_cycles_sent + 1;
537 
            end
538 
            default: begin
539 
            end
540 
        endcase
541 
 
542 
        if(!LXTXPS || rf_warm_reset) begin
543 
            init_state          <= INIT_TX_NULL_1;
544 
            if(rf_warm_reset)
545 
                rtc_rx_initialize   <= 1'b1;
546 
        end
547 
 
548 
    end
549 
end
550 
 
551 
`ifdef ASYNC_RES
552 
always @(posedge clk or negedge res_n)  begin `else
553 
always @(posedge clk)  begin `endif
554 
 
555 
`ifdef RESET_ALL
556 
    if(!res_n) begin
557 
        for(i_f=0;i_f<FPW;i_f=i_f+1)    data2rtc_stage_flit[i_f] <= {128{1'b0}};
558 
        for(i_f=0;i_f<FPW-1;i_f=i_f+1)  d_in_buf_flit[i_f]       <= {128{1'b0}};
559 
    end else
560 
`endif
561 
begin
562 11 juko 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
563 
        data2rtc_stage_flit[i_f]    <= {128{1'b0}};
564 
    end
565 15 juko 
 
566 
    case(state)
567 
 
568 
            INIT: begin
569 
                if(init_state == INIT_TX_TS1) begin
570 
 
571 
                    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
572 
                        data2rtc_stage_flit[i_f]    <= ts1_flit[i_f];
573 
                    end
574 
                end
575 
            end
576 
 
577 
            IDLE: begin
578 
                if(|remaining_tokens && !ram_full)begin
579 
                    data2rtc_stage_flit[0]            <= {{64{1'b0}},tret_hdr};
580 
                end
581 
            end
582 
 
583 
            TX: begin
584 
                //Choose the data source
585 
                if(d_in_use_buf) begin
586 
                    for(i_f=0;i_f<FPW-1;i_f=i_f+1) begin
587 
                        data2rtc_stage_flit[i_f+1]        <= d_in_buf_flit[i_f];
588 
                    end
589 
                end else begin
590 
                    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
591 
                        data2rtc_stage_flit[i_f]        <= d_in_flit[i_f];
592 
                    end
593 
                end
594 
 
595 
                for(i_f=0;i_f<FPW-1;i_f=i_f+1)begin
596 
                    //No matter what, fill the buffer
597 
                    d_in_buf_flit[i_f]              <= d_in_flit[i_f+1];
598 
                end
599 
            end
600 
 
601 
            HMC_RTRY: begin
602 
                for(i_f=0;i_f<FPW;i_f=i_f+1)begin //Send IRTRY start retry
603 
                    data2rtc_stage_flit[i_f]        <= {48'h0,8'b00000001,8'h00,irtry_hdr};
604 
                end
605 
            end
606 
 
607 
            LNK_RTRY: begin
608 
                    for(i_f=0;i_f<FPW;i_f=i_f+1)begin   //Send IRTRY clear error abort
609 
                        data2rtc_stage_flit[i_f]        <= {48'h0,8'b00000010,8'h00,irtry_hdr};
610 
                    end
611 
            end
612 
    endcase
613 
end
614 
 
615 
if(!res_n) begin
616 11 juko 
    data2rtc_stage_flit_is_hdr      <= {FPW{1'b0}};
617 
    data2rtc_stage_flit_is_tail     <= {FPW{1'b0}};
618 
    data2rtc_stage_flit_is_valid    <= {FPW{1'b0}};
619 
    data2rtc_stage_is_flow          <= 1'b0;
620 
 
621 
    data2rtc_stage_force_tx_retry   <= 1'b0;
622 
    d_in_shift_out                  <= 1'b0;
623 
 
624 
    //----Reset the input buffer reg
625 15 juko 
    d_in_buf_flit_is_hdr            <= {FPW-1{1'b0}};
626 
    d_in_buf_flit_is_valid          <= {FPW-1{1'b0}};
627 11 juko 
    d_in_use_buf                    <= 1'b0;
628 
 
629 
    //General
630 15 juko 
    state                           <= INIT;
631 11 juko 
 
632 
    //Token Flow Control
633 15 juko 
    remaining_tokens                <= {LOG_MAX_RX_TOKENS{1'b0}};
634 11 juko 
    rtc_return_val                  <= {5{1'b0}};
635 
    rtc_return                      <= 1'b0;
636 
 
637 
    //Retry
638 15 juko 
    irtry_start_retry_cnt       <= {5{1'b0}};
639 
    irtry_clear_error_cnt       <= {5{1'b0}};
640 11 juko 
 
641 
    //HMC Control
642 15 juko 
    LXRXPS                          <= 1'b1;
643 11 juko 
 
644 
    //Flow Control
645 
    tx_link_retry_request           <= 1'b0;
646 
 
647 
end
648 
else begin
649 
//====================================================================
650 
//---------------------------------INIT
651 
//====================================================================
652 
    //Reset control signals
653 15 juko 
    d_in_shift_out              <= 1'b0;
654 
    irtry_start_retry_cnt       <= {5{1'b0}};
655 
    irtry_clear_error_cnt       <= {5{1'b0}};
656 11 juko 
 
657 
    //HMC Control
658 15 juko 
    LXRXPS                      <= 1'b1;
659 11 juko 
 
660 
    if(rx_force_tx_retry)begin
661 
        tx_link_retry_request   <= 1'b1;
662 
    end
663 
 
664 
    //RTC
665 
    rtc_return       <= 1'b0;
666 
    //Initialize rtc to be transmitted after reset and warm reset
667 
    if(rtc_rx_initialize) begin
668 
        remaining_tokens <= rf_rx_buffer_rtc;
669 
    end else begin
670 
        remaining_tokens <= remaining_tokens + rx_hmc_tokens_to_return + rx_hmc_poisoned_tokens_to_return;
671 
    end
672 
 
673 
    //Reset information bits
674 
    data2rtc_stage_flit_is_hdr     <= {FPW{1'b0}};
675 
    data2rtc_stage_flit_is_tail    <= {FPW{1'b0}};
676 
    data2rtc_stage_flit_is_valid   <= {FPW{1'b0}};
677 
    data2rtc_stage_is_flow         <= 1'b0;
678 
    data2rtc_stage_force_tx_retry  <= 1'b0;
679 
 
680 15 juko 
    rtc_return_val      <= outstanding_tokens_to_return;
681 11 juko 
 
682 
    case(state)
683 
 
684 
//====================================================================
685 
//---------------------------------Normal operation (including init TRETs)
686 
//====================================================================
687 
// Some branches to other states may be removed in HMC_RTRY for instance.
688 
// Saves logic if an additional cycle in IDLE is acceptable
689 
 
690 15 juko 
        INIT: begin
691 
            if(init_state==INIT_DONE) state <= IDLE;
692 
        end
693 
 
694 11 juko 
        IDLE: begin
695 
        //Issue NULL Flits if there's nothing else to do
696 
 
697 
            //SEND TRET PACKET even if there are no tokens available
698 15 juko 
            if(|remaining_tokens && !ram_full)begin
699 11 juko 
                data2rtc_stage_flit_is_hdr[0]     <= 1'b1;
700 
                data2rtc_stage_flit_is_tail[0]    <= 1'b1;
701 
                data2rtc_stage_flit_is_valid[0]   <= 1'b1;
702 
 
703 
                remaining_tokens    <= remaining_tokens + rx_hmc_tokens_to_return + rx_hmc_poisoned_tokens_to_return - outstanding_tokens_to_return;
704 
                rtc_return          <= 1'b1;
705 
            end
706 
 
707 15 juko 
            // //---State---
708 11 juko 
            if(force_hmc_retry) begin
709 
                state <= HMC_RTRY;
710 
            end else if(tx_link_retry_request) begin
711 
                state <= LNK_RTRY;
712 
            end else if(rf_hmc_sleep_requested) begin
713 
                state <= SLEEP;
714 
            end else if(!d_in_empty && !ram_full && hmc_tokens_av) begin
715 
                state           <= TX;
716 
                d_in_shift_out  <= ~d_in_use_buf;
717 
            end
718 
 
719 
        end
720 
 
721 
        TX: begin
722 
        //Get and transmit data
723 
 
724 
            //First set control signals
725 
            d_in_use_buf    <= 1'b0;
726 
            d_in_shift_out  <= 1'b1;
727 
 
728 
            //Fill the buffer
729 15 juko 
            d_in_buf_flit_is_hdr         <= d_in_flit_is_hdr[FPW-1:1];
730 
            d_in_buf_flit_is_valid       <= d_in_flit_is_valid[FPW-1:1];
731 11 juko 
 
732 
            //If there is data buffered - use it
733 15 juko 
            data2rtc_stage_flit_is_hdr   <= d_in_use_buf ? {d_in_buf_flit_is_hdr,1'b0}   : d_in_flit_is_hdr;
734 
            data2rtc_stage_flit_is_tail  <= d_in_use_buf ? {FPW{1'b0}}                   : d_in_flit_is_tail;
735 
            data2rtc_stage_flit_is_valid <= d_in_use_buf ? {d_in_buf_flit_is_valid,1'b0} : d_in_flit_is_valid;
736 11 juko 
 
737 
            //Set RTC to be added in the next step
738 15 juko 
            if( |remaining_tokens &&
739 
                (!d_in_use_buf && |d_in_flit_is_tail)
740 11 juko 
            ) begin
741 
                remaining_tokens    <= remaining_tokens + rx_hmc_tokens_to_return + rx_hmc_poisoned_tokens_to_return - outstanding_tokens_to_return;
742 
                rtc_return          <= 1'b1;
743 
            end
744 
 
745 
            //Exit state if seen a tail and exit condition occured
746 15 juko 
            if(     ((!d_in_use_buf && |d_in_flit_is_tail)) &&
747 11 juko 
                    (force_hmc_retry || ram_full || tx_link_retry_request || !hmc_tokens_av || d_in_a_empty)) begin
748 
 
749 
                d_in_shift_out  <= 1'b0;
750 
 
751 
 
752 15 juko 
                case ({force_hmc_retry,tx_link_retry_request})
753 
                    2'b00: state    <= IDLE;
754 
                    2'b01: state    <= LNK_RTRY;
755 
                    default: state  <= HMC_RTRY;
756 
                endcase
757 
 
758 11 juko 
                for(i_f=0;i_f<FPW;i_f=i_f+1)begin
759 15 juko 
                    if(!d_in_use_buf && d_in_flit_is_tail[i_f])begin
760 11 juko 
                        data2rtc_stage_flit_is_valid    <= {FPW{1'b1}} >> {FPW-1-i_f};
761 
                    end
762 
                end
763 
 
764 15 juko 
                for(i_f=1;i_f<FPW;i_f=i_f+1)begin
765 
                    if(d_in_flit_is_tail[i_f])begin
766 
                        d_in_buf_flit_is_hdr            <= d_in_flit_is_hdr[FPW-1:1] & ({FPW-1{1'b1}} << i_f);
767 
                        d_in_buf_flit_is_valid          <= d_in_flit_is_valid[FPW-1:1] & ({FPW-1{1'b1}} << i_f);
768 
                    end
769 
                end
770 
 
771 11 juko 
                //Use buf next time TX state is entered if there is a packet pending
772 15 juko 
                if(!d_in_use_buf && (d_in_flit_is_hdr[FPW-1:1] > d_in_flit_is_tail[FPW-1:1]))begin
773 11 juko 
                    d_in_use_buf    <= 1'b1;
774 
                end
775 
            end
776 
        end
777 
 
778 
    //---------------------------------An error in RX path occured - send irtry start packets
779 
        HMC_RTRY: begin
780 
 
781 
            data2rtc_stage_is_flow          <= 1'b1;
782 
 
783 
            irtry_start_retry_cnt               <= irtry_start_retry_cnt + FPW;
784 
 
785 
            if(irtry_start_retry_cnt+FPW >= rf_irtry_to_send)begin
786 15 juko 
                irtry_start_retry_cnt           <= {5{1'b0}};
787 
                state <= IDLE;
788 11 juko 
            end
789 
 
790 
        end
791 
 
792 
 
793 
    //---------------------------------HMC sent start retry packets -
794 
    //                                 re-send all valid packets in RAM after sending clear error packets
795 
        LNK_RTRY: begin
796 
 
797 15 juko 
            if(!tx_retry_ongoing && (tx_link_retry_request || |irtry_clear_error_cnt)) begin
798 
 
799 11 juko 
                data2rtc_stage_is_flow          <= 1'b1;
800 
 
801 
                if(irtry_clear_error_cnt+FPW >= rf_irtry_to_send)begin
802 15 juko 
                    irtry_clear_error_cnt         <= {5{1'b0}};
803 11 juko 
                    data2rtc_stage_force_tx_retry <= 1'b1;
804 
                end else begin
805 
                    irtry_clear_error_cnt   <= irtry_clear_error_cnt + FPW;
806 
                end
807 
            end
808 
 
809 
            if(tx_retry_finished && !tx_link_retry_request) begin
810 15 juko 
                state <= IDLE;
811 11 juko 
            end
812 
 
813 15 juko 
            if(!tx_retry_ongoing && !rx_force_tx_retry) begin
814 11 juko 
                tx_link_retry_request   <= 1'b0;
815 
            end
816 
        end
817 
 
818 
    //---------------------------------Power State Management
819 
        SLEEP: begin
820 
 
821 15 juko 
            if(rf_hmc_sleep_requested) begin
822 
                LXRXPS          <= 1'b0;
823 
            end else begin
824 
                state           <= WAIT_FOR_HMC;
825 11 juko 
            end
826 
 
827 
        end
828 
 
829 
        WAIT_FOR_HMC: begin
830 
 
831 15 juko 
            if(LXTXPS) begin
832 
                state           <= INIT;
833 11 juko 
            end
834 
 
835 
        end
836 
 
837 
    endcase
838 
 
839 15 juko 
    //Warm Reset
840 
    if(rf_warm_reset) begin
841 
        //in case of a warm reset request, continue at INIT_TX_NULL_2 sequence and intialize tokens to be returned
842 
        state       <= INIT;
843 11 juko 
    end
844 15 juko 
 
845 11 juko 
end
846 
end
847 
 
848 
//====================================================================
849 
//---------------------------------HMC input buffer Token Handling
850 
//====================================================================
851 
//Count the tokens that were used and make sure the HMC has enough tokens in its input buffer left
852 
//This always block remains combinational to save one cycle
853 
always @(*)  begin
854 
 
855 15 juko 
    num_flits_transmitted = {LOG_FPW+1{1'b0}};
856 
    num_flits_in_buf      = {LOG_FPW{1'b0}};
857 11 juko 
 
858 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
859 
        if(d_in_flit_is_valid[i_f] && d_in_shift_out) begin
860 15 juko 
            num_flits_transmitted   = num_flits_transmitted + 1;
861 11 juko 
        end
862 15 juko 
    end
863 
    for(i_f=0;i_f<FPW-1;i_f=i_f+1)begin
864 11 juko 
        if(d_in_buf_flit_is_valid[i_f] && d_in_use_buf) begin
865 15 juko 
            num_flits_in_buf = num_flits_in_buf + 1;
866 11 juko 
        end
867 
    end
868 
end
869 
 
870 
`ifdef ASYNC_RES
871 
always @(posedge clk or negedge res_n)  begin `else
872 
always @(posedge clk)  begin `endif
873 
if(!res_n) begin
874 15 juko 
    rf_hmc_tokens_av    <= {LOG_MAX_HMC_TOKENS{1'b0}};
875 11 juko 
end else begin
876 15 juko 
    rf_hmc_tokens_av    <= rf_hmc_tokens_av + rx_returned_tokens - num_flits_transmitted;
877 11 juko 
end
878 
end
879 
 
880 
//====================================================================
881 15 juko 
//---------------------------------Counter in the RF, currently only data transactions are counted
882 11 juko 
//====================================================================
883 
always @(*) begin
884 
 
885 
    rf_sent_p_comb   = {LOG_FPW+1{1'b0}};
886 
    rf_sent_np_comb  = {LOG_FPW+1{1'b0}};
887 
    rf_sent_r_comb   = {LOG_FPW+1{1'b0}};
888 
 
889 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
890 
        if(data2seq_frp_stage_flit_is_hdr[i_f])begin
891 
        //split into independent cases to avoid dependencies
892 
        //Instead of comparing the entire cmd field, try to reduce logic effort
893 
 
894 
            //All non-posted types have either bit 3 or 4 in the cmd set:
895 
            if( data2seq_frp_stage_flit[i_f][3] ^ data2seq_frp_stage_flit[i_f][4] ) begin
896 
                rf_sent_np_comb = rf_sent_np_comb + {{LOG_FPW{1'b0}},1'b1};
897 
            end
898 
 
899 
            //Only reads have bit 4 and 5 set:
900 
            if(data2seq_frp_stage_flit[i_f][4] && data2seq_frp_stage_flit[i_f][5] ) begin
901 
                rf_sent_r_comb = rf_sent_r_comb + {{LOG_FPW{1'b0}},1'b1};
902 
            end
903 
 
904 
            //Otherwise it's a posted write
905 
            if(cmd_type(data2seq_frp_stage_flit[i_f])==PKT_P_WRITE)begin
906 
                rf_sent_p_comb = rf_sent_p_comb + {{LOG_FPW{1'b0}},1'b1};
907 
            end
908 
 
909 
        end
910 
    end
911 
end
912 
 
913 
 
914 15 juko 
 
915 
`ifdef XILINX
916 
    openhmc_counter48_wrapper_xilinx #(
917 
        .INC_SIZE(LOG_FPW+1),
918 
        .PIPELINED(XIL_CNT_PIPELINED)
919 
    ) cnt_sent_p (
920 
        .clk(clk),
921 
        .res_n(res_n),
922 
        .inc_value(rf_sent_p_comb),
923 
        .value(rf_sent_p)
924 
    );
925 
 
926 
    openhmc_counter48_wrapper_xilinx #(
927 
        .INC_SIZE(LOG_FPW+1),
928 
        .PIPELINED(XIL_CNT_PIPELINED)
929 
    ) cnt_sent_np (
930 
        .clk(clk),
931 
        .res_n(res_n),
932 
        .inc_value(rf_sent_np_comb),
933 
        .value(rf_sent_np)
934 
    );
935 
 
936 
    openhmc_counter48_wrapper_xilinx #(
937 
        .INC_SIZE(LOG_FPW+1),
938 
        .PIPELINED(XIL_CNT_PIPELINED)
939 
    ) cnt_sent_r (
940 
        .clk(clk),
941 
        .res_n(res_n),
942 
        .inc_value(rf_sent_r_comb),
943 
        .value(rf_sent_r)
944 
    );
945 
`else
946 
    reg  [RF_COUNTER_SIZE-1:0]    rf_sent_p_temp;
947 
    reg  [RF_COUNTER_SIZE-1:0]    rf_sent_np_temp;
948 
    reg  [RF_COUNTER_SIZE-1:0]    rf_sent_r_temp;
949 
    assign rf_sent_p            = rf_sent_p_temp;
950 
    assign rf_sent_np           = rf_sent_np_temp;
951 
    assign rf_sent_r            = rf_sent_r_temp;
952 
 
953 
    `ifdef ASYNC_RES
954 
    always @(posedge clk or negedge res_n)  begin `else
955 
    always @(posedge clk)  begin `endif
956 
    if(!res_n) begin
957 
        rf_sent_p_temp   <= {RF_COUNTER_SIZE{1'b0}};
958 
        rf_sent_np_temp  <= {RF_COUNTER_SIZE{1'b0}};
959 
        rf_sent_r_temp   <= {RF_COUNTER_SIZE{1'b0}};
960 
    end else begin
961 
        rf_sent_p_temp   <= rf_sent_p_temp  + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_sent_p_comb};
962 
        rf_sent_np_temp  <= rf_sent_np_temp + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_sent_np_comb};
963 
        rf_sent_r_temp   <= rf_sent_r_temp  + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_sent_r_comb};
964 
    end
965 
    end
966 
`endif
967 
 
968 11 juko 
//====================================================================
969 
//---------------------------------HMC Retry Logic
970 
//====================================================================
971 
//Monitor RX error abort mode - if the timer expires send another series of start retry packets
972 
`ifdef ASYNC_RES
973 
always @(posedge clk or negedge res_n)  begin `else
974 
always @(posedge clk)  begin `endif
975 
 
976 
if(!res_n) begin
977 
    error_abort_mode_clr_cnt       <= {8{1'b0}};
978 
    force_hmc_retry                <= 1'b0;
979 
    rf_error_abort_not_cleared     <= 1'b0;
980 
end else begin
981 
 
982 
    rf_error_abort_not_cleared     <= 1'b0;
983 
 
984 
    if(rx_error_abort_mode)begin
985 15 juko 
        error_abort_mode_clr_cnt   <= error_abort_mode_clr_cnt + 1; //decrement counter
986 11 juko 
    end
987 
 
988 
    if(rx_error_abort_mode_cleared) begin
989 
        error_abort_mode_clr_cnt   <= {8{1'b0}};
990 
    end
991 
 
992 15 juko 
    if(&error_abort_mode_clr_cnt) begin
993 
        rf_error_abort_not_cleared  <= 1'b1;
994 
    end
995 
 
996 
    if((rx_error_abort_mode && state!=HMC_RTRY && |error_abort_mode_clr_cnt==1'b0) || (&error_abort_mode_clr_cnt))begin
997 11 juko 
        force_hmc_retry             <= 1'b1;
998 15 juko 
 
999 11 juko 
    end else begin
1000 
        if(state==HMC_RTRY)begin
1001 
            force_hmc_retry     <= 1'b0;
1002 
        end
1003 
    end
1004 
 
1005 
end
1006 
end
1007 
 
1008 
//====================================================================
1009 
//---------------------------------RTC Stage
1010 
//====================================================================
1011 15 juko 
generate
1012 
if(OPEN_RSP_MODE==0) begin : RTC_stage
1013 
    reg  [4:0]      data2seq_frp_stage_flit_rtc     [FPW-1:0];
1014 
    reg             rtc_return_sent;
1015 11 juko 
 
1016 15 juko 
    always @(*)  begin
1017 
        rtc_return_sent = 0;
1018 11 juko 
 
1019 15 juko 
        for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1020 
            if(data2rtc_stage_flit_is_tail[i_f] && !rtc_return_sent && rtc_return) begin
1021 
                //Return outstanding tokens, but only once per cycle
1022 
                data2seq_frp_stage_flit_rtc[i_f] = rtc_return_val;
1023 
                rtc_return_sent                  = 1'b1;
1024 
            end else begin
1025 
                data2seq_frp_stage_flit_rtc[i_f] = 5'h00;
1026 
            end
1027 11 juko 
        end
1028 
    end
1029 
 
1030 15 juko 
    `ifdef ASYNC_RES
1031 
    always @(posedge clk or negedge res_n)  begin `else
1032 
    always @(posedge clk)  begin `endif
1033 11 juko 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1034 15 juko 
        `ifdef ASYNC_RES
1035 
        if(!res_n)
1036 
            data2seq_frp_stage_flit[i_f]  <= {128{1'b0}};
1037 
        else
1038 
        `endif
1039 
        begin
1040 
            data2seq_frp_stage_flit[i_f]        <= data2rtc_stage_flit[i_f];
1041 
            if(data2rtc_stage_flit_is_tail[i_f]) begin
1042 
                data2seq_frp_stage_flit[i_f][64+31:64+27]   <= data2seq_frp_stage_flit_rtc[i_f];
1043 
            end
1044 
        end
1045 11 juko 
    end
1046 15 juko 
    end
1047 11 juko 
end else begin
1048 15 juko 
 
1049 
    `ifdef ASYNC_RES
1050 
    always @(posedge clk or negedge res_n)  begin `else
1051 
    always @(posedge clk)  begin `endif
1052 
        for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1053 
            `ifdef ASYNC_RES
1054 
            if(!res_n)
1055 
                data2seq_frp_stage_flit[i_f]  <= {128{1'b0}};
1056 
            else
1057 
            `endif
1058 
            begin
1059 
                data2seq_frp_stage_flit[i_f]  <= data2rtc_stage_flit[i_f];
1060 
            end
1061 
        end
1062 11 juko 
    end
1063 
end
1064 15 juko 
endgenerate
1065 11 juko 
 
1066 15 juko 
    `ifdef ASYNC_RES
1067 
    always @(posedge clk or negedge res_n)  begin `else
1068 
    always @(posedge clk)  begin `endif
1069 
    `ifdef RESET_ALL
1070 
        if(!res_n) begin
1071 
            data2seq_frp_stage_flit_is_hdr    <= {FPW{1'b0}};
1072 
            data2seq_frp_stage_flit_is_tail   <= {FPW{1'b0}};
1073 
            data2seq_frp_stage_flit_is_valid  <= {FPW{1'b0}};
1074 
            data2seq_frp_stage_is_flow        <= 1'b0;
1075 
            data2seq_frp_stage_force_tx_retry <= 1'b0;
1076 
        end else
1077 
    `endif
1078 
    begin
1079 
        data2seq_frp_stage_flit_is_hdr    <= data2rtc_stage_flit_is_hdr & data2rtc_stage_flit_is_valid;
1080 
        data2seq_frp_stage_flit_is_tail   <= data2rtc_stage_flit_is_tail & data2rtc_stage_flit_is_valid;
1081 
        data2seq_frp_stage_flit_is_valid  <= data2rtc_stage_flit_is_valid;
1082 
        data2seq_frp_stage_is_flow        <= data2rtc_stage_is_flow;
1083 
        data2seq_frp_stage_force_tx_retry <= data2rtc_stage_force_tx_retry;
1084 
    end
1085 
    end
1086 
 
1087 11 juko 
//====================================================================
1088 
//---------------------------------Seqnum and FRP Stage
1089 
//====================================================================
1090 15 juko 
 
1091 11 juko 
always @(*)  begin
1092 15 juko 
    tx_seqnum_inc  = {LOG_FPW{1'b0}};
1093 11 juko 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1094 15 juko 
        tx_seqnum_temp[i_f] = 0;
1095 
        if(data2seq_frp_stage_flit_is_tail[i_f])begin
1096 
            tx_seqnum_inc       = tx_seqnum_inc + 1;
1097 
            tx_seqnum_temp[i_f] = tx_seqnum + tx_seqnum_inc;
1098 11 juko 
        end
1099 
    end
1100 
 
1101 15 juko 
    target_temp[0] = next_target;
1102 11 juko 
 
1103 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1104 15 juko 
        if(data2rtc_stage_flit_is_valid[i_f]) begin
1105 
             target_temp[i_f+1] = target_temp[i_f] + 1;
1106 
             if(target_temp[i_f+1]==FPW)
1107 
                target_temp[i_f+1]=0;
1108 
        end else begin
1109 
            target_temp[i_f+1] = target_temp[i_f];
1110 11 juko 
        end
1111 
    end
1112 
end
1113 
 
1114 
`ifdef ASYNC_RES
1115 
always @(posedge clk or negedge res_n)  begin `else
1116 
always @(posedge clk)  begin `endif
1117 
if(!res_n) begin
1118 15 juko 
    //Reset the target RAM location and seqnum
1119 11 juko 
    tx_seqnum   <= {LOG_FPW{1'b0}};
1120 15 juko 
    next_target <= {LOG_FPW{1'b0}};
1121 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1122 
        target[i_f]   <= {FPW{1'b0}};
1123 
    end
1124 11 juko 
end else begin
1125 15 juko 
    tx_seqnum   <= tx_seqnum  + tx_seqnum_inc;
1126 
    if(!data2rtc_stage_is_flow) begin
1127 
        for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1128 
            target[i_f]             <= target_temp[i_f];
1129 
        end
1130 
        next_target <= target_temp[FPW];
1131 
    end
1132 11 juko 
end
1133 
end
1134 
 
1135 
//Constant propagation, no need for reset condition
1136 
`ifdef ASYNC_RES
1137 
always @(posedge clk or negedge res_n)  begin `else
1138 
always @(posedge clk)  begin `endif
1139 15 juko 
 
1140 11 juko 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1141 15 juko 
        `ifdef RESET_ALL
1142 
        if(!res_n) data2ram_flit[i_f] <= {128{1'b0}};
1143 
        else
1144 
        `endif
1145 
        begin
1146 
            data2ram_flit[i_f]      <= data2seq_frp_stage_flit[i_f];
1147 
 
1148 
            if(data2seq_frp_stage_flit_is_tail[i_f]) begin
1149 
                data2ram_flit[i_f][64+15+3:64+8] <= {tx_seqnum_temp[i_f],tx_frp_adr[target[i_f]],target[i_f]};
1150 
            end
1151 
        end
1152 11 juko 
    end
1153 15 juko 
 
1154 
    data2ram_flit_is_hdr    <= data2seq_frp_stage_flit_is_hdr | {FPW{data2seq_frp_stage_is_flow}};
1155 11 juko 
    data2ram_flit_is_tail   <= data2seq_frp_stage_flit_is_tail;
1156 15 juko 
    data2ram_flit_is_valid  <= data2seq_frp_stage_flit_is_valid | {FPW{data2seq_frp_stage_is_flow}};
1157 11 juko 
    data2ram_force_tx_retry <= data2seq_frp_stage_force_tx_retry;
1158 15 juko 
if(!res_n) begin
1159 
    `ifdef RESET_ALL
1160 
        data2ram_flit_is_hdr    <= {FPW{1'b0}};
1161 
        data2ram_flit_is_tail   <= {FPW{1'b0}};
1162 
        data2ram_flit_is_valid  <= {FPW{1'b0}};
1163 
        data2ram_force_tx_retry <= 1'b0;
1164 
    `endif
1165 
 
1166 11 juko 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1167 15 juko 
        tx_frp_adr[i_f]     <= {RAM_ADDR_SIZE{1'b0}};
1168 11 juko 
    end
1169 15 juko 
end else begin
1170 
 
1171 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1172 
        if(data2seq_frp_stage_flit_is_valid[i_f]) begin
1173 
            tx_frp_adr[target[i_f]] <= tx_frp_adr[target[i_f]] + 1;
1174 
        end
1175 
    end
1176 
 
1177 11 juko 
end
1178 
end
1179 
 
1180 
//====================================================================
1181 
//---------------------------------Fill RAM
1182 
//====================================================================
1183 
//-- Always assign FLITs to RAM write register
1184 
`ifdef ASYNC_RES
1185 
always @(posedge clk or negedge res_n)  begin `else
1186 
always @(posedge clk)  begin `endif
1187 15 juko 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1188 
        ram_w_data[target[i_f]] <= { data2seq_frp_stage_flit_is_valid[i_f],
1189 
                                     data2seq_frp_stage_flit_is_tail[i_f],
1190 
                                     data2seq_frp_stage_flit_is_hdr[i_f],
1191 
                                     data2seq_frp_stage_flit[i_f]
1192 
                                  };
1193 11 juko 
 
1194 15 juko 
        if(data2seq_frp_stage_flit_is_tail[i_f])begin
1195 
            ram_w_data[target[i_f]][64+15+3:64+8] <= {tx_seqnum_temp[i_f],tx_frp_adr[target[i_f]],target[i_f]};
1196 11 juko 
        end
1197 15 juko 
    end
1198 11 juko 
 
1199 15 juko 
    if(!res_n) begin
1200 
        ram_w_en    <= {FPW{1'b0}};
1201 
    end else begin
1202 
        for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1203 
            if(data2seq_frp_stage_flit_is_valid[i_f]) begin
1204 
                ram_w_en[target[i_f]]    <= 1'b1;
1205 
            end else begin
1206 
                ram_w_en[target[i_f]]    <= 1'b0;
1207 
            end
1208 
        end
1209 11 juko 
    end
1210 
end
1211 
 
1212 
//====================================================================
1213 
//---------------------------------Select Data Source: Valid sources are the Retry Buffers or regular data stream.
1214 
//====================================================================
1215 
`ifdef ASYNC_RES
1216 
always @(posedge clk or negedge res_n)  begin `else
1217 
always @(posedge clk)  begin `endif
1218 15 juko 
 
1219 
    for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1220 
    `ifdef RESET_ALL
1221 
    if(!res_n) data2rrp_stage_flit[i_f] <= {128{1'b0}};
1222 
    else
1223 
    `endif
1224 
        begin
1225 
 
1226 
            if(tx_retry_ongoing) begin
1227 
                //-- If there's a TX retry ongoing increment read address until it equals the write address
1228 
                data2rrp_stage_flit[i_f]    <= ram_r_data[i_f][127:0];
1229 
            end else begin
1230 
                //Propagate data from normal packet stream
1231 
                data2rrp_stage_flit[i_f]    <= data2ram_flit[i_f];
1232 
            end
1233 
        end
1234 
    end
1235 
 
1236 11 juko 
if(!res_n) begin
1237 
    //Reset control signals
1238 
    tx_retry_finished   <= 1'b0;
1239 
    tx_retry_ongoing    <= 1'b0;
1240 
    rf_cnt_retry        <= 1'b0;
1241 
 
1242 
    //Ram
1243 
    ram_r_en            <= 1'b0;
1244 
    ram_r_addr_temp     <= {RAM_ADDR_SIZE{1'b0}};
1245 15 juko 
    ram_r_mask          <= {FPW{1'b0}};
1246 11 juko 
 
1247 
    //Data propagation
1248 
    data2rrp_stage_flit_is_hdr      <= {FPW{1'b0}};
1249 
    data2rrp_stage_flit_is_tail     <= {FPW{1'b0}};
1250 
    data2rrp_stage_flit_is_valid    <= {FPW{1'b0}};
1251 
 
1252 
end else begin
1253 
    tx_retry_finished   <= 1'b0;
1254 15 juko 
    tx_retry_ongoing    <= 1'b0;
1255 11 juko 
    rf_cnt_retry        <= 1'b0;
1256 
 
1257 15 juko 
    ram_r_en            <= 1'b0;
1258 
    ram_r_addr_temp     <= {RAM_ADDR_SIZE{1'b0}};
1259 
    ram_r_mask          <= {FPW{1'b0}};
1260 11 juko 
 
1261 
    //if there is a retry request coming set the ram address to last received rrp
1262 15 juko 
    if(data2seq_frp_stage_force_tx_retry) begin
1263 11 juko 
        ram_r_en            <= 1'b1;
1264 15 juko 
        ram_r_addr_temp     <= ram_r_addr+1;
1265 11 juko 
    end
1266 
 
1267 
    if(!tx_retry_ongoing) begin
1268 
 
1269 
        data2rrp_stage_flit_is_hdr      <= data2ram_flit_is_hdr;
1270 
        data2rrp_stage_flit_is_tail     <= data2ram_flit_is_tail;
1271 
        data2rrp_stage_flit_is_valid    <= data2ram_flit_is_valid;
1272 
 
1273 
        //Switch to retry if requested
1274 
        if(data2ram_force_tx_retry) begin
1275 
 
1276 15 juko 
            if(ram_r_addr_temp == ram_w_addr_next) begin //if the next address is the write address -> no retry.
1277 11 juko 
                tx_retry_finished   <= 1'b1;
1278 
            end else begin
1279 15 juko 
                ram_r_mask          <= ({FPW{1'b1}}) << (rx_rrp[8-RAM_ADDR_SIZE-1:0]);
1280 
                ram_r_addr_temp     <= ram_r_addr_temp+1;
1281 
                ram_r_en            <= 1'b1;
1282 11 juko 
                rf_cnt_retry        <= 1'b1;
1283 
                tx_retry_ongoing    <= 1'b1;
1284 
            end
1285 
        end
1286 
    end else begin
1287 
        //-- If there's a TX retry ongoing increment read addr until it equals the write address
1288 
 
1289 
        ram_r_mask          <= {FPW{1'b1}};
1290 
 
1291 
        for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1292 15 juko 
                data2rrp_stage_flit_is_hdr[i_f]     <= ram_r_mask[i_f] ? ram_r_data[i_f][128]   :1'b0 ;
1293 
                data2rrp_stage_flit_is_tail[i_f]    <= ram_r_mask[i_f] ? ram_r_data[i_f][128+1] :1'b0 ;
1294 
                data2rrp_stage_flit_is_valid[i_f]   <= ram_r_mask[i_f] ? ram_r_data[i_f][128+2] :1'b0 ;
1295 
        end
1296 11 juko 
 
1297 
        //if the next address is the write address -> retry finished
1298 15 juko 
        if(ram_r_addr_temp == ram_w_addr_next) begin
1299 
            for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1300 
                if(i_f >= target[0] && !(tx_frp_adr[0]==tx_frp_adr[FPW-1]))begin
1301 
                    data2rrp_stage_flit_is_hdr[i_f]     <= 1'b0;
1302 
                    data2rrp_stage_flit_is_tail[i_f]    <= 1'b0;
1303 
                    data2rrp_stage_flit_is_valid[i_f]   <= 1'b0;
1304 
                end
1305 
            end
1306 11 juko 
            tx_retry_finished   <= 1'b1;
1307 
        end else begin
1308 15 juko 
            ram_r_addr_temp     <= ram_r_addr_temp + 1;
1309 
            tx_retry_ongoing    <= 1'b1;
1310 
            ram_r_en            <= 1'b1;
1311 11 juko 
        end
1312 
 
1313 
    end
1314 
 
1315 
end
1316 
end
1317 
 
1318 
//====================================================================
1319 
//---------------------------------Add RRP
1320 
//====================================================================
1321 
`ifdef ASYNC_RES
1322 
always @(posedge clk or negedge res_n)  begin `else
1323 
always @(posedge clk)  begin `endif
1324 15 juko 
 
1325 
    `ifdef RESET_ALL
1326 
        for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1327 
            data2crc_flit[i_f] <= {128{1'b0}};
1328 
        end
1329 
    `endif
1330 
    begin
1331 
        for(i_f=0;i_f<FPW;i_f=i_f+1)begin
1332 
            data2crc_flit[i_f]  <= (data2rrp_stage_flit_is_valid[i_f] || !init_state[1]) ? data2rrp_stage_flit[i_f] : {128{1'b0}};
1333 
 
1334 
            //Add the RRP
1335 
            if(data2rrp_stage_flit_is_tail[i_f] || (data2rrp_stage_flit_is_hdr[i_f] && is_req_flow(data2rrp_stage_flit[i_f])))begin
1336 
                data2crc_flit[i_f][64+7:64]     <= rx_hmc_frp;
1337 
            end
1338 
 
1339 
            //Increment the FRP by 1, It points to the next possible FLIT position -> retry will start there
1340 
            if(data2rrp_stage_flit_is_tail[i_f])begin
1341 
                data2crc_flit[i_f][64+15:64+8]  <= data2rrp_stage_flit[i_f][64+15:64+8] + 1;
1342 
            end
1343 
 
1344 
        end
1345 
        `ifdef SIMULATION
1346 
            if((last_transmitted_rx_hmc_frp != rx_hmc_frp) && !data2rrp_stage_flit_is_valid[0])begin `else
1347 
            if(!data2rrp_stage_flit_is_valid[0] && send_prets)begin `endif
1348 
                data2crc_flit[0][63:0]          <= pret_hdr;
1349 
                data2crc_flit[0][64+7:64]       <= rx_hmc_frp;
1350 
            end
1351 
    end
1352 
 
1353 11 juko 
if(!res_n) begin
1354 15 juko 
    `ifdef SIMULATION
1355 
        //----Reset control signals
1356 
        last_transmitted_rx_hmc_frp <= {8{1'b0}};
1357 
    `else
1358 
        send_prets <= 1'b0;
1359 
    `endif
1360 11 juko 
 
1361 
    //----Data
1362 
    data2crc_flit_is_hdr    <= {FPW{1'b0}};
1363 
    data2crc_flit_is_tail   <= {FPW{1'b0}};
1364 
 
1365 
end else begin
1366 
 
1367 
    //Propagate signals
1368 
    data2crc_flit_is_hdr  <= data2rrp_stage_flit_is_hdr;
1369 15 juko 
    data2crc_flit_is_tail <= data2rrp_stage_flit_is_tail |  ((data2rrp_stage_flit_is_hdr[FPW-1] && cmd(data2rrp_stage_flit[FPW-1])==CMD_IRTRY) ? {FPW{1'b1}} : {FPW{1'b0}}) ;
1370 11 juko 
 
1371 15 juko 
    `ifdef SIMULATION
1372 
        //If there is a tail, remember the last transmitted RRP. Otherwise generate PRET if there is a new RRP
1373 
        if(|data2rrp_stage_flit_is_tail)begin
1374 
            last_transmitted_rx_hmc_frp     <= rx_hmc_frp;
1375 
        end
1376 
        if((last_transmitted_rx_hmc_frp != rx_hmc_frp) && !data2rrp_stage_flit_is_valid[0])begin
1377 
            data2crc_flit_is_hdr[0]         <= 1'b1;
1378 
            data2crc_flit_is_tail[0]        <= 1'b1;
1379 
            last_transmitted_rx_hmc_frp     <= rx_hmc_frp;
1380 11 juko 
        end
1381 15 juko 
    `else
1382 11 juko 
 
1383 15 juko 
        if(|data2crc_flit_is_hdr) send_prets <= 1'b1;
1384 
        if(rf_hmc_sleep_requested || rf_warm_reset) send_prets <= 1'b0;
1385 
 
1386 
        if(!data2rrp_stage_flit_is_valid[0] && send_prets)begin
1387 
            data2crc_flit_is_hdr[0]         <= 1'b1;
1388 
            data2crc_flit_is_tail[0]        <= 1'b1;
1389 
        end
1390 
    `endif
1391 11 juko 
 
1392 
end
1393 
end
1394 
 
1395 
//=====================================================================================================
1396 
//-----------------------------------------------------------------------------------------------------
1397 
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
1398 
//-----------------------------------------------------------------------------------------------------
1399 
//=====================================================================================================
1400 
 
1401 
//Retry Buffer
1402 
generate
1403 
    for(f=0;f<FPW;f=f+1)begin : retry_buffer_gen
1404 
        openhmc_ram #(
1405 15 juko 
            .DATASIZE(128+3),      //FLIT + tail/hdr/valid indicator
1406 11 juko 
            .ADDRSIZE(RAM_ADDR_SIZE)
1407 
        )
1408 
        retry_buffer_per_lane_I
1409 
        (
1410 
            .clk(clk),
1411 15 juko 
            .wen(ram_w_en[f]),
1412 11 juko 
            .wdata(ram_w_data[f]),
1413 15 juko 
            .waddr(tx_frp_adr[f]),
1414 11 juko 
            .ren(ram_r_en),
1415 
            .raddr(ram_r_addr_temp),
1416 
            .rdata(ram_r_data[f])
1417 
        );
1418 
    end
1419 
endgenerate
1420 
 
1421 
//HMC CRC Logic
1422 
tx_crc_combine #(
1423 
    .DWIDTH(DWIDTH),
1424 
    .FPW(FPW),
1425 
    .LOG_FPW(LOG_FPW)
1426 
)
1427 
tx_crc_combine_I
1428 
(
1429 
    .clk(clk),
1430 
    .res_n(res_n),
1431 
    .d_in_hdr(data2crc_flit_is_hdr),
1432 
    .d_in_tail(data2crc_flit_is_tail),
1433 
    .d_in_data(data2crc),
1434 
    .d_out_data(data_rdy)
1435 
);
1436 
 
1437 
//Scrambler
1438 
generate
1439 
    for(n=0;n<NUM_LANES;n=n+1) begin : scrambler_gen
1440 
        tx_scrambler #(
1441 
            .LANE_WIDTH(LANE_WIDTH),
1442 
            .HMC_RX_AC_COUPLED(HMC_RX_AC_COUPLED)
1443 
        )
1444 
        scrambler_I
1445 
        (
1446 
            .clk(clk),
1447 
            .res_n(res_n),
1448 
            .disable_scrambler(rf_scrambler_disable),
1449 
            .seed(seed_lane[n]), // unique per lane
1450 
            .data_in(data_to_scrambler[n*LANE_WIDTH+LANE_WIDTH-1:n*LANE_WIDTH]),
1451 
            .data_out(phy_scrambled_data_out[n*LANE_WIDTH+LANE_WIDTH-1:n*LANE_WIDTH]),
1452 
            .rf_run_length_enable(rf_run_length_enable && ~rf_scrambler_disable),
1453 
            .rf_run_length_bit_flip(bit_was_flipped[n])
1454 
        );
1455 
    end
1456 
endgenerate
1457 
 
1458 
endmodule
1459 
`default_nettype wire

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