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[/] [openhmc/] [trunk/] [openHMC/] [sim/] [UVC/] [cag_rgm/] [sv/] [cag_rgm_defines.svh] - Blame information for rev 12

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1 12 juko 
/*
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 *                              .--------------. .----------------. .------------.
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 *                             | .------------. | .--------------. | .----------. |
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 *                             | | ____  ____ | | | ____    ____ | | |   ______ | |
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 *                             | ||_   ||   _|| | ||_   \  /   _|| | | .' ___  || |
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 *       ___  _ __   ___ _ __  | |  | |__| |  | | |  |   \/   |  | | |/ .'   \_|| |
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 *      / _ \| '_ \ / _ \ '_ \ | |  |  __  |  | | |  | |\  /| |  | | || |       | |
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 *       (_) | |_) |  __/ | | || | _| |  | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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 *      \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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 *           | |               | |            | | |              | | |          | |
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 *           |_|               | '------------' | '--------------' | '----------' |
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 *                              '--------------' '----------------' '------------'
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 *
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 *  openHMC - An Open Source Hybrid Memory Cube Controller
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 *  (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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 *  www.ziti.uni-heidelberg.de
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 *  B6, 26
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 *  68159 Mannheim
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 *  Germany
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 *
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 *  Contact: openhmc@ziti.uni-heidelberg.de
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 *  http://ra.ziti.uni-heidelberg.de/openhmc
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 *
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 *   This source file is free software: you can redistribute it and/or modify
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 *   it under the terms of the GNU Lesser General Public License as published by
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 *   the Free Software Foundation, either version 3 of the License, or
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 *   (at your option) any later version.
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 *
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 *   This source file is distributed in the hope that it will be useful,
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 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *   GNU Lesser General Public License for more details.
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 *
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 *   You should have received a copy of the GNU Lesser General Public License
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 *   along with this source file.  If not, see .
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 *
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 *
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 */
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typedef enum {
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    NONE,
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    CONTAINER,
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    REPEAT_BLOCK,
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    REGISTER,
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    RAM,
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    REGISTER_FILE
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} CAG_RGM_TYPE;
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typedef enum {
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    CAG_RGM_UNDEFINED,
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    CAG_RGM_READ,
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    CAG_RGM_WRITE,
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    CAG_RGM_READ_RESPONSE,
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    CAG_RGM_WRITE_RESPONSE
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} CAG_RGM_TRANSFER_COMMAND;
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typedef enum {
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    SINGLE,
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    ALL
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} CAG_RGM_MODE;
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`define cag_rgm_register_fields(T) \
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rand T fields;
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`define cag_rgm_driver_utils_start \
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task start_rf(); \
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    super.start_rf(); \
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    fork
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`define cag_rgm_driver_utils_end \
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    join \
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endtask : start_rf
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`define cag_rgm_driver_field_reg_begin(TYPE,PATH,NAME) \
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begin \
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        TYPE m_reg; \
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    $cast(m_reg,rf_model.get_by_name(PATH)); \
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    if( m_reg == null ) \
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        uvm_report_fatal(get_type_name(),{PATH," not found"});\
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    forever begin \
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        wait(!vif.res_n); \
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        vif.NAME <= {16{1'b0}}; \
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        @(posedge vif.res_n); \
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        fork \
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            @(negedge vif.res_n); \
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            begin \
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                forever begin \
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                    @(posedge vif.clk);
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`define cag_rgm_driver_field_reg_no_reset_begin(TYPE,PATH) \
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begin \
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        TYPE m_reg; \
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    $cast(m_reg,rf_model.get_by_name(PATH)); \
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    if( m_reg == null ) \
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        uvm_report_fatal(get_type_name(),{PATH," not found"});\
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    forever begin \
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        wait(!vif.res_n); \
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        @(posedge vif.res_n); \
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        fork \
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            @(negedge vif.res_n); \
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            begin \
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                forever begin \
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                    @(posedge vif.clk);
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`define cag_rgm_driver_field_reg_end \
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                end \
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            end \
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        join_any \
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        disable fork; \
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    end \
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end
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`define cag_rgm_driver_reg_ro(TYPE,PATH,NAME,FIELD) \
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        `cag_rgm_driver_field_reg_begin(TYPE,PATH,NAME) \
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                vif.NAME <= m_reg.fields.FIELD; \
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        `cag_rgm_driver_field_reg_end
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`define cag_rgm_driver_reg_wo(TYPE,PATH,NAME,FIELD) \
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        `cag_rgm_driver_field_reg_no_reset_begin(TYPE,PATH) \
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                m_reg.fields.FIELD = vif.NAME``_next; \
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        `cag_rgm_driver_field_reg_end
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`define cag_rgm_driver_reg_wo_en(TYPE,PATH,NAME,FIELD) \
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        `cag_rgm_driver_field_reg_begin(TYPE,PATH,NAME) \
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                if(vif.NAME``_wen) \
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                        m_reg.fields.FIELD = vif.NAME; \
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        `cag_rgm_driver_field_reg_end
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`define cag_rgm_driver_reg_rw(TYPE,PATH,NAME,FIELD) \
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        `cag_rgm_driver_field_reg_begin(TYPE,PATH,NAME) \
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                vif.NAME <= m_reg.fields.FIELD; \
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                m_reg.fields.FIELD = vif.NAME; \
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        `cag_rgm_driver_field_reg_end
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`define cag_rgm_driver_reg_rw_en(TYPE,PATH,NAME,FIELD) \
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        `cag_rgm_driver_field_reg_begin(TYPE,PATH,NAME) \
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                vif.NAME <= m_reg.fields.FIELD; \
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                if(vif.NAME``_wen) \
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                        m_reg.fields.FIELD = vif.NAME; \
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        `cag_rgm_driver_field_reg_end
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`define cag_rgm_driver_ram_int(TYPE,PATH,NAME,WIDTH) \
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    begin \
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        TYPE m_ram; \
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        bit [WIDTH-1:0] ram_address; \
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        bit enable = 0; \
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        $cast(m_ram,rf_model.get_by_name(PATH)); \
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        if( m_ram == null ) \
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            uvm_report_fatal(get_type_name(),{PATH," not found"}); \
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        forever begin \
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                enable = vif.NAME``_ren; \
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                if(enable) \
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                        ram_address = vif.NAME``_rf_addr; \
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                @(posedge vif.clk); \
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                if(enable) \
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                        vif.NAME``_rdata <= m_ram.get_entry(ram_address); \
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                ->m_ram.write_done; \
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        end \
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    end
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`define cag_rgm_driver_ram_ext(TYPE,PATH,NAME) \
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    begin \
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        TYPE m_ram; \
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        int unsigned entry; \
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        $cast(m_ram,rf_model.get_by_name(PATH)); \
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        if( m_ram == null ) \
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            uvm_report_fatal(get_type_name(),{PATH," not found"}); \
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        vif.NAME``_rf_wen <= 1'b0; \
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        vif.NAME``_rf_ren <= 1'b0; \
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        forever begin \
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                @(m_ram.read_event or m_ram.write_event); \
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                @(posedge vif.clk); \
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                entry = m_ram.entry; \
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                vif.NAME``_rf_addr <= entry; \
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                if(m_ram.read_write) begin \
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                        vif.NAME``_rf_wdata <= m_ram.get_entry(entry); \
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                        vif.NAME``_rf_wen   <= 1'b1; \
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                end else begin \
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                        vif.NAME``_rf_ren <= 1'b1; \
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                end \
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                @(posedge vif.clk); \
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                vif.NAME``_rf_wen <= 1'b0; \
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                while(!vif.NAME``_rf_access_complete) \
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                        @(posedge vif.clk); \
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                vif.NAME``_rf_wen <= 1'b0; \
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                vif.NAME``_rf_ren <= 1'b0; \
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                if(!m_ram.read_write) \
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                        m_ram.set_entry(vif.NAME``_rf_rdata, entry ); \
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                ->m_ram.write_done; \
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        end \
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    end
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