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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see .
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*
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*
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*/
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//
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//
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// register file interface
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//
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//
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`ifndef CAG_RGM_RFS_IF_SV
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`define CAG_RGM_RFS_IF_SV
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interface cag_rgm_rfs_if #(
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parameter ADDR_WIDTH = 6,
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parameter WRITE_DATA_WIDTH = 64,
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parameter READ_DATA_WIDTH = 64
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) ();
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logic res_n;
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logic clk;
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logic [ADDR_WIDTH-1:0] address;
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logic wen;
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logic ren;
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logic [WRITE_DATA_WIDTH-1:0] write_data;
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logic [READ_DATA_WIDTH-1:0] read_data;
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logic access_done;
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logic invalid_address;
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property valid_wen;
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@(posedge clk) disable iff(!res_n)
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wen |-> !$isunknown(address) && !$isunknown(write_data);
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endproperty : valid_wen
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assert property(valid_wen);
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property valid_ren;
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@(posedge clk) disable iff(!res_n)
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ren |-> !$isunknown(address);
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endproperty : valid_ren
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assert property(valid_ren);
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property valid_access_done;
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@(posedge clk) disable iff(!res_n)
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wen || ren |=> !(wen || ren) [*0:1150] ##1 access_done;
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endproperty : valid_access_done
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assert property(valid_access_done);
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access_done_one_clk : assert property(@(posedge clk) disable iff(!res_n) $rose(access_done) |=> !access_done );
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property invalid_address_on_done_only;
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@(posedge clk) disable iff(!res_n)
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invalid_address |-> access_done;
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endproperty : invalid_address_on_done_only
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assert property(invalid_address_on_done_only);
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property no_simultaneous_read_and_write_on_0;
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@(posedge clk) disable iff(!res_n)
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ren |-> !wen;
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endproperty : no_simultaneous_read_and_write_on_0
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assert property(no_simultaneous_read_and_write_on_0);
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property no_simultaneous_read_and_write_on_1;
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@(posedge clk) disable iff(!res_n)
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wen |-> !ren;
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endproperty : no_simultaneous_read_and_write_on_1
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assert property(no_simultaneous_read_and_write_on_1);
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endinterface : cag_rgm_rfs_if
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`endif // CAG_RGM_RFS_IF_SV
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