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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see .
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*
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*
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*/
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//
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//
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// cag rgm rfs monitor OVC monitor
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//
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//
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`ifndef CAG_RGM_RFS_MONITOR_SV
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`define CAG_RGM_RFS_MONITOR_SV
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class cag_rgm_rfs_monitor #(
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parameter ADDR_WIDTH = 6,
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parameter READ_DATA_WIDTH = 64,
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parameter WRITE_DATA_WIDTH = 64
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) extends uvm_monitor;
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uvm_analysis_port #(cag_rgm_transfer) request_port;
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uvm_analysis_port #(cag_rgm_transfer) response_port;
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virtual cag_rgm_rfs_if #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.READ_DATA_WIDTH(READ_DATA_WIDTH),
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.WRITE_DATA_WIDTH(WRITE_DATA_WIDTH)
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) rfs_if;
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cag_rgm_transfer collected_request;
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cag_rgm_transfer collected_response;
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bit enable_coverage = 1;
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bit enable_checks = 1;
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int cycles_between_req = 0;
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int cycles_between_resp = 0;
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`uvm_component_param_utils_begin(cag_rgm_rfs_monitor #(.ADDR_WIDTH(ADDR_WIDTH), .READ_DATA_WIDTH(READ_DATA_WIDTH), .WRITE_DATA_WIDTH(WRITE_DATA_WIDTH)))
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`uvm_field_int(enable_coverage, UVM_ALL_ON)
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`uvm_field_int(enable_checks, UVM_ALL_ON)
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`uvm_component_utils_end
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function new ( string name="cag_rgm_rfs_monitor", uvm_component parent );
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super.new(name, parent);
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request_port = new("request_port", this);
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response_port = new("response_port", this);
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endfunction : new
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function void assign_vi( virtual interface cag_rgm_rfs_if #(.ADDR_WIDTH(ADDR_WIDTH), .READ_DATA_WIDTH(READ_DATA_WIDTH), .WRITE_DATA_WIDTH(WRITE_DATA_WIDTH)) rfs_if );
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this.rfs_if = rfs_if;
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endfunction : assign_vi
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task run();
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#1;
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do_reset();
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fork
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collect_request_transfers();
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collect_response_transfers();
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join_none
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endtask : run
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task do_reset();
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while (rfs_if.res_n == 0)
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@( posedge rfs_if.clk );
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endtask : do_reset
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task collect_request_transfers();
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forever
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begin
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cycles_between_req = 0;
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// wait for write or read enable
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while (!(rfs_if.wen || rfs_if.ren)) begin
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cycles_between_req++;
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@(posedge rfs_if.clk);
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end
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collected_request = cag_rgm_transfer::type_id::create("collected_request", this);
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if(recording_detail == UVM_FULL)
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collected_request.enable_recording({get_full_name(),"_request"});
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void'(collected_request.begin_tr());
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if (rfs_if.ren)
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collected_request.command = CAG_RGM_READ;
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else
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collected_request.command = CAG_RGM_WRITE;
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collected_request.address = {{64-3-ADDR_WIDTH {1'b0}}, rfs_if.address,3'b0};
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collected_request.data = rfs_if.write_data;
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collected_request.delay = cycles_between_req;
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collected_request.error = 1'b0;
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@(posedge rfs_if.clk);
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if (enable_checks)
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perform_request_checks();
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if (enable_coverage)
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perform_request_coverage();
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void'(collected_request.end_tr());
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// forward the collected_request to the next higher layer of the verification environment
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// collected_request.print();
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request_port.write(collected_request);
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end
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endtask : collect_request_transfers
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task collect_response_transfers();
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forever begin
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cycles_between_resp = 0;
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while (!(rfs_if.wen || rfs_if.ren)) begin
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@(posedge rfs_if.clk);
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end
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collected_response = cag_rgm_transfer::type_id::create("collected_response", this);
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if(rfs_if.wen)
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collected_response.command = CAG_RGM_WRITE_RESPONSE;
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else
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collected_response.command = CAG_RGM_READ_RESPONSE;
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// wait for write or read enable
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while (!rfs_if.access_done) begin
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cycles_between_resp++;
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@(posedge rfs_if.clk);
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end
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if(recording_detail == UVM_FULL)
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collected_response.enable_recording({get_full_name(),"_response"});
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void'(collected_response.begin_tr());
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collected_response.address = {{64-ADDR_WIDTH {1'b0}}, rfs_if.address}; //-- FIXME? address should be byte aligned? not qw?
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collected_response.data = rfs_if.read_data;
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collected_response.delay = cycles_between_req;
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collected_response.error = rfs_if.invalid_address;
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@(posedge rfs_if.clk);
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if (enable_checks)
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perform_response_checks();
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if (enable_coverage)
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perform_response_coverage();
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void'(collected_response.end_tr());
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// forward the collected_response to the next higher layer of the verification environment
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// collected_response.print();
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response_port.write(collected_response);
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end
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endtask : collect_response_transfers
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// checks
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function void perform_request_checks();
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// perform data checks on collected_packet
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endfunction : perform_request_checks
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function void perform_response_checks();
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//-- perform data checks on collected_packet
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if(collected_response.error)
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uvm_report_fatal(get_type_name(),$psprintf("Invalid access to address 0x%0h",collected_response.address));
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endfunction : perform_response_checks
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// coverage
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function void perform_request_coverage();
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// perform coverage on collected_packet
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endfunction : perform_request_coverage
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function void perform_response_coverage();
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// perform coverage on collected_packet
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endfunction : perform_response_coverage
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endclass : cag_rgm_rfs_monitor
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`endif // CAG_RGM_RFS_MONITOR_SV
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