| 1 |
12 |
juko |
/*
|
| 2 |
|
|
* .--------------. .----------------. .------------.
|
| 3 |
|
|
* | .------------. | .--------------. | .----------. |
|
| 4 |
|
|
* | | ____ ____ | | | ____ ____ | | | ______ | |
|
| 5 |
|
|
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
|
| 6 |
|
|
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
|
| 7 |
|
|
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
|
| 8 |
|
|
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
|
| 9 |
|
|
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
|
| 10 |
|
|
* | | | | | | | | | | | |
|
| 11 |
|
|
* |_| | '------------' | '--------------' | '----------' |
|
| 12 |
|
|
* '--------------' '----------------' '------------'
|
| 13 |
|
|
*
|
| 14 |
|
|
* openHMC - An Open Source Hybrid Memory Cube Controller
|
| 15 |
|
|
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
|
| 16 |
|
|
* www.ziti.uni-heidelberg.de
|
| 17 |
|
|
* B6, 26
|
| 18 |
|
|
* 68159 Mannheim
|
| 19 |
|
|
* Germany
|
| 20 |
|
|
*
|
| 21 |
|
|
* Contact: openhmc@ziti.uni-heidelberg.de
|
| 22 |
|
|
* http://ra.ziti.uni-heidelberg.de/openhmc
|
| 23 |
|
|
*
|
| 24 |
|
|
* This source file is free software: you can redistribute it and/or modify
|
| 25 |
|
|
* it under the terms of the GNU Lesser General Public License as published by
|
| 26 |
|
|
* the Free Software Foundation, either version 3 of the License, or
|
| 27 |
|
|
* (at your option) any later version.
|
| 28 |
|
|
*
|
| 29 |
|
|
* This source file is distributed in the hope that it will be useful,
|
| 30 |
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 31 |
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 32 |
|
|
* GNU Lesser General Public License for more details.
|
| 33 |
|
|
*
|
| 34 |
|
|
* You should have received a copy of the GNU Lesser General Public License
|
| 35 |
|
|
* along with this source file. If not, see .
|
| 36 |
|
|
*
|
| 37 |
|
|
*
|
| 38 |
|
|
*/
|
| 39 |
|
|
|
| 40 |
|
|
`include "axi4_stream_pkg.sv"
|
| 41 |
|
|
`include "hmc_module_pkg.sv"
|
| 42 |
|
|
`include "cag_rgm_rfs_if.sv"
|
| 43 |
|
|
|
| 44 |
|
|
`timescale 100ps/10ps
|
| 45 |
|
|
|
| 46 |
|
|
module tb_top ();
|
| 47 |
|
|
|
| 48 |
|
|
import uvm_pkg::*;
|
| 49 |
|
|
|
| 50 |
|
|
//-- include the UVCs
|
| 51 |
|
|
import axi4_stream_pkg::*;
|
| 52 |
|
|
import hmc_module_pkg::*;
|
| 53 |
|
|
import hmc_base_types_pkg::*;
|
| 54 |
|
|
|
| 55 |
|
|
`include "cag_rgm.svh"
|
| 56 |
|
|
|
| 57 |
|
|
`ifdef X16
|
| 58 |
|
|
`include "register_file_model_16x.sv"
|
| 59 |
|
|
`else
|
| 60 |
|
|
`include "register_file_model_8x.sv"
|
| 61 |
|
|
`endif
|
| 62 |
|
|
|
| 63 |
|
|
`include "hmc_packet.sv"
|
| 64 |
|
|
`include "hmc_req_packet.sv"
|
| 65 |
|
|
//`include "hmc_req_posted_packet.sv"
|
| 66 |
|
|
`include "hmc_2_axi4_sequencer.sv"
|
| 67 |
|
|
`include "hmc_2_axi4_sequence.sv"
|
| 68 |
|
|
`include "tag_handler.sv"
|
| 69 |
|
|
|
| 70 |
|
|
`include "hmc_link_config.sv"
|
| 71 |
|
|
`include "hmc_vseqr.sv"
|
| 72 |
|
|
|
| 73 |
|
|
`include "axi4_stream_hmc_monitor.sv"
|
| 74 |
|
|
`include "bfm_2_hmc_monitor.sv"
|
| 75 |
|
|
|
| 76 |
|
|
`include "hmc_tb.sv"
|
| 77 |
|
|
|
| 78 |
|
|
`include "test_lib.sv"
|
| 79 |
|
|
|
| 80 |
|
|
logic res_n, clk_user, clk_hmc_refclk;
|
| 81 |
|
|
|
| 82 |
|
|
//-- instantiate the interfaces
|
| 83 |
|
|
axi4_stream_if #(
|
| 84 |
|
|
.DATA_BYTES(`AXI4BYTES),
|
| 85 |
|
|
.TUSER_WIDTH(`AXI4BYTES)
|
| 86 |
|
|
) axi4_hmc_req_if(
|
| 87 |
|
|
.ACLK(clk_user),
|
| 88 |
|
|
.ARESET_N(res_n)
|
| 89 |
|
|
);
|
| 90 |
|
|
|
| 91 |
|
|
axi4_stream_if #(
|
| 92 |
|
|
.DATA_BYTES(`AXI4BYTES),
|
| 93 |
|
|
.TUSER_WIDTH(`AXI4BYTES)
|
| 94 |
|
|
) axi4_hmc_rsp_if(
|
| 95 |
|
|
.ACLK(clk_user),
|
| 96 |
|
|
.ARESET_N(res_n)
|
| 97 |
|
|
);
|
| 98 |
|
|
|
| 99 |
|
|
cag_rgm_rfs_if #(
|
| 100 |
|
|
.ADDR_WIDTH(`RFS_HMC_CONTROLLER_RF_AWIDTH),
|
| 101 |
|
|
.READ_DATA_WIDTH(`RFS_HMC_CONTROLLER_RF_RWIDTH),
|
| 102 |
|
|
.WRITE_DATA_WIDTH(`RFS_HMC_CONTROLLER_RF_WWIDTH)
|
| 103 |
|
|
) rfs_hmc_if();
|
| 104 |
|
|
|
| 105 |
|
|
dut dut_I (
|
| 106 |
|
|
.clk_user(clk_user),
|
| 107 |
|
|
.clk_hmc_refclk(clk_hmc_refclk),
|
| 108 |
|
|
.res_n(res_n),
|
| 109 |
|
|
|
| 110 |
|
|
.axi4_req(axi4_hmc_req_if),
|
| 111 |
|
|
.axi4_rsp(axi4_hmc_rsp_if),
|
| 112 |
|
|
|
| 113 |
|
|
.rfs_hmc(rfs_hmc_if)
|
| 114 |
|
|
);
|
| 115 |
|
|
|
| 116 |
|
|
initial begin
|
| 117 |
|
|
|
| 118 |
|
|
uvm_config_db#(virtual axi4_stream_if #(.DATA_BYTES(`AXI4BYTES), .TUSER_WIDTH(`AXI4BYTES)))::set(null, "uvm_test_top.hmc_tb0.axi4_req", "vif", axi4_hmc_req_if);
|
| 119 |
|
|
uvm_config_db#(virtual axi4_stream_if #(.DATA_BYTES(`AXI4BYTES), .TUSER_WIDTH(`AXI4BYTES)))::set(null, "uvm_test_top.hmc_tb0.axi4_rsp", "vif", axi4_hmc_rsp_if);
|
| 120 |
|
|
|
| 121 |
|
|
//-- connect the BFM monitors with the Module UVC BFM to HMC Packet monitors
|
| 122 |
|
|
uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_req_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_rsp_pkt[0]);
|
| 123 |
|
|
uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_rsp_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_req_pkt[0]);
|
| 124 |
|
|
|
| 125 |
|
|
//uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_req_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_req_pkt_err_cov[0]);
|
| 126 |
|
|
//uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_rsp_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_rsp_pkt_err_cov[0]);
|
| 127 |
|
|
|
| 128 |
|
|
run_test();
|
| 129 |
|
|
end
|
| 130 |
|
|
|
| 131 |
|
|
initial begin
|
| 132 |
|
|
clk_user <= 1'b1;
|
| 133 |
|
|
clk_hmc_refclk <= 1'b1;
|
| 134 |
|
|
res_n <= 1'b0;
|
| 135 |
|
|
#1000ns
|
| 136 |
|
|
@(posedge clk_user) res_n <= 1'b1;
|
| 137 |
|
|
end
|
| 138 |
|
|
|
| 139 |
|
|
//-- Generate the user clock
|
| 140 |
|
|
always begin
|
| 141 |
|
|
case(`FPW)
|
| 142 |
|
|
2: begin
|
| 143 |
|
|
if(`LOG_NUM_LANES==3) //8lanes
|
| 144 |
|
|
#1.6ns clk_user = !clk_user;
|
| 145 |
|
|
else begin
|
| 146 |
|
|
#0.8ns clk_user = !clk_user;
|
| 147 |
|
|
end
|
| 148 |
|
|
end
|
| 149 |
|
|
4: begin
|
| 150 |
|
|
if(`LOG_NUM_LANES==3) //8lanes
|
| 151 |
|
|
#3.2ns clk_user = !clk_user;
|
| 152 |
|
|
else
|
| 153 |
|
|
#1.6ns clk_user = !clk_user;
|
| 154 |
|
|
end
|
| 155 |
|
|
6: begin
|
| 156 |
|
|
if(`LOG_NUM_LANES==3) //8lanes
|
| 157 |
|
|
#4.8ns clk_user = !clk_user;
|
| 158 |
|
|
else
|
| 159 |
|
|
#2.4ns clk_user = !clk_user;
|
| 160 |
|
|
end
|
| 161 |
|
|
8: begin
|
| 162 |
|
|
if(`LOG_NUM_LANES==3) //8lanes
|
| 163 |
|
|
#6.4ns clk_user = !clk_user;
|
| 164 |
|
|
else
|
| 165 |
|
|
#3.2ns clk_user = !clk_user;
|
| 166 |
|
|
end
|
| 167 |
|
|
endcase
|
| 168 |
|
|
end
|
| 169 |
|
|
|
| 170 |
|
|
//-- 125 MHz
|
| 171 |
|
|
always #4ns clk_hmc_refclk <= ~clk_hmc_refclk;
|
| 172 |
|
|
|
| 173 |
|
|
endmodule : tb_top
|
