OpenCores
URL https://opencores.org/ocsvn/openhmc/openhmc/trunk

Subversion Repositories openhmc

[/] [openhmc/] [trunk/] [openHMC/] [sim/] [tb/] [common/] [src/] [serdes/] [behavioral/] [deserializer.v] - Blame information for rev 15

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 juko
/*
2
 *                              .--------------. .----------------. .------------.
3
 *                             | .------------. | .--------------. | .----------. |
4
 *                             | | ____  ____ | | | ____    ____ | | |   ______ | |
5
 *                             | ||_   ||   _|| | ||_   \  /   _|| | | .' ___  || |
6
 *       ___  _ __   ___ _ __  | |  | |__| |  | | |  |   \/   |  | | |/ .'   \_|| |
7
 *      / _ \| '_ \ / _ \ '_ \ | |  |  __  |  | | |  | |\  /| |  | | || |       | |
8
 *       (_) | |_) |  __/ | | || | _| |  | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
9
 *      \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
10
 *           | |               | |            | | |              | | |          | |
11
 *           |_|               | '------------' | '--------------' | '----------' |
12
 *                              '--------------' '----------------' '------------'
13
 *
14
 *  openHMC - An Open Source Hybrid Memory Cube Controller
15
 *  (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
16
 *  www.ziti.uni-heidelberg.de
17
 *  B6, 26
18
 *  68159 Mannheim
19
 *  Germany
20
 *
21
 *  Contact: openhmc@ziti.uni-heidelberg.de
22
 *  http://ra.ziti.uni-heidelberg.de/openhmc
23
 *
24
 *   This source file is free software: you can redistribute it and/or modify
25
 *   it under the terms of the GNU Lesser General Public License as published by
26
 *   the Free Software Foundation, either version 3 of the License, or
27
 *   (at your option) any later version.
28
 *
29
 *   This source file is distributed in the hope that it will be useful,
30
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
31
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
32
 *   GNU Lesser General Public License for more details.
33
 *
34
 *   You should have received a copy of the GNU Lesser General Public License
35
 *   along with this source file.  If not, see <http://www.gnu.org/licenses/>.
36
 *
37
 *
38
 */
39
module deserializer #(
40
        parameter LOG_DWIDTH=7,
41
        parameter DWIDTH=64
42
)
43
(
44
        input  wire                     clk,
45
        input  wire                     res_n,
46
        input  wire                     fast_clk,
47
        input  wire                     bit_slip,
48
        input  wire                     data_in,
49
        output wire [DWIDTH-1:0]data_out,
50
        input  wire                     lane_polarity
51
);
52
 
53
reg [DWIDTH-1:0]         tmp_buffer;
54
reg [DWIDTH-1:0]         buffer;
55
reg [DWIDTH-1:0]         buffer2;
56
reg [DWIDTH-1:0]         data_out_temp;
57
reg [LOG_DWIDTH-1:0]curr_bit = 'h0;
58
reg [5:0]                        bit_slip_cnt;
59
reg                             bit_slip_done = 1'b0;
60
 
61
reg d_in_dly;
62
 
63
assign data_out = lane_polarity ? data_out_temp^{DWIDTH{1'b1}} : data_out_temp;
64
 
65
// SEQUENTIAL PROCESS
66
always @ (posedge fast_clk) begin
67
        if(!res_n) begin
68
                curr_bit                <= {LOG_DWIDTH{1'b0}};
69
                bit_slip_done   <= 1'b0;
70
        end else begin
71
 
72
                #1ps d_in_dly <= data_in;
73
 
74
                if (!bit_slip || bit_slip_done) begin
75
                        if(curr_bit == DWIDTH-1) begin
76
                                curr_bit <= 0;
77
                        end else begin
78
                                curr_bit         <= curr_bit + 1;
79
                        end
80
                end
81
 
82
                if (bit_slip && !bit_slip_done)
83
                        bit_slip_done <= 1'b1;
84
 
85
                if (bit_slip_done && !bit_slip)
86
                        bit_slip_done <= 1'b0;
87
 
88
                if (|curr_bit == 1'b0) begin
89
                        buffer <= tmp_buffer;
90
                end
91
                tmp_buffer[curr_bit] <= d_in_dly;
92
        end
93
end
94
 
95
always @ (posedge clk) begin
96
        if(!res_n) begin
97
                bit_slip_cnt <= 6'h0;
98
        end else begin
99
                if(bit_slip)
100
                        bit_slip_cnt <= bit_slip_cnt + 1;
101
 
102
                buffer2 <= buffer;
103
 
104
                if(bit_slip_cnt < DWIDTH-1) begin
105
                        data_out_temp <= buffer2;
106
                end else begin
107
                        data_out_temp <= buffer;
108
                end
109
        end
110
end
111
 
112
endmodule
113
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.