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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see .
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*
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*
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*/
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`include "axi4_stream_pkg.sv"
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`include "hmc_pkg.sv"
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`include "hmc_module_pkg.sv"
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`include "cag_rgm_rfs_if.sv"
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`timescale 100ps/1ps
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module tb_top ();
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import uvm_pkg::*;
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//-- include the UVCs
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import axi4_stream_pkg::*;
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import hmc_pkg::*;
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import hmc_module_pkg::*;
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import hmc_base_types_pkg::*;
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`include "cag_rgm.svh"
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`ifdef X16
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`include "register_file_model_16x.sv"
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`else
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`include "register_file_model_8x.sv"
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`endif
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`include "hmc_packet.sv"
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`include "hmc_req_packet.sv"
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`include "hmc_2_axi4_sequencer.sv"
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`include "hmc_2_axi4_sequence.sv"
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`include "tag_handler.sv"
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`include "hmc_vseqr.sv"
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`include "axi4_stream_hmc_monitor.sv"
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`include "hmc_tb.sv"
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`include "test_lib.sv"
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logic res_n, clk_user, clk_hmc_refclk;
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//-- instantiate the interfaces
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axi4_stream_if #(
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.DATA_BYTES(`AXI4BYTES),
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.TUSER_WIDTH(`AXI4BYTES)
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) axi4_hmc_req_if();
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axi4_stream_if #(
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.DATA_BYTES(`AXI4BYTES),
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.TUSER_WIDTH(`AXI4BYTES)
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) axi4_hmc_rsp_if();
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cag_rgm_rfs_if #(
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.ADDR_WIDTH(`RFS_OPENHMC_RF_AWIDTH),
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.READ_DATA_WIDTH(`RFS_OPENHMC_RF_RWIDTH),
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.WRITE_DATA_WIDTH(`RFS_OPENHMC_RF_WWIDTH)
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) rfs_hmc_if();
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hmc_sr_if#(.NUM_LANES(2**`LOG_NUM_LANES)) hmc_if();
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hmc_sr_if#(.NUM_LANES(2**`LOG_NUM_LANES)) hmc_int_if();
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dut dut_I (
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.clk_user(clk_user),
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.clk_hmc_refclk(clk_hmc_refclk),
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.res_n(res_n),
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.hmc(hmc_if),
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.axi4_req(axi4_hmc_req_if),
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.axi4_rsp(axi4_hmc_rsp_if),
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.rfs_hmc(rfs_hmc_if)
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);
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assign hmc_int_if.REFCLK_BOOT = hmc_if.REFCLK_BOOT;
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assign hmc_int_if.REFCLKN = hmc_if.REFCLKN;
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assign hmc_int_if.REFCLKP = hmc_if.REFCLKP;
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assign hmc_int_if.P_RST_N = hmc_if.P_RST_N;
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assign hmc_int_if.RXPS = hmc_if.RXPS;
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assign hmc_if.TXPS = hmc_int_if.TXPS;
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assign hmc_if.FERR_N = hmc_int_if.FERR_N;
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initial begin
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uvm_config_db#(virtual axi4_stream_if #(.DATA_BYTES(`AXI4BYTES), .TUSER_WIDTH(`AXI4BYTES)))::set(null, "uvm_test_top.hmc_tb0.axi4_req", "vif", axi4_hmc_req_if);
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uvm_config_db#(virtual axi4_stream_if #(.DATA_BYTES(`AXI4BYTES), .TUSER_WIDTH(`AXI4BYTES)))::set(null, "uvm_test_top.hmc_tb0.axi4_rsp", "vif", axi4_hmc_rsp_if);
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//hmc_link interfaces
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uvm_config_db#(virtual hmc_sr_if#(.NUM_LANES(2**`LOG_NUM_LANES)))::set(null, "uvm_test_top.hmc_tb0.hmc", "vif", hmc_if);
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uvm_config_db#(virtual hmc_sr_if#(.NUM_LANES(2**`LOG_NUM_LANES)))::set(null, "uvm_test_top.hmc_tb0.hmc", "int_vif", hmc_int_if);
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run_test();
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end
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initial begin
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clk_user <= 1'b1;
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clk_hmc_refclk <= 1'b1;
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res_n <= 1'b0;
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#500ns;
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@(posedge clk_user) res_n <= 1'b1;
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end
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//-- Generate the user clock
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always begin
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case(`FPW)
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2: begin
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if(`LOG_NUM_LANES==3) //8lanes
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#1.6ns clk_user = !clk_user;
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else begin
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#0.8ns clk_user = !clk_user;
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end
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end
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4: begin
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if(`LOG_NUM_LANES==3) //8lanes
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#3.2ns clk_user = !clk_user;
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else
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#1.6ns clk_user = !clk_user;
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end
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6: begin
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if(`LOG_NUM_LANES==3) //8lanes
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#4.8ns clk_user = !clk_user;
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else
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#2.4ns clk_user = !clk_user;
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end
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8: begin
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if(`LOG_NUM_LANES==3) //8lanes
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#6.4ns clk_user = !clk_user;
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else
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#3.2ns clk_user = !clk_user;
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end
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endcase
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end
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//-- 125 MHz HMC/Transceiver refclock
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always #4ns clk_hmc_refclk <= ~clk_hmc_refclk;
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endmodule : tb_top
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